WO2012066696A1

WO2012066696A1 - Level shift circuit having delay function, digital-analog hybrid semiconductor integrated circuit, and delay circuit

Info

Publication number: WO2012066696A1
Application number: PCT/JP2011/002870
Authority: WO
Inventors: 後藤　陽介; 進一荻田; 文人犬飼
Original assignee: パナソニック株式会社
Priority date: 2010-11-19
Filing date: 2011-05-24
Publication date: 2012-05-24

Abstract

A level shift circuit of the present invention, said level shift circuit having a delay function, is provided with: a differential clock signal input circuit (3), which is provided with NMOS transistors (N1, N2), and is configured such that one differential output terminal of a differential clock signal generating circuit (1) is connected to the gate of an NMOS transistor (N1), and the other differential output terminal is connected to the gate of an NMOS transistor (N2); a latch circuit (4), which is configured such that the latch circuit latches the drain-side potentials of the NMOS transistors (N1, N2), and that analog clock signals are outputted from at least one of the drains of the NMOS transistors (N1, N2); and a capacitor (C1), which has both the terminals connected to between the gates of the NMOS transistors (N1, N2), and which forms a low-pass filter with the output impedance of the differential clock signal generating circuit (1).

Description

Level shift circuit with delay function, digital-analog mixed semiconductor integrated circuit, and delay circuit

The present invention relates to a level shift circuit with a delay function, a digital-analog mixed semiconductor integrated circuit, and a delay circuit, and more particularly to prevention of interference of clock signals in an analog-digital converter and a digital-analog converter. is there.

In recent years, with the progress of miniaturization of the semiconductor manufacturing process and the price reduction of electronic devices, many digital-analog mixed type semiconductor integrated circuits in which a digital circuit and an analog circuit are realized by one semiconductor chip have been designed. A typical example is an IC in which an analog-digital converter (hereinafter referred to as AD converter) or a digital-analog converter (hereinafter referred to as DA converter) used for voice processing or sensors is mounted.

By the way, with the integration of the digital circuit and the analog circuit into one chip, digital noise may spread to the analog circuit through the common impedance of the power supply wiring and the like, and the characteristics of the analog circuit may be deteriorated. For this reason, generally, measures are taken to make the power supply wiring independent between the digital circuit and the analog circuit, and for electrical connection between the digital circuit and the analog circuit where different power supplies are used. A level shift circuit is used. The level shift circuit is configured, for example, as shown in

Patent Documents

1 and 2, and is used to switch the amplitude of a digital signal between two different power sources.

A level shift circuit 700 illustrated in FIG. 17 corresponds to the configuration illustrated in FIG. 1 of Patent Document 1, and the like, and is driven by the input-side power supply voltage [VDDI−VSSI] and based on a signal input to the input terminal IN. The differential clock signal generation circuit 1 for generating the differential clock signals INO and INOB, one differential clock signal INO is input to the gate, the source is connected to the input side ground terminal VSSI, and the gate is The other differential clock signal INOB is inputted, the source is connected to the input side ground terminal VSSI, the NMOS transistor N2, the source is connected to the output side power supply terminal VDDO, the drain is connected to the drain of the NMOS transistor N1, and the gate A PMOS transistor P1 connected to the drain of the NMOS transistor N2, The source is connected to the output side power supply terminal VDDO, the drain is connected to the drain of the NMOS transistor N2, the gate is connected to the drain of the NMOS transistor N1, and the output side power supply voltage [VDDO-VSSO] is driven. And an inverter circuit 2 having an input terminal connected to the drain of the NMOS transistor N2 and an output terminal connected to the output terminal OUT.

A level shift circuit 800 shown in FIG. 18 corresponds to the configuration shown in FIG. 1 of Patent Document 2, and the like. The level shift circuit 800 is driven by the input-side power supply voltage [VDDL−VSSL] and is based on a signal input to the input terminal IN. A differential clock signal generation circuit 1 for generating dynamic clock signals XINO and XINOB, a pair of NMOS transistors N1 and N2 whose differential clock signals XINO and XINOB are input to their gates, and their gates connected to the output side power supply terminal VDDH The source is connected to the drains of the NMOS transistors N1 and N2, a pair of NMOS transistors N5 and N6 operating as a protection circuit, the source is connected to the output side power supply potential VDDH, and the drain is connected to the drains of the NMOS transistors N5 and N6. The gate is connected to the output terminals of the

inverter circuits

9 and 10, and the power supply circuit A pair of PMOS transistors P1 and P2, the resistor R1 provided between the drains of the PMOS transistors P1 and P2, the drain connected to the sources of the NMOS transistors N1 and N2, and the source to the input-side power supply potential VSSL Connected, the gate is connected to the output terminals of the

inverter circuits

9 and 10, driven by a pair of NMOS transistors N3 and N4 operating as an intermittent circuit, and the output side power supply voltage [VDDH-VSSH], and the input terminal is NMOS transistor N5 , N6, and NAND circuits 7 and 8 whose output terminals are connected to the output terminal OUT, and inverter circuits which are driven by the output side power supply voltage [VDDH-VSSH] and whose input terminals are connected to the

output terminal OUT

9 and 10.

However, a level shift circuit as shown in FIGS. 17 and 18 and a measure for making the power supply wiring independent between the digital circuit and the analog circuit can completely suppress the digital noise from spreading to the analog circuit. Can not. In particular, in recent years, digital circuits have been increased in speed (higher frequency), and digital noise can easily spread to analog circuits through parasitic capacitance or the like that exists between the substrate and the wiring or between the wiring and the wiring. . Thus, measures such as providing a separation layer between the blocks are taken, but it is still difficult to completely block the path of the wraparound of digital noise.

Therefore, as a different viewpoint from countermeasures on the pattern layout, the fastest digital noise is caused by the digital clock signal, and the object that is most affected by the digital noise is the rise or fall of the analog clock signal. Measures that focus on the timing of falling are considered. For example,

Patent Documents

3 and 4 disclose that the influence of digital noise on an analog circuit is suppressed by shifting the phase between a digital clock signal and an analog clock signal. Specifically, as shown in FIG. 19, the digital clock signal output from the digital circuit 201 is converted into an analog clock signal having a different frequency in the analog clock signal generation circuit 202, and then analogized via the level shift circuit 203. Propagated to circuit 205. Here, in order to suppress the spread of digital noise, a delay circuit 204 is provided on the input side or output side of the level shift circuit 203. The delay circuit 204 is configured, for example, as shown in FIGS.

JP-A-11-195975 JP 2006-140884 A JP-A-6-162224 JP-A-9-153801

The delay circuit in FIG. 20 is configured to obtain a desired gate delay by connecting a plurality of inverter circuits INV0, INV1,... INVN in multiple stages. However, in this configuration, the area occupied by the IC increases in order to provide the necessary gate delay, and the inverter circuits INV0 to INVN are driven by a high-speed clock signal, which causes a problem that the transient current increases.

The delay circuit of FIG. 21 forms a low-pass filter formed by a resistor R and a capacitor C, blunts the waveform, and then shapes the waveform by a buffer circuit BF provided at the subsequent stage of the low-pass filter. It is configured to obtain a delay. However, in this configuration, a shift occurs between the delay at the rising edge of the waveform and the delay at the falling edge, and a clock signal whose duty ratio is lost with respect to the input waveform is output. Therefore, the delay circuit (buffer circuit BF) There is concern about the deterioration of the characteristics of the analog circuit in the latter stage.

The present invention has been made in order to solve the above-described conventional problems. The level shift with a delay function that delays an analog clock signal while maintaining a duty ratio while suppressing an increase in circuit area and current consumption. An object is to provide a circuit, a digital-analog mixed semiconductor integrated circuit, and a delay circuit.

To achieve the above object, a level shift circuit with a delay function according to the present invention has a first power supply voltage amplitude and generates a pair of complementary differential clock signals. A differential output terminal of one of the differential clock signal generation circuits is connected to a gate of the first NMOS transistor, and the differential clock signal generation circuit includes: a first NMOS transistor; A differential clock signal input circuit configured such that the other differential output terminal is connected to the gate of the second NMOS transistor, and on the drain side of the first NMOS transistor and the second NMOS transistor. Latching each potential, at least one of the drains of the first NMOS transistor and the second NMOS transistor A latch circuit configured to output an analog clock signal having an amplitude of a second power supply voltage different from the first power supply voltage, and gates of the first NMOS transistor and the second NMOS transistor And a capacitor that forms a low-pass filter together with an output impedance of the differential clock signal generation circuit, and the analog clock signal delays the differential clock signal through the low-pass filter. It is made up of.

According to the above configuration, a low-pass filter is formed by the output impedance of the differential clock signal generation circuit and the capacitor, and the delay is reduced by blunting the waveform of the differential clock signal output from the differential clock signal generation circuit. Will get. Here, since complementary differential clock signals are input to the gates of the first and second NMOS transistors, the capacitor connected between the gates of the first and second NMOS transistors is a virtual ground. In contrast, the same effect is obtained as when a double capacity is connected to each gate. That is, when compared with a general RC low-pass filter, assuming that the output impedance of the differential clock generation circuit is equal to the resistance value of the RC low-pass filter, an equivalent delay is obtained with a capacitance value half that of the RC low-pass filter. realizable. Further, if the output impedances at the two differential output terminals of the differential clock generation circuit are equal, the pair of differential clock signals are distorted in the same way, so that the difference between the rise and fall delays can be canceled in the latch circuit. In summary, it is possible to provide a level shift circuit with a delay function that delays an analog clock signal while maintaining a duty ratio while suppressing an increase in circuit area and current consumption.

In the level shift circuit with a delay function, the latch circuit includes a first PMOS transistor and a second PMOS transistor, and the drain of the first NMOS transistor and the drain of the first PMOS transistor are connected. And the drain of the second NMOS transistor and the drain of the second PMOS transistor are connected, the gate of the first PMOS transistor is connected to the drain of the second PMOS transistor, and The gates of two PMOS transistors are connected to the drain of the first PMOS transistor, and the analog clock signal is output from at least one drain of the first PMOS transistor and the second PMOS transistor. There may be.

With the above configuration, in addition to the above effects, the configuration of the latch circuit of the level shift circuit with a delay function can be simplified.

The level shift circuit with a delay function includes a first PMOS transistor and a second PMOS transistor, and a source of the first PMOS transistor and the second PMOS transistor that defines the second power supply voltage. And the drains of the first PMOS transistor and the second PMOS transistor are connected to the first and second nodes, which are the latch locations of the latch circuit, and the first node and the second node A power supply circuit configured to supply the power to one of the transistors and to block the supply of the power to the other node, and from the sources of the first NMOS transistor and the second NMOS transistor to the first A third NMOS transistor and a fourth NMOS transistor between two paths to the ground defining the power supply voltage of An interrupting circuit comprising an NMOS transistor configured to connect one of the two paths and disconnect the other by turning on and off the third NMOS transistor and the fourth NMOS transistor; and the first node And a fifth NMOS transistor and a sixth NMOS transistor between the second node and the drains of the first NMOS transistor and the second NMOS transistor, and the first NMOS transistor and the second NMOS transistor. And a protection circuit configured to limit a drain voltage of the NMOS transistor to a withstand voltage or less, and a resistor connected between the first node and the second node.

With the above configuration, in addition to the above-described effect, when the level of a signal using the low voltage source as a power source is shifted to the voltage level of the high voltage source, the high voltage source The level shift operation can be performed reliably without the transistor being destroyed due to the voltage of.

In the level shift circuit with a delay function, the differential clock signal generation circuit includes first and second inverter circuits, and a single-phase clock signal from the outside is input to an input terminal of the first inverter circuit. The output terminal of the first inverter circuit and the input terminal of the second inverter circuit are connected, and the differential clock signal is output from the output terminals of the first and second inverter circuits. It may be configured.

With the above configuration, in addition to the above effects, the configuration of the differential clock signal generation circuit of the level shift circuit with a delay function can be simplified.

In the level shift circuit with a delay function, the differential clock signal generation circuit includes first and second flip-flops, and an external single-phase clock signal is input to a clock input terminal of the first flip-flop. A signal obtained by inverting the single-phase clock signal is input to the clock input terminal of the second flip-flop, and the positive logic output terminal of the first flip-flop and the input terminal of the second flip-flop are connected. The negative logic output terminal of the second flip-flop and the input terminal of the first flip-flop are connected, and from the positive logic output terminal and the negative logic output terminal of the first flip-flop or the second flip-flop. The differential clock signal may be output.

In the level shift circuit with a delay function, the differential clock signal generation circuit may be configured as a phase synchronization circuit.

In the level shift circuit with a delay function, the differential clock signal generation circuit may be configured to change an output impedance depending on an amount of current supplied from a current source.

With the above configuration, in addition to the above effects, the delay time of the analog clock signal can be adjusted.

In the level shift circuit with a delay function, the capacitor may be formed on the same chip as other elements constituting the level shift circuit with a delay function.

With the above configuration, in addition to the above effects, an increase in the area of the level shift circuit with a delay function can be further suppressed.

In the level shift circuit with a delay function, the capacitor has two or more MOS capacitors, and the first and second NMOS transistors are arranged between the gates of the first NMOS transistor and the second NMOS transistor. The capacitance values seen from the gates of the transistors may be arranged in parallel so as to be equal.

The above configuration makes it easier to maintain the duty ratio when the analog clock signal is delayed in addition to the above effect.

In the above-described level shift circuit with a delay function, the capacitor may be composed of a varactor whose capacitance value is changed by an external control voltage.

In the level shift circuit with a delay function, the capacitor is one of a plurality of capacitors, and the plurality of capacitors are connected in parallel between the gates of the first NMOS transistor and the second NMOS transistor. The combined capacitance value of the plurality of capacitors may be changed by a switching element that is disposed in each of the plurality of capacitors and is connected to each of the plurality of capacitors.

To achieve the above object, another digital-analog mixed semiconductor integrated circuit according to the present invention uses at least a digital circuit for generating a clock signal having the amplitude of the first power supply voltage and the clock signal. And an analog circuit that is provided between the digital circuit and the analog circuit, the clock signal from the digital circuit is input, and the amplitude of the clock signal is changed from the first power supply voltage to the second power supply voltage. And a level shift circuit with a delay adjustment function for outputting the analog clock signal obtained by delaying through the low-pass filter.

With the above configuration, it is possible to prevent interference of digital noise in an analog circuit in a digital-analog mixed semiconductor integrated circuit.

In the digital-analog mixed semiconductor integrated circuit, the analog circuit is one of a plurality of analog circuits, and the analog clock signals having different delay times by the level shift circuit with a delay function are the plurality of analog circuits. The analog circuits may be supplied respectively.

With the above configuration, it is possible to prevent interference between analog circuits due to digital noise in a digital-analog mixed semiconductor integrated circuit.

In order to achieve the above object, another delay circuit according to the present invention includes a differential clock signal generation circuit that generates a pair of complementary differential clock signals, a first NMOS transistor, and a second NMOS transistor. One differential output terminal of the differential clock signal generation circuit is connected to a gate of the first NMOS transistor, and the other differential output terminal of the differential clock signal generation circuit is the second NMOS transistor. A differential clock signal input circuit configured to be connected to the gates of the first and second NMOS transistors, and latch the potentials on the drain sides of the first NMOS transistor and the second NMOS transistor, respectively. An analog clock signal is output from at least one of the drains of the second NMOS transistor. A latch circuit, and a capacitor having both terminals connected between the gates of the first NMOS transistor and the second NMOS transistor and forming a low-pass filter together with an output impedance of the differential clock signal generation circuit, The analog clock signal is obtained by delaying the differential clock signal through the low-pass filter.

According to the present invention, there are provided a level shift circuit with a delay function, a digital-analog mixed type semiconductor integrated circuit, and a delay circuit that delay an analog clock signal while maintaining a duty ratio while suppressing an increase in circuit area and current consumption. can do.

FIG. 1 is a circuit diagram showing a configuration of a level shift circuit with a delay function according to the first embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration example of the differential clock signal generation circuit of FIG. FIG. 3 is an input / output waveform diagram of the differential clock signal generation circuit of FIG. FIG. 4 is a circuit diagram showing another configuration example of the differential clock signal generation circuit of FIG. FIG. 5 is an input / output waveform diagram of the differential clock signal generation circuit of FIG. FIG. 6 is a circuit diagram showing a modification of the level shift circuit with a delay function according to the first embodiment of the present invention. FIG. 7 is a waveform diagram for explaining the principle of delay generation in the level shift circuit with a delay function of FIG. FIG. 8 is a waveform diagram and a transistor state transition diagram for explaining the principle of delay generation in the level shift circuit with a delay function of FIG. FIG. 9 is a circuit diagram showing a configuration of a level shift circuit with a delay function according to the third embodiment of the present invention. FIG. 10 is a circuit diagram showing a configuration of a level shift circuit with a delay function according to the fourth embodiment of the present invention. FIG. 11 is a circuit diagram showing a configuration of a level shift circuit with a delay function according to the fifth embodiment of the present invention. FIG. 12 is a circuit diagram showing a configuration of a level shift circuit with a delay function according to the sixth embodiment of the present invention. FIG. 13 is a circuit diagram showing a configuration of a level shift circuit according to the fifth embodiment of the present invention. FIG. 14 is a block diagram and waveform diagram for explaining the overall configuration of a digital-analog mixed semiconductor integrated circuit according to the sixth embodiment of the present invention. FIG. 15 is a block diagram showing a configuration example of a digital-analog mixed semiconductor integrated circuit according to the sixth embodiment of the present invention. FIG. 16 is a waveform diagram of clock signals for driving the digital circuit, AD converter, and DA converter shown in FIG. FIG. 17 is a circuit diagram showing a configuration of a conventional level shift circuit. FIG. 18 is a circuit diagram showing the configuration of another conventional level shift circuit. FIG. 19 is a block diagram and a waveform diagram for explaining the overall configuration of a conventional digital-analog mixed semiconductor integrated circuit. FIG. 20 is a circuit diagram showing a configuration example of a conventional delay circuit. FIG. 21 is a circuit diagram showing a configuration example of a conventional delay circuit.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In the following description, the same or corresponding elements are denoted by the same reference symbols throughout the drawings, and redundant description thereof is omitted.
(First embodiment)
[Overall configuration of level shift circuit with delay function]
FIG. 1 is a circuit diagram showing a configuration of a level shift circuit with a delay function according to the first embodiment of the present invention.

The level shift circuit 100 with a delay function in FIG. 1 includes an input side power supply terminal VDDI, an input side ground terminal VSSI, an input terminal IN, an output side power supply terminal VDDO, an output side ground terminal VSSO, and an output terminal OUT. Have. The level shift circuit 100 with a delay function in FIG. 1 adds a capacitor C1 to the configuration of the level shift circuit 700 with a delay function in FIG. 17, and inputs an analog clock signal output from the output terminal OUT to the input terminal IN. The single phase clock signal is delayed in accordance with the capacitance value of the capacitor C1. As a result, it is possible to delay the analog clock signal while maintaining the duty ratio while minimizing the spread of digital noise to the analog circuit and suppressing an increase in circuit area and current consumption.

Specifically, the level shift circuit 100 with a delay function includes a differential clock signal generation circuit 1, a differential clock signal input circuit 3, a latch circuit 4, an inverter circuit 2, and a capacitor C1. .

The differential clock signal generation circuit 1 is driven by the input-side power supply voltage [VDDI−VSSI] and has an amplitude of the input-side power supply voltage [VDDI−VSSI] based on the single-phase clock signal input to the input terminal IN. And a pair of complementary differential clock signals INO and INOB are generated.

The differential clock signal input circuit 3 includes an NMOS transistor N1 and an NMOS transistor N2, and one of the two differential output terminals of the differential clock signal generation circuit 1 is connected to the gate of the NMOS transistor N1. The other differential output terminal is configured to be connected to the gate of the NMOS transistor N2. In the present embodiment, the differential clock signal input circuit 3 has one differential clock signal INO input to the gate, the NMOS transistor N1 whose source is connected to the input side ground terminal VSSI, and the other differential clock signal to the gate. An NMOS transistor N2 to which the clock signal INOB is input and whose source is connected to the input side ground terminal VSSI.

The latch circuit 4 latches the drain-side potentials (nodes W1 and W2) of the NMOS transistors N1 and N2, and the amplitude of the output-side power supply voltage [VDDO−VSSI] from at least one of the drains of the NMOS transistors N1 and N2. Is configured to output an analog clock signal. In this embodiment, the latch circuit 4 includes a PMOS transistor P1 having a source connected to the output side power supply terminal VDDO, a drain connected to the drain of the NMOS transistor N1, and a gate connected to the drain of the NMOS transistor N2. Is connected to the output side power supply terminal VDDO, the drain is connected to the drain of the NMOS transistor N2, and the gate is connected to the drain of the NMOS transistor N1, and the drain of the PMOS transistor P2 and the NMOS transistor N2 An analog clock signal is output from a node W2 that connects the drains to each other.

That is, the gates and drains of the PMOS transistors P1 and P2 are so-called cross-coupled, and latch the potential state on the drain side of the NMOS transistors N1 and N2. When the NMOS transistor N1 is turned on, the drain voltage of the NMOS transistor N1 becomes a low level (input-side ground potential VSSI), and the PMOS transistor P2 is turned on and the PMOS transistor P1 is turned off until the NMOS transistor N2 is turned on next time. Hold. On the other hand, when the NMOS transistor N2 is turned on, the drain voltage of the NMOS transistor N2 becomes low level (input-side ground potential VSSI), and the PMOS transistor P1 is turned on and the PMOS transistor P2 is turned off until the NMOS transistor N1 is turned on next time. Hold the state to do. The above operation is defined as a latch.

The inverter circuit 2 shapes the analog clock signal output from the latch circuit 4 and outputs it. In the present embodiment, the inverter circuit 2 is driven by the output side power supply voltage [VDDO-VSSO], the input terminal is connected to the drain of the NMOS transistor N2, and the output terminal is connected to the output terminal OUT. ing.

The capacitor C1 has both terminals connected between the gates of the NMOS transistors N1 and N2, and is configured to form an RC low-pass filter together with the output impedance of the differential clock signal generation circuit 1. The capacitor C1 is formed on the same chip as the other elements constituting the level shift circuit 100 with a delay function.

FIG. 2 is a circuit diagram showing a configuration example of the differential clock signal generation circuit of FIG. 1, and FIG. 3 is an input / output waveform diagram of the differential clock signal generation circuit of FIG.

As shown in FIG. 2, the differential clock signal generation circuit 1 includes

inverter circuits

11 and 12 of the same size, and a single-phase clock signal from the outside is input to the input terminal of the inverter circuit 11. The output terminal and the input terminal of the inverter circuit 12 are connected, and the differential clock signals INO and INOB are output from the output terminals of the

inverter circuits

11 and 12. Further, the differential clock signal generation circuit 1 is configured such that the output impedances of the output terminals of the

inverter circuits

11 and 12 are substantially equal. According to this configuration, as shown in FIG. 3, it can be seen that differential clock signals INO and INOB having the same frequency as the clock signal input to the inverter circuit 11 in the previous stage are generated.

FIG. 4 is a circuit diagram showing another configuration example of the differential clock signal generation circuit 1 of FIG. 1, and FIG. 5 is an input / output waveform diagram of the differential clock signal generation circuit of FIG. As shown in FIG. 5, the differential clock signal generation circuit 1 includes edge-triggered flip-

flops

13 and 14 having the same size, and an external single-phase clock signal is applied to the clock input terminal of the edge-triggered flip-flop 13. A signal obtained by logically inverting the single-phase clock signal by the inverter circuit 15 is input to the clock input terminal (C) of the edge trigger flip-flop 14, and the positive logic output terminal (Q 1) of the edge trigger flip-flop 13 is input. The input end (D2) of the edge trigger flip-flop 14 is connected, the negative logic output end (Q2B) of the edge trigger flip-flop 14 and the input end (D1) of the edge trigger flip-flop 13 are connected, and the edge trigger type Positive logic output terminal (Q of the flip-flop 13 or the edge trigger type flip-flop 14) ) And negative logic output (Q2B) from the differential clock signals INO, is configured to INOB is output. Further, the edge trigger type flip-

flops

13 and 14 are configured so that the output impedances of the positive logic output and the negative logic output are substantially equal. According to this configuration, as shown in FIG. 5, it can be seen that differential clock signals INO and INOB are generated by dividing the clock signal input to the preceding edge trigger type flip-flop 13 by two.

In addition to the above configuration example, the differential clock signal generation circuit 1 is configured to output differential clock signals INO and INOB from two output terminals having substantially equal output impedances, as shown in FIG. The phase synchronization circuit (PLL circuit) may be implemented. Alternatively, the differential clock signal generation circuit 1 may be realized by an arbitrary circuit that has a positive logic output end and a negative logic output end and is configured so that the output impedances of both are substantially equal.

[Operation of level shift circuit with delay function]
The outline of the operation of the level shift circuit 100 with a delay function in FIG.
The differential clock signals INO and INOB have the amplitude of the input-side power supply voltage [VDDI−VSSI] and have a relationship in which the phases are inverted. Accordingly, the NMOS transistors N1 and N2 are turned on and off in a complementary manner.

For example, when the potentials of the differential clock signals INO and INOB are Low level (input-side ground potential VSSI) and High level (input-side power supply potential VDDI), the NMOS transistor N1 is turned on and the NMOS transistor N2 is turned off. At this time, the gate voltage of the PMOS transistor P2 becomes higher than the input-side ground potential VSSI by the on-voltage (drain-source voltage) of the NMOS transistor N1, and the PMOS transistor P2 is turned on. Then, the gate voltage of the PMOS transistor P1 becomes lower than the high-voltage power supply potential VDDO by the on-voltage (drain-source voltage) of the PMOS transistor P2, and the PMOS transistor P1 is turned off. The drain voltage of the NMOS transistor N2 is also applied to the input terminal of the inverter circuit 2, and the output of the inverter circuit 2 becomes a low level voltage near the output-side ground potential VSSO.

Here, if only the potential of the differential clock signal INOB changes to the Low level, the NMOS transistors N1 and N2 are both turned off, so that the on / off states of the PMOS transistors P1 and P2 are maintained. That is, the PMOS transistors P1 and P2 whose gates and drains are cross-coupled operate as the latch circuit 4.

On the other hand, when the potentials of the differential clock signals INO and INOB are High level (input-side power supply potential VDDI) and Low level (input-side ground potential VSSI), the NMOS transistor N2 is turned on and the NMOS transistor N1 is turned off. In this case, the operation is the same as described above, and the PMOS transistor P1 is turned on and the PMOS transistor P2 is turned off. Further, the output of the inverter circuit 2 becomes a high level voltage in the vicinity of the output side power supply potential VDDO.

[Principle of delay generation]
FIG. 7 is a waveform diagram for explaining the principle of delay generation in the level shift circuit 100 with a delay function in FIG.

7A and 7D are ideal waveform diagrams of the differential clock signals INO and INOB output from the differential clock signal generation circuit 1. FIG.

However, the waveforms of the differential clock signals INO and INOB are not actually rectangular waves as shown in FIGS. 7A and 7D, but the output impedance of the differential clock signal generation circuit 1 and the capacitor C1. Are blunted so that the rise and fall are gentle as shown in FIGS. 7B and 7E. Note that the time constant of the rising edge of the waveform is usually longer than the time constant of the falling edge of the waveform.

Furthermore, the waveforms of the differential clock signals INO and INOB are delayed by the threshold voltages Vth (gate voltages at which N1 and N2 are turned on) of the NMOS transistors N1 and N2, and are shaped as rectangular wave drain voltages. The threshold voltage Vth is generally a value lower than half of the input-side power supply potential VDDL, and a deviation occurs between the rising delay time TR and the falling delay time TF. For this reason, the NMOS transistors N1 and N2 are ideally turned on and off in a complementary manner. For example, there is a difference between the time when the NMOS transistor N1 is switched from off to on and the time when the NMOS transistor N2 is switched from on to off. Arise.

However, when one of the NMOS transistors N1 and N2 is subjected to waveform shaping at the time of rising, the other is subjected to waveform shaping at the time of falling, and these waveform-shaped voltages (drain voltages of N1 and N2) ) Is applied to the gates of the PMOS transistors P1 and P2 operating as the latch circuit 4. Thereby, the difference between the delay at the rise and the delay at the fall is canceled, and the ideal output duty ratio of the differential clock signal generation circuit 1 is reproduced. Then, the waveform is again shaped by the inverter circuit 2 at the final stage, and an analog clock signal as shown in FIGS. 7C and 7D is output from the output terminal OUT.

FIG. 8 shows the state transition of the NMOS transistors N1, N2 and the PMOS transistors P1, P2 at this time. As shown in FIG. 8, the drain voltage of the NMOS transistors N1 and N2 does not have a complementary relationship due to the difference between the rising delay time TR and the falling delay time TF, and the NMOS transistors N1 and N2 The on / off timing is not synchronized. However, when the drain voltages of the NMOS transistors N1 and N2 are applied to the gates of the PMOS transistors P1 and P2 operating as the latch circuit 4, it can be seen that the on / off timings of the PMOS transistors P1 and P2 are synchronized.

As described above, according to the level shift circuit 100 with a delay function according to the present embodiment, the low-pass filter is formed by the output impedance of the differential clock signal generation circuit 1 and the capacitor C1, and the waveforms of the differential clock signals INO and INOB are obtained. I am trying to get a delay by slowing down. Here, complementary differential clock signals INO and INOB are input to the gates of the NMOS transistors N1 and N2, respectively. For this reason, the capacitor C1 connected between the gates of the NMOS transistors N1 and N2 brings about the same effect as when the double capacitance is connected to each gate with respect to the virtual ground.

Then, the low-pass filter in the present embodiment is assumed that the resistance value of the resistor R in FIG. 21 is equal to the output impedance of the differential clock signal generation circuit 1 as compared with the low-pass filter included in the delay circuit in FIG. In this case, the same delay can be realized by the capacitance value of one half of the capacitor C in FIG. Further, if the output impedances of the two differential output terminals of the differential clock signal generation circuit 1 are equalized, the differential clock signals INO and INOB are distorted in the same manner, so that the PMOS transistors P1 and P1 that operate as a latch circuit In P2, the difference between the delay at the rise and the delay at the fall can be canceled out.

(Third embodiment)
FIG. 9 is a circuit diagram showing a configuration of a level shift circuit with a delay function according to the third embodiment of the present invention.

9 differs from the level shift circuit 100 with a delay function in FIG. 1 in that the MOS capacitors C2 and C3 are replaced with the NMOS transistors N1 and N2 in place of the capacitor C1 that generates a delay. This is the point that the capacitance values seen from the gate are equal. The MOS capacitor generally has polarity and parasitic capacitance, and the capacitance value seen from both terminals changes. Therefore, in the present embodiment, the MOS capacitors C2 and C3 are connected in the reverse direction and in parallel so that the capacitance values seen from the gates of the NMOS transistors N1 and N2 are equal. This makes it easier to maintain the duty ratio when delaying the analog clock signal.

(Fourth embodiment)
FIG. 10 is a circuit diagram showing a configuration of a level shift circuit with a delay function according to the fourth embodiment of the present invention.

The level shift circuit 100 with a delay function in FIG. 10 is different from the level shift circuit 100 with a delay function in FIG. 1 in that a capacitor C1 that generates a delay has a varactor VC1, a capacitance value of which varies according to an external control voltage VCTRL. This is a point constituted by VC2. Even in this embodiment, the analog clock signal can be delayed while maintaining the duty ratio while suppressing an increase in circuit area and current consumption. Furthermore, the delay time of the analog clock signal can be adjusted by changing the capacitance values of the varactors VC1 and VC2 by the external control voltage VCTRL.

(Fifth embodiment)
FIG. 11 is a circuit diagram showing a configuration of a level shift circuit with a delay function according to the fifth embodiment of the present invention.

The level shift circuit 100 with a delay function in FIG. 11 is different from the level shift circuit 100 with a delay function in FIG. 1 in that a plurality of capacitors C1 to CN are arranged in parallel between the gates of the NMOS transistors N1 and N2. The switching elements SW1 to SWN are connected in series to the capacitors C1 to CN. Note that on / off of the switching elements SW1 to SWN is controlled by an external digital control signal DCTRL. Even in this embodiment, the analog clock signal can be delayed while maintaining the duty ratio while suppressing an increase in circuit area and current consumption. Further, by controlling on / off of each of the switching elements SW1 to SWN, the capacitance value connected between the gates of the NMOS transistors N1 and N2, that is, the combined capacitance value of the plurality of capacitors C1 to CN is changed, thereby changing the analog value. The delay time of the clock signal can also be adjusted.
(Sixth embodiment)
FIG. 12 is a circuit diagram showing a configuration of a level shift circuit with a delay function according to the sixth embodiment of the present invention.

The level shift circuit 100 with a delay function in FIG. 12 is different from the level shift circuit 100 with a delay function in FIG. 1 in that a current source I1 is provided on the input side power supply potential VDDI side of the differential clock signal generation circuit 1, and The current source I2 is provided on the input side ground potential VSSI side. Even in this embodiment, the analog clock signal can be delayed while maintaining the duty ratio while suppressing an increase in circuit area and current consumption. Further, by adjusting the current amounts of the current sources I1 and I2, the output impedance can be changed for each of the two differential outputs of the differential clock signal generation circuit 1, and the delay time of the analog clock signal can be adjusted. .
(Seventh embodiment)
[Configuration of level shift circuit with delay function]
FIG. 13 is a circuit diagram showing a configuration of a level shift circuit with a delay function according to the seventh embodiment of the present invention.

The level shift circuit 200 with a delay function in FIG. 13 includes an input side power supply terminal VDDL, an input side ground terminal VSSL, an input terminal IN, an output side power supply terminal VDDH, an output side ground terminal VSSH, and an output terminal OUT. Have. Note that the power supply potential VDDH of the output side power supply terminal VDDH is higher than the power supply potential VDDL of the input side power supply terminal VDDL.

Further, the level shift circuit 200 with a delay function includes a differential clock signal generation circuit 1, a differential clock signal input circuit 3, a power supply circuit 20, an intermittent circuit 5, a protection circuit 6, a resistor R1, and a NAND. An RS latch circuit composed of circuits 7 and 8 and a power supply and intermittent control circuit composed of

inverter circuits

9 and 10 are provided.

The differential clock signal generation circuit 1 is driven by the input side power supply voltage [VDDL−VSSL], and has an amplitude of the input side power supply voltage [VDDL−VSSL] based on the single-phase clock signal input to the input terminal IN. And a pair of complementary differential clock signals XINO and XINOB are generated.

The differential clock signal input circuit 3 includes an NMOS transistor N1 and an NMOS transistor N2, and one of the two differential output terminals of the differential clock signal generation circuit 1 is connected to the gate of the NMOS transistor N1. The other differential output terminal is configured to be connected to the gate of the NMOS transistor N2. In this embodiment, the differential clock signal input circuit 3 has one differential clock signal INO input to the gate and the source connected to the output side ground terminal VSSL via the NMOS transistor N3 described later. And an NMOS transistor N2 whose gate is supplied with the other differential clock signal INOB and whose source is connected to an output-side ground terminal VSSL via an NMOS transistor N4 described later.

The power supply circuit 20 includes a PMOS transistor P3 and a PMOS transistor P4, and the sources of the PMOS transistor P3 and the PMOS transistor O4 are connected to the output-side power supply terminal VDDH on the high potential side of the first output-side power supply voltage [VDDH−VSSL]. The drains of the PMOS transistor P3 and the PMOS transistor P4 are connected to nodes W1 and W2 which are latched portions of the latch circuit composed of the NAND circuits 7 and 8, and one of the nodes W1 and W2 is connected to the output side power supply. While supplying the voltage from the terminal VDDH, the supply of the voltage from the output side power supply terminal VDDH to the other node is cut off.

The intermittent circuit 5 includes NMOS transistors N3 and N4 between two paths from the sources of the NMOS transistors N1 and N2 to the output-side ground terminal VSSL on the low potential side of the first output-side power supply voltage [VDDH−VSSL]. One of the two paths is connected and the other is disconnected by turning on and off the NMOS transistors N3 and N4.

The protection circuit 6 includes NMOS transistors N5 and N6 between the nodes W1 and W2 and the drains of the NMOS transistors N1 and N2, and is configured to limit the drain voltage of the NMOS transistors N1 and N2 to a withstand voltage or less.

The resistor R1 is connected between the nodes W1 and W2.

The NAND circuits 7 and 8 are driven by the second output side power supply voltage [VDDH−VSSH], input terminals are connected to the nodes W1 and W2, and are connected to the output terminal OUT, thereby forming an RS latch circuit. Yes.

The

inverter circuits

9 and 10 are driven by the output side power supply voltage [VDDH−VSSH], and their input terminals are connected to the output terminal OUT. The power supply circuit 20 and the intermittent circuit 5 are controlled based on the outputs of the

inverter circuits

9 and 10.

[Operation of level shift circuit with delay function]
Hereinafter, an outline of the operation of the level shift circuit 200 with a delay function in FIG.

For example, when the potential of the differential clock signal INO changes from the low level (input side ground potential VSSL) to the high level (input side power supply potential VDDL), the NMOS transistor N1 is turned on, and the high level potential of the node W1 in the figure. (Output-side power supply potential VDDH) decreases. At this time, a high level voltage (output-side power supply potential VDDH) of the differential clock signal INO is applied to the gate of the NMOS transistor N5. The NMOS transistor N5 limits the drain potential of the NMOS transistor N1 to the output side power supply potential VDDH or less (below the withstand voltage of the NMOS transistor N1), so that the NMOS transistor N1 is not destroyed. Further, the NMOS transistor N2 is turned off, but a low level (input-side ground potential VSSL) voltage is applied to the gate of the NMOS transistor N6. Therefore, even if the potential of the node W2 is at a high level (output-side power supply potential VDDH), the drain potential of the NMOS transistor N2 is limited to be equal to or lower than the output-side power supply potential VDDH. *

Also when the differential clock signal INO changes from the high level (input-side power supply potential VDDH) to the low level (input-side ground potential VSSL), the same operation as described above is performed.

[Principle of delay generation]
The level shift circuit 200 with a delay function in FIG. 13 is provided with a capacitor C1 between the gates of the NMOS transistors N1 and N2 based on the same principle as the above embodiment, while suppressing an increase in circuit area and current consumption. The analog clock signal can be delayed while maintaining the duty ratio. Note that in a level shift circuit with a delay function that receives a complementary analog clock signal and is processed by a latch circuit, a delay can be similarly generated by inserting a capacitor between the analog clock signal inputs. it can. Furthermore, the level shift circuit 200 with a delay function can be used as a simple delay circuit by making the input-side power supply and the output-side power supply the same.

(Eighth embodiment)
[Overall configuration of digital-analog mixed semiconductor integrated circuit]
FIG. 14 is a block diagram and a waveform diagram for explaining the overall configuration of the digital-analog mixed semiconductor integrated circuit according to the eighth embodiment of the present invention.

14 includes a digital circuit 201, an analog clock signal generation circuit 202,

level shift circuits

100 and 200 with a delay function, and an analog circuit 205.

As shown in the waveform diagram of FIG. 14, the digital clock signal output from the digital circuit 201 is converted into an analog clock signal having a different frequency in the analog clock signal generation circuit 202. Next, the analog clock signal is level-shifted from the digital circuit power supply voltage DVDD to the analog circuit power supply voltage AVDD by the

level shift circuits

100 and 200 with a delay function, and delayed according to the capacitor C1, and then the analog circuit. Propagated to 205.

[Configuration example of digital-analog mixed semiconductor integrated circuit]
FIG. 15 is a block diagram showing a configuration example of a digital / analog mixed semiconductor integrated circuit according to the eighth embodiment of the present invention.

The digital-analog mixed type semiconductor integrated circuit 600 of FIG. 15 includes a digital power pad DVDD, a digital ground pad DVSS, an analog power pad AVDD, an analog ground pad AVSS, and an AD converter input signal pad ADIN. And a DA converter output signal pad DAOUT. The digital-analog mixed semiconductor integrated circuit 600 includes a digital circuit 601, an AD converter 602, a DA converter 603, AD converter

level shift circuits

604 and 605, and DA converter

level shift circuits

606 and 607. And.

The digital circuit 601 is driven by a digital power supply voltage [DVDD-DVSS], receives AD conversion data ADDATAD, and outputs an AD converter clock signal ADCLKD, a DA converter clock signal DACLKD, and a DA converter data signal DADATAD. Is done.

The DA converter 603 converts the amplitude of the AD converter clock signal ADCLKD generated by the digital circuit 601 from the digital power supply voltage [DVDD-DVSS] to the analog power supply voltage [AVDD-AVSS], and the analog power supply voltage [AVDD] -AVSS] AD converter clock signal ADCLK.

The AD converter level shift circuit 605 converts the amplitude of the AD conversion data ADDATA generated by the AD converter 602 from the analog power supply voltage [AVDD-AVSS] to the digital power supply voltage [DVDD-DVSS]. DVDD-DVSS] AD conversion data ADDATAD is obtained.

The DA converter

level shift circuits

606 and 607 convert the amplitude of the DA converter clock signal DACLKD and DA converter data DADATAD generated by the digital circuit 601 from the digital power supply voltage [DVDD-DVSS] to the analog power supply voltage [AVDD-AVSS]. To obtain the DA converter clock signal DACLK and DA converter data DATA of the analog power supply voltage [AVDD−AVSS].

The AD converter 602 outputs AD conversion data ADDATA obtained by AD converting the AD converter input signal ADIN based on the AD converter clock signal ADCLK.

The DA converter 603 outputs a DA conversion output signal DAOUT obtained by DA converting the DA converter input data DATA based on the DA converter clock signal DACLK.

Here, the AD converter level shift circuit 604 is configured by the delay function

level shift circuits

100 and 200 according to the above-described embodiment, and performs a level shift with a delay time Td1. The DA converter level shift circuit 606 includes the delay function-equipped

level shift circuits

100 and 200 according to the above-described embodiment, and performs a level shift with a delay time Td2.

As shown in FIG. 16, the delay time Td1 is a delay time having such a length that the edge does not overlap with the clock signal DIGICLK used in the digital circuit 601. The delay time Td2 is a delay time having a length that does not overlap edges of the clock signal DIGICLK used in the digital circuit 601 and the clock signal ADCLK used in the AD converter 602. . The relationship between the delay time Td1 and the delay time Td2 may be “Td1 <Td2” or “Td1> Td2”.

Further, as shown in FIG. 15, the analog power supply line and the analog ground line are supplied from separate pads, and are connected to the AD converter 602 and the DA converter 603, respectively. Is designed to branch near the pad to reduce the common impedance. Furthermore, the interference from the digital circuit 601 to the AD converter 602 and the DA converter 603 and the mutual interference between the AD converter 602 and the DA converter 603 are designed to be small.

Further, the AD converter level shift circuit 604 and the DA converter level shift circuit 606 add a delay, and the delay time Td1 of the AD converter clock signal ADCLK and the delay time Td2 of the DA converter clock signal DACLK have different lengths. By setting to, interference between the digital circuit 601, the AD converter 602, and the DA converter 603 due to an unexpected path can be prevented.

Further, if the delay time can be adjusted by changing the capacitance value of the capacitor C1 or the like as the level shift circuit with a delay function of the present embodiment, it is necessary to rise and fall the clock signal by changing the power supply voltage or the like. Even if edges overlap due to changing the time, it is possible to adjust the delay time so that the edges do not overlap again by changing the capacitance value from the outside, and interference between analog circuits can be prevented.

In this embodiment, the digital-analog mixed semiconductor integrated circuit 600 on which the AD converter 602 and the DA converter 603 are mounted is illustrated, but the present invention is applied to other digital-analog mixed semiconductor integrated circuits. can do.

From the above description, many modifications and other embodiments of the present invention are apparent to persons skilled in the art. Accordingly, the foregoing description should be construed as illustrative only and is provided for the purpose of teaching those skilled in the art the best mode of carrying out the invention. The details of the structure and / or function may be varied substantially without departing from the spirit of the invention.

The present invention relates to a level shift circuit with a delay function between two different power supplies and a digital-analog mixed type semiconductor integrated circuit using the same, and in particular, analog-to-digital conversion that requires improvement in noise characteristics and distortion characteristics. This is useful for a digital-analog mixed type semiconductor integrated circuit equipped with an analog circuit and a digital-analog converter.

DESCRIPTION OF

SYMBOLS

100, 200 ... Level shift circuit 1 ... Differential clock signal generation circuit 11 ... Inverter circuit (1st inverter circuit)
12 ... Inverter circuit (second inverter circuit)
13. Edge trigger type flip-flop (first flip-flop)
14 Edge-triggered flip-flop (second flip-flop)
15 ... Inverter circuits I1, I2 ... Current source 3 ... Differential clock signal input circuit N1 ... NMOS transistor (first NMOS transistor)
N2 ... NMOS transistor (second NMOS transistor)
4 ... Latch circuit P1 ... PMOS transistor (first PMOS transistor)
P2 ... PMOS transistor (second PMOS transistor)
W1 ... Node (first node)
W2 ... Node (second node)
2 ... Inverter circuit C1 ... Capacitors C2, C3 ... MOS capacitors SW1 to SWN ... Switching elements VC1, VC2 ... Varactor 20 ... Power supply circuit P3 ... PMOS transistor (first PMOS transistor)
P4: PMOS transistor (second PMOS transistor)
5 ... Intermittent circuit N3 ... NMOS transistor (third NMOS transistor)
N4 ... NMOS transistor (fourth NMOS transistor)
7, 8 ... NAND circuit (latch circuit)
9, 10... Inverter circuit R1... Resistor 6... Protection circuit N5... NMOS transistor (fifth NMOS transistor)
N6: NMOS transistor (sixth NMOS transistor)
600 ... Digital-analog mixed type semiconductor integrated circuit 601 ... Digital circuit 602 ... AD converter 603 ... DA converter 604,605 ... AD converter level shift circuit 606,607 ... DA converter level shift circuit

Claims

A differential clock signal generation circuit having a first power supply voltage amplitude and generating a pair of complementary differential clock signals;
A first NMOS transistor and a second NMOS transistor, wherein one differential output terminal of the differential clock signal generation circuit is connected to a gate of the first NMOS transistor, and the other of the differential clock signal generation circuit A differential clock signal input circuit configured to be connected to the gate of the second NMOS transistor;
The potential on the drain side of the first NMOS transistor and the second NMOS transistor is latched, respectively, and the first power supply voltage from at least one of the drains of the first NMOS transistor and the second NMOS transistor A latch circuit configured to output an analog clock signal having a different amplitude of the second power supply voltage;
A capacitor having both terminals connected between the gates of the first NMOS transistor and the second NMOS transistor and forming a low-pass filter together with an output impedance of the differential clock signal generation circuit;
The analog clock signal is a level shift circuit with a delay function obtained by delaying the differential clock signal through the low-pass filter.
The latch circuit is
A first PMOS transistor and a second PMOS transistor;
The drain of the first NMOS transistor and the drain of the first PMOS transistor are connected, and the drain of the second NMOS transistor and the drain of the second PMOS transistor are connected,
The gate of the first PMOS transistor is connected to the drain of the second PMOS transistor, and the gate of the second PMOS transistor is connected to the drain of the first PMOS transistor;
2. The level shift circuit with a delay function according to claim 1, configured to output the analog clock signal from at least one drain of the first PMOS transistor and the second PMOS transistor. 3.
A first PMOS transistor and a second PMOS transistor, and the sources of the first PMOS transistor and the second PMOS transistor are connected to a power supply defining the second power supply voltage, and the first PMOS transistor And the drain of the second PMOS transistor is connected to the first and second nodes, which are the latch locations of the latch circuit, and supplies the power to one of the first node and the second node; A power supply circuit configured to cut off the supply of the power to the other node;
A third NMOS transistor and a fourth NMOS transistor are provided between two paths from the sources of the first NMOS transistor and the second NMOS transistor to the ground defining the second power supply voltage, An interrupt circuit configured to connect one of the two paths and disconnect the other by turning on and off the NMOS transistor and the fourth NMOS transistor;
A fifth NMOS transistor and a sixth NMOS transistor are provided between the first node and the second node and the drains of the first NMOS transistor and the second NMOS transistor, and the first NMOS transistor A protection circuit configured to limit a drain voltage of the transistor and the second NMOS transistor to a withstand voltage or less;
A resistor connected between the first node and the second node;
A level shift circuit with a delay function according to claim 1.
The differential clock signal generation circuit includes:
A first and second inverter circuits are provided, and an external single-phase clock signal is input to the input terminal of the first inverter circuit, and the output terminal of the first inverter circuit and the input of the second inverter circuit 4. The delay function according to claim 1, wherein the differential clock signal is output from each output terminal of the first and second inverter circuits. Level shift circuit with.
The differential clock signal generation circuit includes:
A first and second flip-flop, an external single-phase clock signal is input to the clock input terminal of the first flip-flop, and a signal obtained by inverting the single-phase clock signal is input to the second flip-flop; Input to a clock input terminal, a positive logic output terminal of the first flip-flop and an input terminal of the second flip-flop are connected, and a negative logic output terminal of the second flip-flop and the first flip-flop And the differential clock signal is output from a positive logic output terminal and a negative logic output terminal of the first flip-flop or the second flip-flop. 4. The level shift circuit with a delay function according to any one of items 1 to 3.
The level shift circuit with a delay function according to any one of claims 1 to 3, wherein the differential clock signal generation circuit is configured as a phase synchronization circuit.
The level shift circuit with a delay function according to claim 1, wherein the differential clock signal generation circuit is configured to change an output impedance according to an amount of current supplied from a current source.
The level shift circuit with a delay function according to claim 1, wherein the capacitor is formed on the same chip as other elements constituting the level shift circuit with a delay function.
The capacitor has two or more MOS capacitors, and a capacitance value seen from each gate of the first and second NMOS transistors is between each gate of the first NMOS transistor and the second NMOS transistor. Arranged in parallel to be equal,
The level shift circuit with a delay function according to claim 1.
2. The level shift circuit with a delay function according to claim 1, wherein the capacitor is constituted by a varactor whose capacitance value is changed by an external control voltage.
The capacitor is one of a plurality of capacitors;
The plurality of capacitors are arranged in parallel between the gates of the first NMOS transistor and the second NMOS transistor, and a combined capacitance value of the plurality of capacitors is obtained by a switching element connected to each of the plurality of capacitors. The level shift circuit with a delay function according to claim 1, wherein the level shift circuit is configured to change.
A digital circuit for generating at least a clock signal having an amplitude of the first power supply voltage;
An analog circuit using the clock signal;
Provided between the digital circuit and the analog circuit, the clock signal from the digital circuit is input, and the level of the amplitude of the clock signal is shifted from the first power supply voltage to the second power supply voltage; And the level shift circuit with a delay function according to claim 1, which outputs the analog clock signal obtained by delaying through the low-pass filter,
A digital-analog mixed semiconductor integrated circuit comprising:
13. The analog circuit is one of a plurality of analog circuits, and the analog clock signals having different delay times are supplied to the plurality of analog circuits by the level shift circuit with a delay function, respectively. The digital-analog mixed semiconductor integrated circuit described.
A differential clock signal generation circuit for generating a pair of complementary differential clock signals;
A first NMOS transistor and a second NMOS transistor, wherein one differential output terminal of the differential clock signal generation circuit is connected to a gate of the first NMOS transistor, and the other of the differential clock signal generation circuit A differential clock signal input circuit configured to be connected to the gate of the second NMOS transistor;
The drain side potentials of the first NMOS transistor and the second NMOS transistor are latched, and an analog clock signal is output from at least one of the drains of the first NMOS transistor and the second NMOS transistor. A configured latch circuit; and
A capacitor having both terminals connected between the gates of the first NMOS transistor and the second NMOS transistor and forming a low-pass filter together with an output impedance of the differential clock signal generation circuit;
And the analog clock signal is obtained by delaying the differential clock signal through the low-pass filter.