CN110047916B - 一种硅基电荷俘获型存储器件及制备方法 - Google Patents
一种硅基电荷俘获型存储器件及制备方法 Download PDFInfo
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Abstract
硅基电荷俘获型存储器件,在结构为p‑Si/隧穿层介质/电荷俘获介质/阻挡层介质/栅电极的存储器件中,存储器件由下至上包括衬底、隧穿层、电荷俘获介质层、阻挡层以及栅电极;隧穿层厚度为1~5nm的绝缘层,电荷俘获介质的导带底与p‑Si的导带底具有匹配的能带结构;电荷俘获介质是两种单元氧化物的混合物,且与硅相比两种介质均具有较高的介电系数,介电系数为6~100。制备出的电荷俘获介质的导带底与p‑Si的导带底具有匹配的能带结构,二者势能差值的范围为‑1.5eV~1.5eV,有利于使电子保持在电荷俘获介质内,提高硅基电荷俘获型存储器件的存储性能。
Description
技术领域
本发明涉及微电子行业的存储技术领域,特别是在电荷俘获型半导体存储器件领域。
背景技术
非易失性存储器件是指当外部电源切断后,存储器件里的信息不会丢失,仍能保持一段时间。它常用于移动硬盘、存储卡和U盘等设备。传统非易失性存储器件使用的是闪存(Flash)技术,在此基础上发展出的新型电荷俘获型存储器,能满足未来器件小型化的需求,有助于实现高集成密度、高性能、低成本的存储技术。
但随着器件尺寸的不断减小,10年内电荷的保持性能是判断器件优良的关键指标,提升保持性能是行业内急需的问题。传统器件使用的存储介质材料(如Si3N4、HfO2)的导带底高于p-Si导带底,电子从p-Si隧穿进入电荷俘获介质,较短时间后又会回到p-Si,致使保持性能不佳。
发明内容
鉴于上述问题,本发明的目的在于,提供一种提高硅基电荷俘获型存储器件存储性能的方法,主要是器件与制备方法。基于能带调控理论制备与p-Si导带底匹配的电荷俘获介质薄膜,该层薄膜的加入能有效提高器件保持性能至10年以上。
本发明的技术方案是,硅基电荷俘获型存储器件,在结构为p-Si/隧穿层介质/电荷俘获介质/阻挡层介质/栅电极的存储器件中,存储器件由下至上包括衬底、隧穿层、电荷俘获介质层、阻挡层以及栅电极;隧穿层厚度为1~5nm的绝缘层,电荷俘获介质的导带底与p-Si的导带底具有匹配的能带结构;电荷俘获介质是两种单元氧化物的混合物,且与硅相比两种介质均具有较高的介电系数,为6~100。在结构为p-Si/隧穿层介质/电荷俘获介质/阻挡层介质/栅电极的存储器件结构中,电荷俘获介质的导带底与p-Si的导带底具有匹配的能带结构。
本发明电荷俘获介质的制备方法包括物理沉积方法,如射频磁控溅射方法及电子束蒸发方法等,也可以使用化学沉积方法,如原子层沉积方法(ALD方法)等,且所制备的薄膜具有非晶结构,薄膜厚度为0.5~20nm。
该电荷俘获介质的导带底的势能与p-Si导带底的势能差值的范围为-1.5eV~1.5eV。
该电荷俘获介质其中所包含的一种单元氧化物介质的导带底的势能比p-Si的导带底的势能高,如Si3N4、Ta2O5、ZrO2、HfO2、Al2O3、Y2O3等,另一种单元氧化物介质的导带底的势能比p-Si的导带底的势能低,如TiO2和ZnO等。
该电荷俘获介质所包含的两种单元氧化物具有不同的晶体结构,且两种氧化物中的阳离子具有不同的化学价态。这是为了在混合均匀后在两种晶体之间产生界面态(或电荷陷阱),界面态的数量由界面态密度表述。高的界面态密度有利于实现高的存储密度,同时这些界面态的能级较深,位于复合氧化物的带隙中,电子被俘获得更深,从而使保持性能更好,电子写入擦除速度更快。
有益效果:本发明基于的能带调控理论是指,使用的两种高介电系数氧化物的导带底势能具有如下特征,其中一个比p-Si的导带底的势能高,另一个比p-Si的导带底的势能低,其目的是为了控制两者比例,合成与p-Si的导带底的势能相近的复合氧化物电荷俘获介质,不产生太大势能差。在外加电场下,电子被写入电荷俘获介质,由于势能差较小,去除外加电场后,电子不会很容易地跃迁回p-Si,使器件具有良好的保持性能。势能差值的范围为-1.5eV~1.5eV,有利于使电子保持在电荷俘获介质内,提高硅基电荷俘获型存储器件的存储性能。
附图说明
图1:基于一种提高硅基电荷俘获型存储器件存储性能方法的电荷俘获型存储器的结构示意图,1为半导体衬底;2隧穿层;3为电荷俘获介质层;4阻挡层;5为栅电极;6为衬底电极;
图2:各材料的能带结构示意图,1为p-Si能带示意图;2为Al2O3的能带示意图,其导带底比p-Si的导带底高2.80eV;3为TiO2的能带示意图,其导带底比p-Si的导带底低1.32eV;4为Al2O3的能带示意图,其导带底比p-Si的导带底低0.084eV;
图3:存储层为(Al2O3)0.3(TiO2)0.7,隧穿层为Al2O3的存储器件的电容电压响应曲线图;
图4:存储层为(Al2O3)0.3(TiO2)0.7,隧穿层为Al2O3的存储器件的保持特性曲线图;
图5:具体实施例2的结构示意图,1为半导体衬底p-Si;2-1为第一种隧穿层;2-2为第二种隧穿层;3为电荷俘获介质层;4阻挡层;5为栅电极;6为衬底电极;
图6:存储层为(Al2O3)0.3(TiO2)0.7,隧穿层为SiO2和Al2O3的存储器件的电容电压响应曲线图;
图7:存储层为(Al2O3)0.3(TiO2)0.7,隧穿层为SiO2和Al2O3的存储器件的保持特性曲线图。
具体实施方式
实施例1:
非易失性电荷俘获存储器件的结构包括衬底,隧穿层,电荷俘获介质层,阻挡层以及栅电极;
隧穿层厚度为1~5nm的绝缘层,制备方法包括物理沉积方法制备,如射频磁控溅射方法及电子束蒸发方法等,也可以使用化学沉积方法制备,如原子层沉积方法(ALD方法);
电荷俘获介质层厚度为0.5~20nm的绝缘层。制备方法包括物理沉积方法,如射频磁控溅射方法及电子束蒸发方法等,也可以使用化学沉积方法制备,如原子层沉积方法(ALD方法);
阻挡层厚度为5~20nm的绝缘层,制备方法包括物理沉积方法,如射频磁控溅射方法及电子束蒸发方法等,也可以使用化学沉积方法制备,如原子层沉积方法(ALD方法);
栅电极层制备方法包括物理沉积方法,如射频磁控溅射方法及电子束蒸发方法等,也可以使用化学沉积方法制备,如原子层沉积方法(ALD方法);
以图1为例,举例具体实施方法。图1中,1为<100>晶向的p-Si衬底,电阻率为1~10Ω/cm;2为Al2O3隧穿层,厚度为3nm;3为(Al2O3)0.3(TiO2)0.7电荷俘获介质层,厚度为3nm;4为Al2O3阻挡层,厚度为15nm;5为Pt栅电极,厚度为100nm;6为衬底电极,用于电学特性测试。
具体制备工艺步骤如下:
p-Si衬底先后用丙酮、乙醇和去离子水超声清洗5分钟,再放入1:10的HF的去离子水溶液中浸泡30s,去除表面二氧化硅,然后用去离子水洗净,并用氮气枪吹干备用;
采用原子层沉积技术(ALD方法),200℃下在上述p-Si衬底上生长3nm的Al2O3隧穿层;
Al2O3中阳离子Al呈正三价,TiO2中阳离子Ti呈正四价,两者阳离子价态不同,另外根据两种氧化物各自的能带结构(如图2),可推算在Al2O3:TiO2为3:7时,合成的复合电荷俘获介质与p-Si导带底相差仅为0.084eV,较为匹配,所以选用(Al2O3)0.3(TiO2)0.7为电荷俘获介质层的材料,其制备方法如下1~3:
1)(Al2O3)0.3(TiO2)0.7陶瓷靶材制备:将Al2O3和TiO2按照3:7的摩尔比均匀混合,再用球磨机充分球磨成粉末,经压片后,放入箱式电阻炉中用1300℃烧结8小时,制成(Al2O3)0.3(TiO2)0.7陶瓷靶材;
2)将(Al2O3)0.3(TiO2)0.7靶材放入磁控溅射仪器的靶台上,p-Si衬底放在样品台上,关腔后,抽真空至7×10-4Pa以下;
3)通入氩气:氧气=3:1的混合气体,控制气压在4Pa,功率使用100W的射频电源,进行溅射,溅射过程中样品台以5~15r/min的速度自转使样品薄膜质量更好;
再次采用原子层沉积技术(ALD方法),200℃下,在生长完电荷俘获介质层的述衬底上生长15nm的Al2O3阻挡层;
将上述结构的器件,放到N2氛围中在200℃下快速退火60s,消除物理应力,使得薄膜之间结合紧密;
在退火后的样品上采用磁控溅射方法生长直径为150μm,厚度为100~200nm的铂金(Pt)电极,磁控溅射的参数为氩气氛围下,2Pa,15W的直流电源生长11分钟;
在上述器件的一角用金刚刀划衬底,直至露出p-Si,在此角涂上银胶,并等待银胶干,作为底电极;
使用Keithley 4200(4200-SCS)半导体分析系统对制备的器件进行电学性能测试,通过测试电容与外加电压的响应关系,来分析器件的保持性能;
器件实行存储的过程如下:在Pt电极和底电极之间施加大于平带电压的正电压时,p-Si表面积累大量电子形成反型层,同时电子也会从p-Si内逃出来穿过隧穿层,进入电荷俘获介质层。由于有较厚阻挡层存在,电子被俘获在电荷俘获介质层内,不会与Pt电极接触。这样就完成了电子的写入过程。在Pt电极和底电极之间施加反向电压时,电荷俘获介质层内的电子会穿过隧穿层,回到p-Si,这样就完成了电子的擦除过程。
图3是实施例1存储器件的电容电压响应曲线,电压测试范围为±6V~±12V,其中±12V时平带电压的变化最大,为8.19V。计算得出电荷存储密度为2.73×1013/cm2,显示出该存储器有良好的存储性能;
图4为对上述存储器件施加±12V的脉冲电压,观察平带电压随时间的变化,从而判断器件的保持性能。具体过程为,施加±12V的脉冲电压后,分别在0s、30s、60s、120s、300s、600s、1200s测试电容电压响应曲线。从图中看出,1200s后电荷损失为25.8%,表明器件保持性能良好。
具体实施例2:
本实施例与实施例1的区别在于,隧穿层厚度为1~5nm的绝缘层,该绝缘层有两层结构,紧邻p-Si衬底有一层0.5~1.5nm的SiO2,是用热氧化方法制备。
在该SiO2层之上是另外一层Al2O3,采用原子层沉积技术(ALD方法),200℃下在上述SiO2层之上生长Al2O3隧穿层;
SiO2层加Al2O3层的总厚度为1~5nm。
在p-Si衬底和Al2O3间增加一层热氧化的SiO2是为了减少p-Si衬底和Al2O3间界面态密度,改善存储器件的保持性能。
以图5为例,举例具体实施方法。图5中,1为<100>晶向的p-Si衬底,电阻率为1~10Ω/cm;2-1为SiO2隧穿层,厚度为1nm;2-2为Al2O3隧穿层,厚度为2nm;3为(Al2O3)0.3(TiO2)0.7电荷俘获介质层,厚度为3nm;4为Al2O3阻挡层,厚度为15nm;5为Pt栅电极,厚度为100nm;6为衬底电极,用于电学特性测试;
图6是实施例2存储器件的电容电压响应曲线,±12V时,平带电压的变化最大,为2.55V。计算得出电荷存储密度为4.92×1012/cm2,显示出该存储器有良好的存储性能;
图7是实施例2存储器件的保持特性曲线,1200s后电荷损失为4.9%,该器件保持性能比实施例2有了显著提升,表明加入SiO2隧穿层后,的确减少了p-Si衬底和Al2O3间界面态密度。
两种氧化物包括Ta为正五价、Ti为正四价的(Ta2O5)5(TiO2)5,或者Hf为正四价,Al为正三价的(HfO2)6(Al2O3)4)。另外需说明的是,以上所述仅为本发明的较佳实施方式,当此基础上进行的任何修饰、扩展和补充等,同样视为本发明保护的内容。
Claims (1)
1.一种硅基电荷俘获型存储器件,其特征在于,硅基电荷俘获型存储器件从下至上由p-Si/隧穿层介质/电荷俘获介质层/阻挡层介质/栅电极构成;电荷俘获介质层的导带底与p-Si的导带底具有匹配的能带结构层;电荷俘获介质层是两种单元氧化物的混合物,且与硅相比两种单元氧化物均具有高的介电系数,两种单元氧化物的介电系数为6~100;
制备的电荷俘获介质层具有非晶结构,厚度为0.5~20nm;该电荷俘获介质层所包含的其中一种单元氧化物的导带底的势能比p-Si的导带底的势能高,另一种单元氧化物的导带底的势能比p-Si的导带底的势能低,电荷俘获介质层为(Al2O3)0.3(TiO2)0.7,隧穿层介质为Al2O3,隧穿层介质厚度为1~5nm;
在p-Si衬底和隧穿层介质Al2O3间增加一层热氧化的SiO2层;以减少p-Si衬底和Al2O3间界面态密度,SiO2层加Al2O3层的总厚度为1~5nm;
该电荷俘获介质层的制备方法包括射频磁控溅射方法、电子束蒸发方法、化学沉积方法或原子层沉积方法;
该电荷俘获介质层的导带底的势能与p-Si导带底的势能差值的范围为-1.5eV~1.5eV。
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