CN110021533A - 制造半导体装置的方法 - Google Patents

制造半导体装置的方法 Download PDF

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Publication number
CN110021533A
CN110021533A CN201811440668.2A CN201811440668A CN110021533A CN 110021533 A CN110021533 A CN 110021533A CN 201811440668 A CN201811440668 A CN 201811440668A CN 110021533 A CN110021533 A CN 110021533A
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China
Prior art keywords
opening
testing cushion
bonding pad
conductive features
layer
Prior art date
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Pending
Application number
CN201811440668.2A
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English (en)
Inventor
胡致嘉
陈宪伟
陈明发
詹森博
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN110021533A publication Critical patent/CN110021533A/zh
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Abstract

一种包括测试垫接触件的半导体装置及一种制造所述半导体装置的方法。在实施例中，半导体装置可包括以单一顶部金属层形式设置在衬底之上的第一金属特征及第二金属特征。可在第一金属特征之上形成测试垫且可将测试垫电连接到第一金属特征。可在第二金属特征及测试垫之上形成第一钝化层且第一钝化层可覆盖测试垫的顶表面及侧表面。可形成穿透第一钝化层并接触测试垫的第一通孔，且可形成穿透第一钝化层并接触第二金属特征的第二通孔。

Description

制造半导体装置的方法
技术领域
本发明的实施例是有关于一种制造半导体装置的方法。
背景技术
半导体装置用于各种电子应用中，例如：个人计算机、手机、数码相机及其他电子设备等。通常通过以下步骤来制作半导体装置：在半导体衬底之上依序沉积绝缘材料层或介电材料层、导电材料层及半导体材料层；以及利用光刻工艺及刻蚀工艺将各种材料层图案化以在所述材料层上形成电路组件及元件。
半导体行业通过不断缩小最小特征大小来不断地提高各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度，以使得更多的组件能够被集成到给定区域中。然而，随着最小特征大小的减小，会在所使用的工艺中的每一工艺内引起附加问题，且应解决这些附加问题。
发明内容
本发明的一实施例公开一种制造半导体装置的方法，其特征在于，包括：在衬底之上形成第一导电特征及第二导电特征；在所述第一导电特征之上形成测试垫且将所述测试垫电性连接到所述第一导电特征；在所述测试垫及所述第二导电特征之上形成结合层；对所述结合层进行刻蚀以形成延伸到所述测试垫的第一开口；对所述结合层进行刻蚀以形成延伸到所述第二导电特征的第二开口；以及分别在所述第一开口及所述第二开口中形成第一结合垫及第二结合垫，其中所述第一结合垫电耦合到所述测试垫，且所述第二结合垫电耦合到所述第二导电特征。
本发明的一实施例公开一种制造半导体装置的方法，其特征在于，包括：在内连结构之上形成第一导电特征及第二导电特征，所述内连结构位于衬底之上；在所述第一导电特征之上形成测试垫且将所述测试垫电连接到所述第一导电特征；对所述测试垫进行探测以确定所述测试垫与所述内连结构之间的电连接；在所述测试垫及所述第二导电特征之上形成介电层；穿过所述介电层形成第一结合垫，其中所述第一结合垫接触所述测试垫；以及穿过所述介电层形成第二结合垫，其中所述第二结合垫接触所述第二导电特征，且其中所述第二结合垫的高度大于所述第一结合垫的高度。
本发明的一实施例公开一种集成电路，其特征在于，包括：第一金属特征及第二金属特征，以单一顶部金属层形式设置在衬底之上；测试垫，位于所述第一金属特征之上且电连接到所述第一金属特征；第一钝化层，位于所述第二金属特征及所述测试垫之上且覆盖所述测试垫的顶表面及侧表面；第一通孔，穿透所述第一钝化层以接触所述测试垫；以及第二通孔，穿透所述第一钝化层以接触所述第二金属特征。
附图说明
结合附图阅读以下详细说明，会最好地理解本公开的各个方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为论述清晰起见，可任意增大或减小各种特征的尺寸。
图1到图10示出根据实施例的在形成半导体管芯中的中间加工步骤的剖视图。
图11到图14示出根据另一实施例的在形成半导体管芯中的中间加工步骤的剖视图。
附图标号说明
100：管芯/半导体管芯
101：衬底
103：有源装置
105：内连结构
107：导电特征
109、1005：介电层
111：顶部金属层
113：钝化层
115：重布线通孔
201：测试垫
301：探测针
401：结合层
501、1101：第一开口
503、1105：第一光刻胶
601、1103：第二开口
603、1205：第二光刻胶
701、1201：第三开口
703、1203：第四开口
705：第三光刻胶
801、1301：晶种层
803、1303：板金属
900、1400：管芯
901、1001、1401：第一结合垫
903、1003、1403：第二结合垫
1000：封装组件
1100：半导体管芯
1107：凹陷的测试垫/测试垫
D1、D2、D3、D4、D5：深度
H1：高度
T1：厚度
W1、W2、W3、W4、W5、W6、W7、W8、W9：宽度
具体实施方式
以下公开内容提供用于实施本发明的不同特征的许多不同的实施例或实例。以下阐述组件及排列形式的具体实例以简化本公开。当然，这些仅为实例且不旨在进行限制。例如，以下说明中将第一特征形成在第二特征“之上”或第二特征“上”可包括其中第一特征及第二特征被形成为直接接触的实施例，且也可包括其中第一特征与第二特征之间可形成有附加特征、进而使得所述第一特征与所述第二特征可不直接接触的实施例。另外，本公开可能在各种实例中重复使用参考编号和/或字母。这种重复使用是出于简洁及清晰的目的，而不是自身表示所论述的各种实施例和/或配置之间的关系。
此外，为易于说明，本文中可能使用例如“位于...之下”、“位于...下方”、“下部的”、“位于...上方”、“上部的”等空间相对性用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括装置在使用或操作中的不同取向。设备可被另外取向(旋转90度或处于其他取向)，且本文中所用的空间相对性描述语可同样相应地进行解释。
图1示出包括衬底101的管芯100的侧视图。衬底101可为硅衬底，但也可使用其他半导体材料，包括III族元素、IV族元素及V族元素。可在衬底101中和/或衬底101上形成有源装置103(例如晶体管)。
在衬底101之上形成内连结构105。在一些实施例中，内连结构105可包括由例如k值低于约4.0的低介电常数介电材料形成的至少一个介电层。在一些实施例中，内连结构105的介电层可由例如氧化硅、SiCOH等制成。内连结构105还可包括在介电层中形成的金属线及通孔(即，连接结构)。举例来说，内连结构105可包括经由通孔进行内连的多个金属层。金属线及通孔可由铜或铜合金形成，且金属线及通孔也可由其他金属形成。可通过以下方式来形成金属线及通孔：在介电层中刻蚀出开口，以导电材料来填充开口，以及执行平坦化(例如化学机械抛光(chemical mechanical polishing，CMP))以使金属线的顶表面及通孔的顶表面与介电层的顶表面齐平。
在内连结构105之上形成顶部金属层111。顶部金属层111包括介电层109及导电特征107。通过在内连结构105的顶表面之上沉积介电层109来形成顶部金属层111。可通过化学气相沉积(chemical vapor deposition，CVD)、物理气相沉积(physical vapordeposition，PVD)等来沉积介电层109。介电层可包含与内连结构105的介电层的材料相同的材料。举例来说，在一些实施例中，介电层109可由氧化硅、SiCOH等制成。
接着可对介电层109进行刻蚀以形成暴露出内连结构105的顶表面的开口。可通过例如镀覆工艺在开口中沉积导电特征107。接着可通过例如化学机械抛光等工艺将导电特征107平坦化。导电特征107可由铜或铜合金制成。也可使用例如铝、铝合金等其他材料来形成导电特征107。如图1所示，导电特征107可为分立(discrete)的特征。举例来说，导电特征107可通过介电层109彼此分隔以及彼此电隔离。根据其他实施例，导电特征107可为连续金属特征的部分。
在顶部金属层111之上形成钝化层113。在实施例中，钝化层113可为聚苯并噁唑(polybenzoxazole，PBO)，但作为另外一种选择也可利用例如苯并环丁烯(benzocyclobutene，BCB)、聚酰亚胺(polyimide)或聚酰亚胺衍生物等任何合适的材料。可利用例如旋转涂布工艺来放置钝化层113，但作为另外一种选择也可利用任何合适的方法。
可在钝化层113中形成重布线通孔(redistribution via)115。举例来说，可将钝化层113图案化以形成开口，导电特征107中的一者经由所述开口被暴露出。可利用光刻技术来执行钝化层113的图案化。接着可在钝化层113中的开口中形成重布线通孔115。重布线通孔115可由铝、铝合金、铜或铜合金制成，但也可使用其他金属材料。
图2示出测试垫201的形成。在重布线通孔115之上形成测试垫201且测试垫201接触重布线通孔115。测试垫201经由导电特征(例如在内连结构105中形成的金属线及通孔、导电特征107以及重布线通孔115)电耦合到有源装置103。测试垫201可由铝或铝合金形成，但也可使用其他金属材料。可通过毯覆沉积(blanket deposition)来形成测试垫201。举例来说，可利用CVD、PVD等在钝化层113及重布线通孔115的表面之上沉积铝层。接着可在铝层之上形成光刻胶层(图中未单独示出)，且可对铝层进行刻蚀以形成测试垫201。在一些实施例中，测试垫201可具有介于约与约之间(例如为约)的高度H1。在各种实施例中，测试垫201可具有介于约1.8μm与约31.5μm之间(例如为约2μm)的宽度W1。测试垫201可具有介于约20μm与约100μm之间(例如为约50μm)的长度(图中未单独示出)。此外，在一些实施例中，测试垫201可定位在已完成的半导体装置的隅角或边缘区中。在其他实施例中，测试垫201可放置在已完成的半导体装置的中心区中。
根据至少一个实施例，测试垫201与重布线通孔115可同时形成。举例来说，可在顶部金属层111之上形成钝化层113且可将钝化层113图案化以暴露出导电特征107中的一者。可通过毯覆沉积来形成测试垫201及重布线通孔115。举例来说，可利用CVD、PVD等在钝化层113的表面之上、在钝化层113中形成的开口中以及在被暴露的导电特征107之上沉积铝层。接着可在铝层之上形成光刻胶层(图中未单独示出)，且可对铝层进行刻蚀以形成测试垫201。
图3示出探测步骤，所述探测步骤可为晶片接受测试(wafer-acceptance-test)或电路测试的一部分。执行探测以验证有源装置103以及相应的电连接结构(例如，内连结构150中的连接结构、导电特征107及重布线通孔115)的功能。可通过使探测针(probeneedle)301接触测试垫201来执行探测。探测针301可为具有多个探测针的探针卡的一部分，例如，其连接到测试设备(图中未单独示出)。如果管芯100通过晶片接受测试，则管芯是已知良好管芯(known gooddie，KGD)。
图4示出结合层401的形成。在钝化成113的顶表面之上以及在测试垫201的顶表面及侧表面之上沉积结合层401。结合层401可用于熔融结合(也被称为氧化物对氧化物结合(oxide-to-oxide bonding))。根据一些实施例，结合层401是由含硅的介电材料(例如氧化硅、氮化硅等)形成。可利用任何合适的方法(例如，CVD、高密度等离子体化学气相沉积(high-density plasma chemical vapor deposition，HDPCVD)、PVD、原子层沉积(atomiclayer deposition，ALD)等)来沉积结合层401。可例如在化学机械抛光(CMP)工艺中将结合层401平坦化。结合层401可具有介于约0.65μm与约6μm之间(例如为约5.5μm)的厚度T1。结合层401的顶表面高于测试垫201的顶表面。结合层401可被称为钝化层或介电层。
图5示出在结合层401中形成第一开口501以暴露出测试垫201。在结合层401的顶表面之上施加第一光刻胶503并将第一光刻胶503图案化。接着使用第一光刻胶503对结合层401进行刻蚀以形成第一开口501。可通过干式刻蚀(例如，反应离子刻蚀(reactive ionetching，RIE)或中性束刻蚀(neutral beam etching，NBE))、湿式刻蚀等来对结合层401进行刻蚀。根据本公开的一些实施例，刻蚀停止于测试垫201上，使得经由结合层401中的第一开口501暴露出测试垫201。第一开口501可具有介于约1.2μm与约2μm之间(例如为约1.4μm)的宽度W2。
图6示出在结合层401及钝化层113中形成第二开口601以暴露出导电特征107。在结合层401的顶表面及测试垫201的顶表面之上以及在开口501中施加第二光刻胶603，且将第二光刻胶603图案化。接着将第二光刻胶603与一种或多种刻蚀一起使用来对结合层401及钝化层113进行刻蚀以形成第二开口601。用于形成第二开口601的刻蚀可与用于形成第一开口501的刻蚀相同或不同，且可包括干式刻蚀(例如，RIE或NBE)、湿式刻蚀等。根据本公开的一些实施例，刻蚀停止于导电特征107上，使得经由结合层401及钝化层113中的第二开口601暴露出导电特征107。第二开口601可具有介于约1.2μm与约2μm之间(例如为约1.4μm)的宽度W3。根据各种实施例，宽度W3可与宽度W2相同或不同。宽度W2对宽度W3的比率可介于约1.2与约0.8之间(例如为约1)。
图7示出在结合层401中可选地形成第三开口701及第四开口703以分别使第一开口501及第二开口601的部分变宽。在结合层401的顶表面、测试垫201的顶表面及导电特征107的顶表面之上以及在第一开口501及第二开口601中施加第三光刻胶705。将第三光刻胶705图案化，并接着使用第三光刻胶705对结合层401进行刻蚀以形成第三开口701及第四开口703。可通过干式刻蚀(例如，RIE或NBE)、湿式刻蚀等来对结合层401进行刻蚀。可在第一开口501及测试垫201上方形成第三开口701。可在第二开口601及导电特征107上方形成第四开口703。第三开口701可具有宽度W4及深度D1。宽度W4可介于约2.2μm与约4.5μm之间(例如为约2.3μm)。深度D1可介于约0.8μm与约3.4μm之间(例如为约0.85μm)。第四开口703可具有宽度W5及深度D2。宽度W5可介于约2.2μm与约4.5μm之间(例如为约2.3μm)。深度D2可介于约0.8μm与约3.4μm之间(例如为约0.85μm)。根据各种实施例，宽度W4可与宽度W5相同或不同，且深度D1可与深度D2相同或不同。宽度W4对宽度W5的比率可介于约0.5与约1.8之间(例如为约1)。深度D1对深度D2的比率可介于约0.8与约1.2之间(例如为约1)。
图8示出以晶种层801及板金属803来填充第一开口501、第二开口601、第三开口701及第四开口703。可在结合层401的顶表面、测试垫201的顶表面及导电特征107的顶表面以及第一开口501的侧壁、第二开口601的侧壁、第三开口701的侧壁及第四开口703的侧壁之上毯覆沉积晶种层801。晶种层801可包括铜层。可依据所期望的材料而使用例如溅射、蒸镀或等离子体增强型化学气相沉积(plasma-enhanced chemical vapor deposition，PECVD)等工艺来沉积晶种层801。可通过例如电镀或无电镀覆等镀覆工艺在晶种层801之上沉积板金属803。板金属803可包含铜、铜合金等。板金属803可为填充材料。可在晶种层801之前，在结合层401的顶表面、测试垫201的顶表面及导电特征107的顶表面以及第一开口501的侧壁、第二开口601的侧壁、第三开口701的侧壁及第四开口703的侧壁之上毯覆沉积障壁层(图中未单独示出)。障壁层可包含钛、氮化钛、钽、氮化钽等。
图9示出包括第一结合垫901及第二结合垫903的管芯900。在填充第一开口501、第二开口601、第三开口701及第四开口703之后，如图8所示，执行平坦化工艺(例如，CMP)以移除晶种层801及板金属803的导电材料的多余的部分，从而形成第一结合垫901及第二结合垫903。第一结合垫901可接触测试垫201，且第二结合垫903可接触导电特征107。根据至少一个实施例，第一结合垫901的顶表面与第二结合垫903的顶表面彼此共面且与结合层401的顶表面共面。第一结合垫901的顶部部分填充第三开口701，具有宽度W4，且可被称为结合垫金属。第二结合垫903的顶部部分填充第四开口703，具有宽度W5，且也可被称为结合垫金属。第一结合垫901的下部部分填充第一开口501，具有宽度W2，且可被称为结合垫通孔。第二结合垫903的下部部分填充第二开口601，具有宽度W3，且也可被称为结合垫通孔。
图10示出用于将管芯900结合到封装组件1000的加工步骤的剖视图。根据本公开的一些实施例，封装组件1000是装置管芯、中介管芯、封装衬底或封装。根据实施例，封装组件1000可为与管芯900镜像对称的装置管芯。封装组件1000包括第一结合垫1001、第二结合垫1003及介电层1005。第一结合垫1001可与第一结合垫901相似，第二结合垫1003可与第二结合垫903相似，且介电层1005可与结合层401相似。举例来说，介电层1005的顶表面与第一结合垫1001的顶表面及第二结合垫1003的顶表面共面。第一结合垫1001及第二结合垫1003可包含导电材料(例如铜、铜合金等)。介电层1005可为包括含硅的介电层(例如，氧化硅层、氮化硅层等)。
在一些实施例中，通过例如混合结合将管芯900结合到封装组件1000。在将管芯900的顶表面及封装组件1000的顶表面平坦化之后，可将管芯900的顶表面及封装组件1000的顶表面激活(activation)。将管芯900的顶表面及封装组件1000的顶表面激活可包括干式处理、湿式处理、等离子体处理、暴露于惰性气体、暴露于H2、暴露于N2或暴露于O2或者其组合作为实例。在其中利用湿式处理的实施例中，例如可利用RCA清洗(RCA clean)。在另一实施例中，激活工艺可包括其他类型的处理。激活工艺有助于管芯900与封装组件1000的混合结合；有利地允许在后续混合结合工艺中使用更低压力及温度。
在激活工艺之后，可利用化学冲洗剂来清洗管芯900及封装组件1000。接着使晶片总成经受热处理及接触压力以将管芯900混合结合到封装组件1000。可使管芯900及封装组件1000经受约200kPa或小于200kPa的压力以及介于约200℃与约400℃之间的温度，以将结合层401及介电层1005熔融。接着可使管芯900及封装组件1000经受处于第一结合垫901、第二结合垫903、第一结合垫1001及第二结合垫1003的材料的共熔点(eutectic point)或高于所述共熔点(例如，介于约150℃与约650℃之间)的温度，以将金属结合垫熔融。以此种方式，管芯900及封装组件1000的熔融会形成混合结合的装置。在一些实施例中，对结合的管芯进行烘烤、退火、按压或以其他方式进行处理以加强或完成所述结合。
在其他实施例中，可通过直接表面结合、金属对金属结合或另一结合工艺来将管芯900结合到封装组件1000。直接表面结合工艺通过清洗和/或表面激活工艺、然后对接合的表面施加压力、热量和/或其他结合工艺步骤形成氧化物对氧化物结合或衬底对衬底结合。在一些实施例中，通过将导电元件熔融而实现的金属对金属结合对管芯900与封装组件1000进行结合。举例来说，通过金属对金属结合将结合垫1001及1003分别结合到结合垫901及903。
形成接触测试垫201的第一结合垫901可增加可对管芯900中的有源装置103进行连接的连接结构的数目。此外，接触测试垫201的第一结合垫901可增大位于不包括第一结合垫901的装置之上的引脚输出区域(pin out area)。举例来说，管芯900的引脚输出区域可比一般管芯的引脚输出区域大介于约3,000个引脚与约700个引脚之间(例如大约30％)。
图11示出根据另一实施例的在结合层401中形成第一开口1101及第二开口1103以及形成凹陷的测试垫1107。在结合层401中形成第一开口1101及第二开口1103之前，半导体管芯1100可与图4所示半导体管芯100相同或相似。在结合层401的顶表面之上施加第一光刻胶1105并将第一光刻胶1105图案化。接着使用第一光刻胶1105对结合层401进行刻蚀以同时形成第一开口1101及第二开口1103。可通过干式刻蚀(例如，RIE或NBE)、湿式刻蚀等来对结合层401进行刻蚀。可通过单一刻蚀或通过多次刻蚀对结合层401进行刻蚀。此外，如果利用多次刻蚀来对结合层401进行刻蚀，则刻蚀中的每一者可利用相同的刻蚀工艺或不同的刻蚀工艺。
根据本公开的一些实施例，当第二开口1103到达导电特征107时停止刻蚀，使得经由结合层401中的第二开口1103暴露出导电特征107。由于第一开口1101是在与第二开口1103相同的时间被刻蚀，因此所述刻蚀可暴露出测试垫201，且刻蚀到测试垫201中达深度D3，使得形成凹陷的测试垫1107。深度D3可介于约与约之间(例如为约)。开口1101可具有介于约1.2μm与约2μm之间(例如为约1.4μm)的宽度W6，且开口1103可具有介于约1.2μm与约2μm之间(例如为约1.4μm)的宽度W7。根据各种实施例，宽度W6可与宽度W7相同或不同。宽度W6对宽度W7的比率可介于约0.8与约1.2之间(例如为约1)。
图12示出在结合层401中形成第三开口1201及第四开口1203以分别使第一开口1101及第二开口1103的部分变宽。在结合层401的顶表面、测试垫1107的顶表面及导电特征107的顶表面之上以及在第一开口1101及第二开口1103中施加第二光刻胶1205。将第二光刻胶1205图案化，并接着使用第二光刻胶1205对结合层401进行刻蚀以形成第三开口1201及第四开口1203。可在第一开口1101及测试垫1107上方形成第三开口1201。可在第二开口1103及导电特征107上方形成第四开口1203。第三开口1201可具有宽度W8及深度D4。宽度W8可介于约2.2μm与约4.5μm之间(例如为约2.3μm)。深度D4可介于约0.8μm与约3.4μm之间(例如为约0.85μm)。第四开口1203可具有宽度W9及深度D5。宽度W9可介于约2.2μm与约4.5μm之间(例如为约2.3μm)。深度D5可介于约0.8μm与约3.4μm之间(例如为约0.85μm)。根据各种实施例，宽度W8可与宽度W9相同或不同。宽度W8对宽度W9的比率可介于约0.5与约1.5之间(例如为约1)。第三开口1201及第四开口1203的宽度W7及宽度W8分别大于第一开口1101及第二开口1103的宽度W5及宽度W6。更具体来说，第三开口1201的宽度W8对第一开口1101的宽度W6的比率介于约1.1与约4之间(例如为约1.6)，且第四开口1203的宽度W9对第二开口1103的宽度W7的比率介于约1.1与约4之间(例如为约1.6)。
图13示出以晶种层1301及板金属1303来填充第一开口1101、第二开口1103、第三开口1201及第四开口1203。可在结合层401的顶表面、测试垫201的顶表面及导电特征107的顶表面以及第一开口1101的侧壁、第二开口1103的侧壁、第三开口1201的侧壁及第四开口1203的侧壁之上毯覆沉积晶种层1301。晶种层1301可包括铜层。可通过例如电镀或无电镀覆等镀覆工艺在晶种层1301之上沉积板金属1303。板金属1303可包含铜、铜合金等。也可在晶种层1301之前，在结合层401的顶表面、凹陷的测试垫1107的凹陷部分的顶表面及导电特征107的顶表面以及第一开口1101的侧壁、第二开口1103的侧壁、第三开口1201的侧壁及第四开口1203的侧壁之上毯覆沉积障壁层(图中未单独示出)。障壁层可包含钛、氮化钛、钽、氮化钽等。
图14示出包括第一结合垫1401及第二结合垫1403的管芯1400。在填充第一开口1101、第二开口1103、第三开口1201及第四开口1203(如图13所示)之后，执行平坦化工艺(例如，CMP)以移除晶种层1301及板金属1303的导电材料的多余的部分，从而形成第一结合垫1401及第二结合垫1403。第一结合垫1401可接触凹陷的测试垫1107，且第二结合垫1403可接触导电特征107。根据至少一个实施例，第一结合垫1401的顶表面与第二结合垫1403的顶表面彼此共面且与结合层401的顶表面共面。第一结合垫1401的顶部部分填充第三开口1201，具有宽度W8，且可被称为结合垫金属。第二结合垫1403的顶部部分填充第四开口1203，具有宽度W9，且也可被称为结合垫金属。第一结合垫1401的下部部分填充第一开口1101，具有宽度W6，且可被称为结合垫通孔。第二结合垫1403的下部部分填充第二开口1103，具有宽度W7，且也可被称为结合垫通孔。
形成接触凹陷的测试垫1107的第一结合垫1401可增加可对管芯1400中的有源装置103进行连接的连接结构的数目。此外，接触凹陷的测试垫1107的第一结合垫1401可增大位于不包括第一结合垫1401的装置之上的引脚输出区域。举例来说，管芯1400的引脚输出区域可比一般管芯的引脚输出区域大介于约3,000个引脚与约700个引脚之间(例如大约30％)。另外，包括凹陷的测试垫1107的第二实施例可减少形成管芯1400所需要的步骤的数目，且可节省成本。第二实施例可增加第一结合垫1401与凹陷的测试垫1107之间的接触的表面积。
根据实施例，一种制造半导体装置的方法包括：在衬底之上形成第一导电特征及第二导电特征；在所述第一导电特征之上形成测试垫且将所述测试垫电性连接到所述第一导电特征；在所述测试垫及所述第二导电特征之上形成结合层；对所述结合层进行刻蚀以形成延伸到所述测试垫的第一开口；对所述结合层进行刻蚀以形成延伸到所述第二导电特征的第二开口；以及分别在所述第一开口及所述第二开口中形成第一结合垫及第二结合垫，所述第一结合垫电耦合到所述测试垫，且所述第二结合垫电耦合到所述第二导电特征。在实施例中，所述方法还包括：在所述第一导电特征及所述第二导电特征之上形成钝化层；对所述钝化层进行刻蚀以形成暴露出所述第一导电特征的第三开口；以及在所述第三开口中形成通孔，所述形成所述测试垫会将所述测试垫经由所述通孔电连接到所述第一导电特征。在实施例中，对所述结合层进行刻蚀以形成所述第二开口还包括：对所述钝化层进行刻蚀以暴露出所述第二导电特征，所述形成所述第二结合垫会形成延伸穿过所述结合层及所述钝化层的所述第二结合垫。在实施例中，所述第一导电特征及所述第二导电特征包含第一导电材料，且所述测试垫包含与所述第一导电材料不同的第二导电材料。在实施例中，所述第一导电材料是铜，且所述第二导电材料是铝。在实施例中，所述的方法还包括形成介电层，所述介电层将所述第一导电特征与所述第二导电特征电隔离。在实施例中，所述方法还包括对所述结合层进行刻蚀以形成第三开口，所述第三开口设置在所述第一开口及所述第二开口中的至少一者上方，且所述第三开口的宽度大于所述第一开口的宽度或所述第二开口的宽度。在实施例中，在对所述结合层进行刻蚀以形成所述第一开口之后，对所述结合层进行刻蚀以形成所述第二开口。
根据另一实施例，一种制造半导体装置的方法包括：在内连结构之上形成第一导电特征及第二导电特征，所述内连结构位于衬底之上；在所述第一导电特征之上形成测试垫且将所述测试垫电连接到所述第一导电特征；对所述测试垫进行探测以确定所述测试垫与所述内连结构之间的电连接；在所述测试垫及所述第二导电特征之上形成介电层；穿过所述介电层形成第一结合垫，所述第一结合垫接触所述测试垫；以及穿过所述介电层形成第二结合垫，所述第二结合垫接触所述第二导电特征，且所述第二结合垫的高度大于所述第一结合垫的高度。在实施例中，所述第一结合垫与所述第二结合垫是同时形成的。在实施例中，所述第一结合垫的最底表面设置在所述测试垫的最顶表面下方有一定距离。在实施例中，所述距离介于约与约之间。在实施例中，所述方法还包括：同时对所述介电层进行刻蚀以形成延伸到所述测试垫的第一开口及延伸到所述第二导电特征的第二开口，所述第一结合垫形成在所述第一开口中，且所述第二结合垫形成在所述第二开口中。在实施例中，所述第一结合垫的宽度对所述第二结合垫的宽度的比率介于约0.5与约1.8之间。
根据再一实施例，一种集成电路包括：第一金属特征及第二金属特征，以单一顶部金属层形式设置在衬底之上；测试垫，位于所述第一金属特征之上且电连接到所述第一金属特征；第一钝化层，位于所述第二金属特征及所述测试垫之上且覆盖所述测试垫的顶表面及侧表面；第一通孔，穿透所述第一钝化层以接触所述测试垫；以及第二通孔，穿透所述第一钝化层以接触所述第二金属特征。在实施例中，所述集成电路还包括：第二钝化层，设置在所述第一钝化层与所述单一顶部金属层之间，所述第二钝化层将所述测试垫与所述第一金属特征分隔开；以及第三通孔，延伸穿过所述第二钝化层，所述第三通孔将所述测试垫电连接到所述第一金属特征。在实施例中，所述测试垫的所述顶表面包括凹槽，且所述第一通孔的至少一部分设置在所述凹槽中。在实施例中，所述第一金属特征及所述第二金属特征包含第一导电材料，且所述测试垫包含与所述第一导电材料不同的第二导电材料。在实施例中，所述第一导电材料是铜，且所述第二导电材料是铝。在实施例中，所述第二通孔的高度大于所述第一通孔与所述测试垫组合的高度。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本公开的各个方面。所属领域中的技术人员应理解，其可容易地使用本公开作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的和/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，这些等效构造并不背离本公开的精神及范围，而且他们可在不背离本公开的精神及范围的条件下对其作出各种改变、代替及变更。

Claims (1)

1.一种制造半导体装置的方法，其特征在于，包括：
在衬底之上形成第一导电特征及第二导电特征；
在所述第一导电特征之上形成测试垫且将所述测试垫电性连接到所述第一导电特征；
在所述测试垫及所述第二导电特征之上形成结合层；
对所述结合层进行刻蚀以形成延伸到所述测试垫的第一开口；
对所述结合层进行刻蚀以形成延伸到所述第二导电特征的第二开口；以及
分别在所述第一开口及所述第二开口中形成第一结合垫及第二结合垫，其中所述第一结合垫电耦合到所述测试垫，且所述第二结合垫电耦合到所述第二导电特征。
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CN112526315A (zh) * 2020-11-05 2021-03-19 长江存储科技有限责任公司 一种封装芯片的测试方法
CN112526315B (zh) * 2020-11-05 2021-11-12 长江存储科技有限责任公司 一种封装芯片的测试方法

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