CN109801965A - 具有双层间隙壁的晶体管及其形成方法 - Google Patents

具有双层间隙壁的晶体管及其形成方法 Download PDF

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CN109801965A
CN109801965A CN201711146633.3A CN201711146633A CN109801965A CN 109801965 A CN109801965 A CN 109801965A CN 201711146633 A CN201711146633 A CN 201711146633A CN 109801965 A CN109801965 A CN 109801965A
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layer
double
wall
transistor
gap wall
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CN109801965B (zh
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王家麟
江品宏
熊昌铂
吕佳纹
李年中
李文芳
王智充
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US15/846,150 priority patent/US10453938B2/en
Priority to US16/258,679 priority patent/US10475903B2/en
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Abstract

本发明公开一种具有双层间隙壁的晶体管及其形成方法。该具有双层间隙壁的晶体管，包含有一栅极、一第一双层间隙壁以及一第二内层间隙壁。栅极设置于一基底上，其中栅极包含一栅极介电层以及一栅极电极，以及栅极介电层自栅极电极突出并覆盖基底。第一双层间隙壁设置于栅极侧边的栅极介电层上，其中第一双层间隙壁包含一第一内层间隙壁以及一第一外层间隙壁。第二内层间隙壁设置于第一双层间隙壁侧边的栅极介电层上，其中第二内层间隙壁具有一L型剖面结构。

Description

具有双层间隙壁的晶体管及其形成方法
技术领域
本发明涉及一种具有间隙壁的晶体管及其形成方法，且特别是涉及一种具有双层间隙壁的晶体管及其形成方法。
背景技术
在集成电路的制造过程中，场效晶体管(field effect transistor)是一种极重要的电子元件。现有的晶体管制作工艺是在基底上形成栅极结构之后，再于栅极结构相对两侧的基底中形成轻掺杂漏极结构(lightly doped drain,LDD)。接着于栅极结构侧边形成间隙壁(spacer)，并以此栅极结构及间隙壁做为掩模，进行离子注入步骤，以于基底中形成源极/漏极区。而为了要将晶体管的栅极、源极、与漏极适当电连接于电路中，因此需要形成接触插塞来进行导通。接触插塞中更形成有阻障层围绕其中的低电阻率材料以防止低电阻率材料向外扩散至其他区域等。
随着半导体元件的尺寸越来越小，晶体管的制作工艺步骤也有许多的改进，以制造出体积小而高品质的晶体管。例如，可通过改良间隙壁的形状、尺寸以及在元件中的相对位置以提升半导体元件的效能。
发明内容
本发明提出一种具有双层间隙壁的晶体管及其形成方法，其形成多层双层间隙壁，并通过将双层间隙壁的内层间隙壁设置为具有L型剖面结构，以调整源/漏极至栅极的距离。
本发明提供一种具有双层间隙壁的晶体管，包含有一栅极、一第一双层间隙壁以及一第二内层间隙壁。栅极设置于一基底上，其中栅极包含一栅极介电层以及一栅极电极，以及栅极介电层自栅极电极突出并覆盖基底。第一双层间隙壁设置于栅极侧边的栅极介电层上，其中第一双层间隙壁包含一第一内层间隙壁以及一第一外层间隙壁。第二内层间隙壁设置于第一双层间隙壁侧边的栅极介电层上，其中第二内层间隙壁具有一L型剖面结构。
本发明提供一种具有双层间隙壁的晶体管，包含有一栅极介电层、一栅极电极、一间隙壁以及一第一双层间隙壁。栅极介电层设置于一基底上。栅极电极设置于栅极介电层上。间隙壁设置于栅极电极侧边的栅极介电层上。第一双层间隙壁设置于间隙壁侧边的栅极介电层上，其中第一双层间隙壁包含一第一内层间隙壁具有一L型剖面结构。
本发明提供一种形成具有双层间隙壁的晶体管的方法，包含有下述步骤。首先，形成一栅极介电层以及一栅极电极于一基底上。接着，形成一第一双层间隙壁于栅极电极侧边的栅极介电层上，其中第一双层间隙壁包含一第一内层间隙壁以及一第一外层间隙壁。接续，形成一第二双层间隙壁于第一双层间隙壁侧边的栅极介电层上，其中第二双层间隙壁包含一第二内层间隙壁以及一第二外层间隙壁，且第二内层间隙壁具有一L型剖面结构。之后，移除第二外层间隙壁。
基于上述，本发明提出一种具有双层间隙壁的晶体管及其形成方法，其形成多个双层间隙壁，以调整源/漏极至栅极的距离，俾能防止源/漏极至栅极之间所产生的高电场，而达到提升元件的所需电性需求的目的。并且，通过将双层间隙壁的内层间隙壁设置为具有L型剖面结构，可进一步避免例如源/漏极或金属硅化物等形成位置太靠近栅极。
附图说明
图1～图10为本发明一实施例的形成具有双层间隙壁的晶体管的方法的剖面示意图。
主要元件符号说明
10：隔离结构
110：基底
120、120a：栅极介电层
122a、122b：高介电常数介电层
124a、124b：牺牲电极层
130a、130b：盖层
132a、132b：氮化层
134a、134b：氧化层
142a、142b：间隙壁
144a、144b：轻掺杂源/漏极
150a、150b：第一双层间隙壁
152：第一内层间隙壁材料
154：第一外层间隙壁材料
152a、152b：第一内层间隙壁
154a、154b：第一外层间隙壁
160b：第二双层间隙壁
162、162a：第二内层间隙壁材料
164、164a：第二外层间隙壁材料
162b：第二内层间隙壁
164b：第二外层间隙壁
166：源/漏极
166a：金属硅化物
170：接触洞蚀刻停止层
A：第一区
B：第二区
E1：第一栅极电极
E2：第二栅极电极
G1：第一栅极
G2：第二栅极
K1：第一部分
K2：第二部分
K3：第三部分
K4：第四部分
M1：第一金属栅极
M2：第二金属栅极
P1、P2：光致抗蚀剂
R1：凹槽
S1：平坦的顶面
t1、t2、t3、t4、t5、t6：厚度
W1、W2：宽度
具体实施方式
以下的实施例中，本发明的半导体制作工艺应用于一前置缓冲层及前置高介电常数介电层的后栅极制作工艺(Gate Last for High-K First,Buffer layer FirstProcess)，但本发明不以此为限。再者，为简化本发明，以下的实施例以二晶体管为例，但本发明也可能应用的晶体管个数非限于此。
图1～图10绘示的是本发明一实施例的形成具有双层间隙壁的晶体管的方法的剖面示意图。如图1所示，形成一第一栅极G1以及一第二栅极G2于一基底110上。基底110例如是一硅基底、一含硅基底、一三五族覆硅基底(例如GaN-on-silicon)、一石墨烯覆硅基底(graphene-on-silicon)或一硅覆绝缘(silicon-on-insulator，SOI)基底等半导体基底。基底110包含一第一区A以及一第二区B。在本实施例中，第一栅极G1位于第一区A，而第二栅极G2位于第二区B，且第一区A为一逻辑电路的主动区等一低压电路的主动区，而第二区B为一高压电路的主动区，因而所形成的第一栅极G1为一低电压晶体管的一栅极，而第二栅极G2为一中电压晶体管的一栅极，但本发明不以此为限。因此，在本实施例中的第一栅极G1的尺寸小于第二栅极G2的尺寸，而第一栅极G1在栅极通道长度方向上的宽度W1小于第二栅极G2在栅极通道长度方向上的宽度W2，但本发明不以此为限。
详细而言，形成具有不同尺寸的第一栅极G1以及第二栅极G2于基底110上的步骤：可先在基底110上以蚀刻及光刻程序形成平坦的一隔离结构10。在本实施例中，隔离结构10例如为一浅沟隔离(shallow trench isolation,STI)结构，其例如以一浅沟隔离制作工艺形成，但本发明不以此为限。当然，在其他实施例中，隔离结构10可为一场氧化层(fieldoxide,FOX)等的绝缘结构，本发明不以此为限。
续之，可先选择性形成一凹槽R1于第二区B的基底110中，然后再全面形成栅极介电层120于第一区A以及第二区B的基底110上，因而第一区A的栅极介电层120的一厚度t1小于第二区B的栅极介电层120的一厚度t2。如此一来，本实施例的栅极介电层120具有一平坦的顶面S1。栅极介电层120可例如为以一原处蒸汽产生(in-situ steam generation,ISSG)制作工艺或热氧化制作工艺形成，但本发明不以此为限。在其他实施例中，也可先全面形成等厚度的介电层于第一区A及第二区B中，而后再移除部分或者薄化位于第一区A的介电层，因而可在第一区A的基底110上形成一较第二区B的介电层厚度薄的介电层(未绘示)。如此，本发明便可于第一区A及第二区B上形成不同厚度的介电层。
之后，如图1所示，分别形成一第一栅极电极E1及一第二栅极电极E2于第一区A的栅极介电层120以及第二区B的栅极介电层120上。如此一来，栅极介电层120自第一栅极电极E1及第二栅极电极E2突出并覆盖基底110。详细而言，第一栅极电极E1由下而上可包含一高介电常数介电层122a、一牺牲电极层124a以及一盖层130a，且盖层130a由下而上可包含一氮化层132a及一氧化层134a；第二栅极电极E2由下而上可包含一高介电常数介电层122b、一牺牲电极层124b以及一盖层130b，且盖层130b由下而上可包含一氮化层132b及一氧化层134b，但本发明不以此为限。依序形成堆迭的一高介电常数介电层122a/122b、一牺牲电极层124a/124b以及一盖层130a/130b的方法可包含：先依序全面堆迭一高介电常数介电层(未绘示)、一牺牲电极层(未绘示)以及一盖层(未绘示)于第一区A以及第二区B的栅极介电层120上；然后，图案化盖层(未绘示)、牺牲电极层(未绘示)以及高介电常数介电层(未绘示)，而分别形成第一栅极电极E1及第二栅极电极E2。
然后，分别形成一间隙壁142a/142b于第一栅极G1以及第二栅极G2侧边的基底110(栅极介电层120)上。间隙壁142a/142b例如是以氮化硅或氧化硅等材质所组成的单层或多层复合结构。在本实施例中，间隙壁142a/142b为一单层的氮化间隙壁。而后，进行一轻掺杂离子注入制作工艺，以分别形成一轻掺杂源/漏极144a/144b于间隙壁142a/142b侧边的基底110中。轻掺杂源/漏极144a及轻掺杂源/漏极144b可依所需浓度分别形成，间隙壁142a/142b则分别定义轻掺杂源/漏极144a/144b形成的位置。轻掺杂离子注入制作工艺的掺杂杂质可例如为硼或磷等三价或五价的离子，视所欲形成的第一栅极G1以及第二栅极G2的电性而定。在本实施例中，第一栅极G1与第二栅极G2具有相同的导电型，但不同的尺寸，因此轻掺杂源/漏极144a/144b具有相同导电型，但可为不同种类或不同浓度的离子；但在其他实施例中第一栅极G1与第二栅极G2也可能为不同的导电型。
如图2～图3所示，分别形成一第一双层间隙壁150a/150b于栅极电极E1/E2侧边的栅极介电层120上。在本实施例中，第一双层间隙壁150a及第一双层间隙壁150b为相同间隙壁，具有相同尺寸及相同厚度，且同时形成，但在其他实施例中，第一双层间隙壁150a及第一双层间隙壁150b可为不同间隙壁且分别形成。第一双层间隙壁150a/150b例如是以氮化硅或氧化硅等材质所组成的单层或多层复合结构。在本实施例中，各第一双层间隙壁150a/150b皆包含一第一内层间隙壁152a/152b以及一第一外层间隙壁154a/154b，且第一内层间隙壁152a/152b具有一L型剖面结构，但本发明不以此为限。较佳者，第一内层间隙壁152a/152b为一氧化间隙壁，如此第一内层间隙壁152a/152b能与间隙壁142a/142b(，其为一单层的氮化间隙壁)具有不同材质，而在后续蚀刻制作工艺中具有蚀刻选择比；相同地，第一外层间隙壁154a/154b较佳为一氮化间隙壁，俾能与第一内层间隙壁152a/152b具有不同材质，而在后续蚀刻制作工艺中具有蚀刻选择比，但本发明不以此为限。
详细而言，可先形成一第一内层间隙壁材料152以及一第一外层间隙壁材料154，全面覆盖栅极介电层120及栅极电极E1/E2，接着蚀刻第一外层间隙壁材料154以及第一内层间隙壁材料152，因而同时形成第一双层间隙壁150a/150b，其包含第一内层间隙壁152a/152b具有L型剖面结构。
如图4所示，形成一第二内层间隙壁材料162以及一第二外层间隙壁材料164，全面覆盖栅极介电层120以及栅极电极E1/E2。在本实施例中，第二内层间隙壁材料162为一氧化层，而第二外层间隙壁材料164为一氮化层，但本发明不以此为限。形成第二内层间隙壁材料162以及第二外层间隙壁材料164的方法可例如以应力记忆技术(stress memorizationtechnique,SMT)形成，因而第二外层间隙壁材料164可例如为一具有应力的材料层。
如图5～图6所示，仅蚀刻第二区B的第二外层间隙壁材料164以及第二内层间隙壁材料162，因而在第二区B形成一第二双层间隙壁160b。如图5所示，可先覆盖一光致抗蚀剂P1于第一区A，并暴露出第二区B；图6所示，蚀刻暴露出的第二区B的第二外层间隙壁材料164以及第二内层间隙壁材料162，以仅在第二区B形成第二双层间隙壁160b，并留下第一区A的第二内层间隙壁材料162a及第二外层间隙壁材料164a；随即，移除光致抗蚀剂P1。第二双层间隙壁160b则包含一第二内层间隙壁162b以及一第二外层间隙壁164b，且第二内层间隙壁162b具有一L型剖面结构。
在此强调，在蚀刻第二区B的第二外层间隙壁材料164以及第二内层间隙壁材料162时，第二区B的栅极介电层120也会被蚀刻而薄化成一栅极介电层120a。突出自第二栅极电极E2的栅极介电层120a至少可包含一第一部分K1以及一第二部分K2，其中第一部分K1位于第二内层间隙壁162b正下方，而第二内层间隙壁162b未覆盖第二部分K2(即暴露出的栅极介电层120a)。由于第二部分K2在蚀刻第二区B的第二外层间隙壁材料164以及第二内层间隙壁材料162时被薄化，因而第一部分K1的一厚度t3大于第二部分K2的一厚度t4。
如图7所示，可先覆盖一光致抗蚀剂P2于第一区A，并暴露出第二区B，再进行一离子注入制作工艺以形成一源/漏极166于第二区B的第二双层间隙壁160b侧边的基底110中。离子注入制作工艺的掺杂杂质可例如为硼或磷等三价或五价的离子，视所欲形成的第二栅极G2的电性而定。随即，移除光致抗蚀剂P2。
之后，移除第二外层间隙壁164b，并保留第二内层间隙壁162b，如图8所示。在本实施例中，移除第二区B的第二外层间隙壁164b的同时，一并移除第一区A的第二外层间隙壁材料164a，但保留第二内层间隙壁材料162a。
如图9所示，在移除第二区B的第二外层间隙壁164b之后，可进行一自对准金属硅化物制作工艺，形成一金属硅化物166a于源/漏极166上。由于本发明仍具有图8的栅极介电层120a的第一部分K1，此第一部分K1的厚度t3足够厚使所形成的金属硅化物166a能限制于第一部分K1的侧边，而不致延伸至第一部分K1的下方。再者，本发明仍具有图8的栅极介电层120a的第二部分K2，此第二部分K2的厚度t4又足够薄，使所形成的金属硅化物166a能形成于第二部分K2的位置。
随后，形成金属硅化物166a于源/漏极166上之后，移除第一外层间隙壁154b，但保留第一内层间隙壁152b，如图10所示。在本实施例中，移除第二区B的第一外层间隙壁154b的同时，一并移除第一区A的第一外层间隙壁154a，但保留第一区A的第一内层间隙壁152a，并形成一栅极介电层120b。
在移除第二区B的第一外层间隙壁154b以及第一区A的第一外层间隙壁154a的同时，可移除第一栅极电极E1中的牺牲电极层124a以及盖层130a，以及第二栅极电极E2中的牺牲电极层124b以及盖层130b，并分别再填入第一金属栅极M1及第二金属栅极M2，以将第一栅极电极E1置换为第一金属栅极M1及第二栅极电极E2置换为第二金属栅极M2，其中金属栅极置换制作工艺为本领域所熟知，故不再赘述。之后，可形成一接触洞蚀刻停止层170全面覆盖并直接接触第一内层间隙壁152a/152b。
再者，如图10所示，突出自第二金属栅极M2的栅极介电层120b至少可包含一第三部分K3以及一第四部分K4，其中第三部分K3位于第一内层间隙壁152b正下方，而第一内层间隙壁152b未覆盖第四部分K4。由于第四部分K4在移除第二区B的第二外层间隙壁164b时被薄化，因而第三部分K3的一厚度t5大于第四部分K4的一厚度t6。如此一来，第四部分则会位于源/漏极166以及第一内层间隙壁152b之间。换言之，本发明可通过形成间隙壁142b、第一双层间隙壁150b及第二双层间隙壁160b而调整源/漏极166至第二金属栅极M2的距离。
综上所述，本发明提出一种具有双层间隙壁的晶体管及其形成方法，其形成第二双层间隙壁于第二栅极侧边，以调整源/漏极至栅极的距离，以能防止源/漏极至栅极之间所产生的高电场，而达到提升元件的所需电性需求的目的。并且，通过将第二双层间隙壁的内层间隙壁设置为具有L型剖面结构，可进一步避免例如源/漏极或金属硅化物等扩充至太靠近第二栅极(或第二金属栅极)。再者，本发明的全面覆盖基底的栅极介电层，可经由在多次对于多层间隙壁蚀刻中形成多个局部厚度，以能形成金属硅化物又能限制源/漏极或金属硅化物的形成范围。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的保护范围。

Claims (26)

1.一种具有双层间隙壁的晶体管，包含有：
栅极，设置于一基底上，其中该栅极包含栅极介电层以及栅极电极，以及该栅极介电层自该栅极电极突出并覆盖该基底；
第一双层间隙壁，设置于该栅极侧边的该栅极介电层上，其中该第一双层间隙壁包含第一内层间隙壁以及第一外层间隙壁；
第二内层间隙壁，设置于该第一双层间隙壁侧边的该栅极介电层上，其中该第二内层间隙壁具有一L型剖面结构。
2.如权利要求1所述的具有双层间隙壁的晶体管，其中该基底具有凹槽，且该栅极介电层设置于该凹槽中。
3.如权利要求1所述的具有双层间隙壁的晶体管，其中突出自该栅极电极的该栅极介电层包含第一部分以及第二部分，其中该第一部分位于该第二内层间隙壁正下方，而该第二内层间隙壁未覆盖该第二部分。
4.如权利要求3所述的具有双层间隙壁的晶体管，其中该第一部分的一厚度大该第二部分的一厚度。
5.如权利要求1所述的具有双层间隙壁的晶体管，还包含：
源/漏极，设置于该第二内层间隙壁侧边的该基底中。
6.如权利要求1所述的具有双层间隙壁的晶体管，还包含：
间隙壁，设置于该栅极以及该第一双层间隙壁之间的该基底上；以及
轻掺杂源/漏极，设置于该间隙壁侧边的该基底中。
7.如权利要求1所述的具有双层间隙壁的晶体管，还包含：
第一栅极，设置于该基底上，其中该栅极为一中电压晶体管的一栅极，而该第一栅极为一低电压晶体管的一栅极，且具有该L型剖面结构该第二内层间隙壁仅设置于该栅极侧边的该基底上。
8.一种具有双层间隙壁的晶体管，包含有：
栅极介电层，设置于一基底上；
栅极电极，设置于该栅极介电层上；
间隙壁，设置于该栅极电极侧边的该栅极介电层上；以及
第一双层间隙壁，设置于该间隙壁侧边的该栅极介电层上，其中该第一双层间隙壁包含第一内层间隙壁，具有一L型剖面结构。
9.如权利要求8所述的具有双层间隙壁的晶体管，其中该基底具有凹槽，且该栅极介电层设置于该凹槽中。
10.如权利要求8所述的具有双层间隙壁的晶体管，其中该栅极介电层突出自该栅极电极，且该栅极介电层包含第三部分以及第四部分，其中该第三部分位于该第一内层间隙壁正下方，而该第一内层间隙壁未覆盖该第四部分。
11.如权利要求10所述的具有双层间隙壁的晶体管，其中该第三部分的一厚度大该第四部分的一厚度。
12.如权利要求11所述的具有双层间隙壁的晶体管，还包含：
源/漏极，设置于该第一内层间隙壁侧边的该基底中，其中该第四部分位于该源/漏极以及该第一内层间隙壁之间。
13.如权利要求8所述的具有双层间隙壁的晶体管，还包含：
轻掺杂源/漏极，设置于该间隙壁侧边的该基底中。
14.一种形成具有双层间隙壁的晶体管的方法，包含有：
形成一栅极介电层以及一栅极电极于一基底上；
形成一第一双层间隙壁于该栅极电极侧边的该栅极介电层上，其中该第一双层间隙壁包含第一内层间隙壁以及第一外层间隙壁；
形成一第二双层间隙壁于该第一双层间隙壁侧边的该栅极介电层上，其中该第二双层间隙壁包含第二内层间隙壁以及第二外层间隙壁，且该第二内层间隙壁具有一L型剖面结构；以及
移除该第二外层间隙壁。
15.如权利要求14所述的形成具有双层间隙壁的晶体管的方法，在移除该第二外层间隙壁之后，还包含：
形成一接触洞蚀刻停止层。
16.如权利要求14所述的形成具有双层间隙壁的晶体管的方法，在形成该栅极介电层以及该栅极电极于该基底上之前，还包含：
形成一凹槽于该基底中；以及
形成该栅极介电层于该凹槽中。
17.如权利要求14所述的形成具有双层间隙壁的晶体管的方法，其中该栅极介电层突出自该栅极电极，且该栅极介电层包含第一部分以及第二部分，其中该第一部分位于该第二内层间隙壁正下方，而该第二内层间隙壁未覆盖该第二部分。
18.如权利要求17所述的形成具有双层间隙壁的晶体管的方法，其中该第一部分的一厚度大该第二部分的一厚度。
19.如权利要求14所述的形成具有双层间隙壁的晶体管的方法，其中形成该第二双层间隙壁的方法包含：
形成一第二内层间隙壁材料以及一第二外层间隙壁材料，全面覆盖该栅极介电层、该栅极电极以及该基底；以及
蚀刻该第二外层间隙壁材料以及该第二内层间隙壁材料，因而形成该第二双层间隙壁。
20.如权利要求19所述的形成具有双层间隙壁的晶体管的方法，其中形成该第二内层间隙壁材料以及该第二外层间隙壁材料的方法包含以应力记忆技术形成该第二内层间隙壁材料以及该第二外层间隙壁材料。
21.如权利要求19所述的形成具有双层间隙壁的晶体管的方法，其中蚀刻该第二外层间隙壁材料以及该第二内层间隙壁材料时，同时蚀刻自该栅极电极突出的该栅极介电层的一部分。
22.如权利要求14所述的形成具有双层间隙壁的晶体管的方法，在形成该第二双层间隙壁之后，还包含：
形成一源/漏极于该第二双层间隙壁侧边的该基底中，之后才移除该第二外层间隙壁。
23.如权利要求22所述的形成具有双层间隙壁的晶体管的方法，在移除该第二外层间隙壁之后，还包含：
形成一金属硅化物于该源/漏极上。
24.如权利要求23所述的形成具有双层间隙壁的晶体管的方法，其中该第一内层间隙壁具有一L型剖面结构，且在形成该金属硅化物于该源/漏极上之后，移除该第一外层间隙壁。
25.如权利要求14所述的形成具有双层间隙壁的晶体管的方法，在形成该第一双层间隙壁之前，还包含：
形成一间隙壁于该栅极侧边的该基底上；以及
形成一轻掺杂源/漏极于该间隙壁侧边的该基底中。
26.如权利要求14所述的形成具有双层间隙壁的晶体管的方法，还包含：
在形成一栅极包含该栅极介电层以及该栅极电极时，同时形成一第一栅极于该基底上，其中该栅极为一中电压晶体管的一栅极，而该第一栅极为一低电压晶体管的一栅极，且该第二双层间隙壁仅形成于该栅极侧边的该基底上，而没有形成于该第一栅极侧边的该基底上。
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