CN1097304C - 半导体器件的制造方法 - Google Patents

半导体器件的制造方法 Download PDF

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CN1097304C
CN1097304C CN97117010A CN97117010A CN1097304C CN 1097304 C CN1097304 C CN 1097304C CN 97117010 A CN97117010 A CN 97117010A CN 97117010 A CN97117010 A CN 97117010A CN 1097304 C CN1097304 C CN 1097304C
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孙正焕
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Abstract

一种半导体器件的制造方法，该方法包括以下步骤：在半导体衬底上形成栅绝缘膜；在栅绝缘膜上形成栅极；在栅极上形成栅帽盖；在衬底中栅极外部形成重掺杂区；在包括栅帽盖的栅极侧面上形成第一侧壁；向下刻蚀栅极绝缘膜外的衬底至具有最高杂质浓度的那部分；及在衬底中围绕重掺杂区形成轻掺杂区。该方法可以防止热载流子注入到栅氧化膜中或侧壁中，并可减少结电流泄漏和短沟道效应的发生。

Description

半导体器件的制造方法
本发明涉及一种半导体器件，特别涉及一种MOSFET器件的制造方法，用于防止由于热载流子导致的器件特性退化，并减少结漏电。
参见图1，该图示出了制造MOSFET器件的常规方法，在半导体衬底11上依次形成栅氧化膜12、栅极13、和氮化物帽盖14。在衬底11通过离子注入中形成轻掺杂区17，并在栅极13和氮化物帽盖14侧面上形成氮化物侧壁15。通过第二次离子注入，在衬底11中形成重掺杂区16。氮化物帽盖14和氮化物侧壁15可以由氧化物形成。
轻掺杂区17减弱了电场，因而热载流子产生速率减慢。然而，衬底表面上产生的热载流子注入到栅氧化膜12中或侧壁15中，导致了半导体器件的特性退化。
另外，在刻蚀形成侧壁15时，场氧化区边缘处会发生结损坏，这样，重掺杂区16中的电流泄漏增加，从而增加了重掺杂区16激活期间轻掺杂区17的扩散。
因此，本发明的目的在于提供一种半导体器件制造方法，用于使重掺杂区远离衬底表面，由此防止热载流子注入到栅氧化膜中或侧壁中，并减少结漏电流的产生和短沟道效应。
为了实现上述目的，按照本发明的一个方面，提供了一种半导体器件制造方法，该方法包括以下步骤：在半导体衬底上形成栅绝缘膜；在栅绝缘膜上形成栅极；在栅极上形成栅帽盖；在栅极每侧下形成远离衬底表面的重掺杂区；在栅帽盖和栅极侧面上形成第一侧壁；刻蚀栅绝缘膜和衬底，其中衬底向下刻至重掺杂区；以及围绕每一重掺杂区形成一轻掺杂区。
按照本发明的另一个方面，提供了一种半导体器件制造方法，该方法包括以下步骤：在半导体衬底上形成栅绝缘膜；在栅绝缘膜上形成栅极；在栅极上形成栅帽盖；在栅极每侧下形成远离衬底表面的重掺杂区；刻蚀栅绝缘膜和衬底，其中衬底向下刻至重掺杂区；在栅帽盖、栅极、栅绝缘膜和刻蚀的衬底侧面上形成侧壁；及围绕每一重掺杂区形成一轻掺杂区。
图1是常规半导体器件的剖面图；
图2A-2D是展示根据本发明第一实施例的半导体器件制造方法的剖面图；及
图3A-3D是展示根据本发明第二实施例的半导体器件制造方法的剖面图。
结合下面附图详细说明根据本发明优选实施例的半导体器件制造方法。
首先，如图2A所示，用局部氧化法在半导体衬底21上形成用于构成隔离结构的场氧化区22。在衬底21上形成厚约20-100埃的栅氧化膜23。在栅氧化膜23上形成厚约1000-3000埃用作栅极的掺杂多晶硅层24。在多晶硅24上用CVD法(化学汽相淀积)淀积厚约500-2000埃用作栅帽盖的氧化膜25。
参见图2B，构图和刻蚀氧化膜25和多晶硅膜24，从而暴露栅氧化膜23，由此形成由氧化膜构成的栅帽盖25和由多晶硅构成的栅极24。
利用栅帽盖作掩模，对衬底21进行离子注入，由此在衬底21中且栅极24每侧之下形成重掺杂区26，其中向衬底中注入砷离子的条件为50-200Kev、剂量2E15-5E15cm-2、及倾斜0-10度。即，在上述条件下注入离子化砷后，在衬底21中形成n+重掺杂区26，该区远离衬底11表面。
如图2C所示，在栅极24和栅帽盖25侧面上形成厚约500-2000埃的氮化物膜，此膜然后被刻蚀形成第一氮化物侧壁27。此后，用第一氮化物侧壁27和栅帽盖25作掩模，刻蚀栅氧化膜23和衬底21，至重掺杂区26中具有最高浓度的部分，其中衬底21被向下刻蚀至重掺杂区26中浓度最高的部分。接着，向衬底21中注入As或P离子，从而形成n-轻掺杂区28，该区围绕重掺杂区26，其中As离子注入最好在50-200Kev、剂量2E15-5E15cm-2、和倾斜0-10度的条件下进行，P离子注入最好在30-100Kev、剂量1E14-5E14cm-2、和倾斜0-10度的条件下进行。
如图2D所示，在图2A至2C的顺序步骤后，还要进行以下制造步骤：在第一侧壁27上和刻蚀的栅氧化膜23每侧面上及刻蚀的衬底21每侧面上形成第二侧壁29；去掉栅帽盖25；及在栅极24上和其中具有重掺杂区26的衬底暴露表面上形成硅化物膜30。通过淀积厚约500-2000埃的氮化物并选择地刻蚀，形成第二侧壁29。在淀积如Ti和Co等金属后，通过快速热退火(RTA)形成硅化物膜30。这里，在形成硅化层30时，为了获得选择性，要去掉栅帽盖25。因此，只在栅极24和暴露的衬底上选择地形成了硅化层30。
作为参考，可以用离子化BF2代替形成重掺杂区26时使用的离子化As，离子化的BF2和离子化B可以由形成轻掺杂区28时使用的离子化As或离子化P代替。栅帽盖25可以由氮化物膜构成，代替氧化膜，而第一和第二侧壁27和29可以由氧化膜构成，代替氮化物膜。
根据本发明第一实施例的半导体器件制造方法，因为衬底21中重掺杂区26远离衬底21表面，所以载流子从栅极24边缘向衬底21的方向移动。因此，产生于远离衬底21表面部位的热载流向栅氧化膜23和侧壁27、29的注入最小化。
图3A-3D是展示根据本发明第二实施例的半导体器件制造方法的剖面图。
如图3A所示，在半导体衬底41中和上，用局部氧化法形成构成隔离结构的场氧化区42。在衬底41上形成厚约40-100埃的栅氧化膜43。在栅氧化膜43上形成厚约1000-3000埃用作栅极的掺杂多晶硅层44。用CVD(化学汽相淀)法，在多晶硅层44上淀积厚约500-2000埃用作栅帽盖的氧化膜45。
参见图3B，构图并刻蚀氧化膜45和多晶硅层44，从而可以暴露栅氧化膜43，并由此形成由氧化膜构成的栅帽盖和由多晶硅构成的栅极44。
利用栅帽盖45作掩模，对衬底41进行离子注入，由此在衬底41中栅极44每侧之下形成重掺杂区46，其中向衬底41注入As离子最好在50-200Kev、剂量2E15-5E15cm-2、和倾斜0-10度的条件下进行，即，在上述条件下注入离子化As后，在衬底41中远离衬底41表面形成了深重掺杂n+杂质区46。
如图3C所示，从栅氧化物膜43到场氧化区42向下刻蚀衬底41，至重掺杂区46中具有最高杂质浓度的部分。在所得结构的整个暴露表面上形成厚500-2000埃的氮化物膜，选择性刻蚀该氮化物膜，分别在栅帽盖45、栅极44、栅氧化膜43的侧面上，及在衬底中41中的内壁上形成氧化物侧壁47。接着，向衬底41注入As离子或P离子，从而形成n-轻掺杂区48，由此包围重掺杂区46，其中As离子注入最好在50-200Kev、剂量1E14-5E15cm-2、和倾斜0-10度的条件下进行，P离子注入最好在30-100Kev、剂量1E14-5E14cm-2、和倾斜0-10度的条件下进行。
如图3D所示，在图3A至3C的顺序步骤后，还要进行以下制造步骤：去掉栅帽盖45；并在衬底41的刻蚀部分中形成硅化物膜49。利用RTA法形成由如Ti和Co等金属构成的硅化物膜49。这里，为了在形成硅化物膜期间获得选择性，要去掉栅帽盖45，硅化物膜只在栅极44和其下具有重掺杂区46的衬底41上形成。
这里，可以用BF2离子代替形成重掺杂区46时使用的As离子，离子化的BF2和离子化B可以由形成轻掺杂区28时使用的离子化As或离子化P代替。栅帽盖45用氮化物膜代替氧化膜，侧壁47和29可以由氧化膜构成，代替氮化物膜。
根据本发明第二实施例的半导体器件制造方法将形成如图2D所示的第一和第二侧壁的各步骤减少到如图3C所示的一个步骤。
如上所述，本发明的半导体器件方法可以防止由热载流子导致的器件特性退化，并且，因为轻掺杂区足以包围重掺杂区，所以发生在场氧化区边缘的重掺杂区电流泄漏可以减至最小。
而且，因为重掺杂区在轻掺杂区之前形成，所以可以防止激活重掺杂区期间轻掺杂区扩散，由此减少短沟道效应。

Claims (24)

1.一种半导体器件制造方法，该方法包括以下步骤：
在半导体衬底上形成栅绝缘膜；
在栅绝缘膜上形成栅极；
在栅极上形成栅帽盖；
在栅极每侧下形成远离衬底表面的重掺杂区；
在栅帽盖和栅极侧面上形成第一侧壁；
刻蚀栅绝缘膜和衬底，其中衬底向下刻至重掺杂区；以及
围绕每一重掺杂区形成一轻掺杂区。
2.如权利要求1的方法，还包括以下步骤：
在第一侧壁上及刻蚀的栅绝缘膜和刻蚀的衬底每一侧面上形成第二侧壁；
去掉栅帽盖；及
在栅极和衬底上形成硅化物层。
3.如权利要求2的方法，其特征在于，第一侧壁和第二侧壁由氧化物和氮化物中一种形成。
4.如权利要求2的方法，其特征在于，重掺杂区的杂质浓度大于轻掺杂区的杂质浓度。
5.如权利要求2的方法，其特征在于，离子注入N型杂质和P型杂质中的一种形成重掺杂区和轻掺杂区。
6.如权利要求2的方法，其特征在于，通过在50-200Kev、剂量2E15-5E15cm-2、和倾斜0-10度的条件下离子注入As离子或离子化BF2形成重掺杂区。
7.如权利要求2的方法，其特征在于，通过在30-100Kev、剂量1E14-5E14cm-2、和倾斜0-10度的条件下离子注入P离子形成轻掺杂区。
8.如权利要求2的方法，其特征在于，通过在50-100Kev、剂量1E14-5E15cm-2、和倾斜0-10度的条件下离子注入As离子、离子化BF2或B离子形成轻掺杂区。
9.如权利要求1的方法，其特征在于，栅极由厚1000-3000埃的多晶硅形成。
10.如权利要求1的方法，其特征在于，栅绝缘膜由厚40-100埃的氧化膜构成。
11.如权利要求1的方法，其特征在于，栅帽盖由厚500-2000埃的氧化膜和氮化物膜中的一种构成。
12.如权利要求1的方法，其特征在于，在每个重掺杂区，衬底向下刻蚀至浓度最高的部分。
13.一种半导体器件制造方法，该方法包括以下步骤：
在半导体衬底上形成栅绝缘膜；
在栅绝缘膜上形成栅极；
在栅极上形成栅帽盖；
在栅极每侧下形成远离衬底表面的重掺杂区；
刻蚀栅绝缘膜和衬底，其中衬底向下刻至重掺杂区；
在栅帽盖、栅极、栅绝缘膜和刻蚀的衬底侧面上形成侧壁；及
围绕每一重掺杂区形成一轻掺杂区。
14.如权利要求13的方法，还包括以下步骤：
去掉栅帽盖；及
在栅极和衬底上形成硅化物层。
15.如权利要求14的方法，其特征在于，重掺杂区的杂质浓度大于轻掺杂区的杂质浓度。
16.如权利要求14的方法，其特征在于，重掺杂区和轻掺杂区由N型杂质和P型杂质中的一种形成。
17.如权利要求14的方法，其特征在于，通过在50-200Kev、剂量2E15-5E15cm-2、和倾斜0-10度的条件下离子注入As离子或离子化BF2形成重掺杂区。
18.如权利要求14的方法，其特征在于，通过在30-100Kev、剂量1E14-5E14cm-2、和倾斜0-10度的条件下离子注入P离子形成轻掺杂区。
19.如权利要求14的方法，其特征在于，通过在50-100Kev、剂量1E14-5E15cm-2、和倾斜0-10度的条件下离子注入As离子、离子化BF2或B离子形成轻掺杂区。
20.如权利要求13的方法，其特征在于，侧壁由氧化物和氮化物中一种形成。
21.如权利要求13的方法，其特征在于，栅绝缘膜由厚40-100埃的氧化膜构成。
22.如权利要求13的方法，其特征在于，栅极由厚1000-3000埃的多晶硅形成。
23.如权利要求13的方法，其特征在于，栅帽盖由厚500-2000埃的氧化膜和氮化物膜中的一种形成。
24.如权利要求13的方法，其特征在于，在每个重掺杂区，衬底向下刻蚀至浓度最高的部分。
CN97117010A 1996-11-27 1997-09-23 半导体器件的制造方法 Expired - Fee Related CN1097304C (zh)

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