CN109690765B - 半导体装置 - Google Patents

半导体装置 Download PDF

Info

Publication number
CN109690765B
CN109690765B CN201780055573.6A CN201780055573A CN109690765B CN 109690765 B CN109690765 B CN 109690765B CN 201780055573 A CN201780055573 A CN 201780055573A CN 109690765 B CN109690765 B CN 109690765B
Authority
CN
China
Prior art keywords
layer
semiconductor element
support
semiconductor device
metallization layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201780055573.6A
Other languages
English (en)
Other versions
CN109690765A (zh
Inventor
岩重朝仁
杉浦和彦
三轮和弘
佐久间裕一
黑坂成吾
小田幸典
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
C Uyemura and Co Ltd
Original Assignee
Denso Corp
C Uyemura and Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp, C Uyemura and Co Ltd filed Critical Denso Corp
Priority claimed from PCT/JP2017/032333 external-priority patent/WO2018047913A1/ja
Publication of CN109690765A publication Critical patent/CN109690765A/zh
Application granted granted Critical
Publication of CN109690765B publication Critical patent/CN109690765B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142Sealing arrangements between parts, e.g. adhesion promotors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334Auxiliary members in encapsulations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492Bases or plates or solder therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29139Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331Disposition
    • H01L2224/3318Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181On opposite sides of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399Material
    • H01L2224/834Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83439Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8384Sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49579Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582Metallic layers on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1027IV
    • H01L2924/10272Silicon Carbide [SiC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/157Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/183Connection portion, e.g. seal
    • H01L2924/18301Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Abstract

半导体装置(1)具备:半导体元件(2);支承体(3),是在最表面(35)具有金属化层(34)的金属部件,且配置为所述最表面与所述半导体元件相对置,所述金属化层(34)含有铁族元素即第一成分和铬以外的周期表第5族或第6族过渡金属元素即第二成分;接合件(4),配置在所述支承体的所述最表面与所述半导体元件之间,并设置为通过与所述最表面接合而将所述半导体元件固定于所述支承体;模塑树脂(6),设置为将所述支承体和所述接合件和所述半导体元件的接合体(S)覆盖。

Description

半导体装置
关联申请的相互参照
本申请基于2016年9月12日申请的日本专利申请第2016-177873号、以及2017年9月7日申请的日本专利申请第2017-172030号,在此参照引用它们的记载内容。
技术领域
本发明涉及具备半导体元件的半导体装置。
背景技术
已知有一种半导体装置,其通过将半导体元件和对其进行支承的支承体(例如支承基板、散热板、热沉等)进行树脂模塑而形成。关于这种半导体装置,日本特开2003-124406号公报提出了在半导体元件及热沉的表面配置聚酰胺树脂层的结构。根据该结构,半导体元件及热沉与模塑树脂之间的粘接力提高。因此,根据该结构,即使在高温下也能够抑制半导体元件及热沉与模塑树脂发生剥离。
发明内容
关于这种半导体装置,要求兼顾相对于支承体将半导体元件进行固定的贴片(dieattach)部的耐热可靠性和树脂模塑部的耐热可靠性。
根据本发明的一个方面,半导体装置具备:半导体元件;支承体,在最表面具有金属化层,配置为所述最表面与所述半导体元件相对置,所述金属化层含有铁族元素即第一成分和铬以外的周期表第5族或第6族过渡金属元素即第二成分;接合件,配置在所述支承体的所述最表面与所述半导体元件之间,并设置为通过与所述最表面接合而将所述半导体元件固定于所述支承体;模塑树脂,设置为将所述支承体与所述接合件与所述半导体元件的接合体覆盖。
在上述结构中,构成所述支承体的所述最表面的所述金属化层,与所述接合件(例如含银的烧结体层)接合,并且被所述模塑树脂覆盖。本申请的发明人经过深入研究发现:通过使所述金属化层含有铁族元素即所述第一成分、以及铬以外的周期表第5族或第6族过渡金属元素即所述第二成分,能够良好地确保夹着所述接合件的所述半导体元件与所述支承体的接合部即贴片部的耐热可靠性、以及利用所述模塑树脂将所述支承体覆盖的部分即树脂模塑部的耐热可靠性。
此外,权利要求所记载的各部分的括弧内的符号用于表示该部分与后述的实施方式所记载的具体部分的对应关系的一例。
附图说明
图1是表示实施方式的半导体装置的概略结构的侧剖视图。
图2A是表示实施例及比较例的树脂模塑部的粘接强度评价用的测试件的结构的侧剖视图。
图2B是表示实施例及比较例的贴片部的接合强度评价用的测试件的结构的侧剖视图。
图3是表示实施例及比较例的评价结果的图表。
图4是表示实施例及比较例的评价结果的表。
图5是表示变形例的半导体装置的概略结构的侧剖视图。
具体实施方式
以下参照附图对实施方式进行说明。此外,在以下的说明中,对于在实施方式与后述变形例之间彼此相同或等价的部分标记相同符号,只要没有技术上的矛盾,则能够将在先实施方式的说明适当地用于后述变形例。
(结构)
参照图1,半导体装置1具备半导体元件2、支承体3、接合件4、底层5、模塑树脂6。
半导体元件2是适于高温工作的SiC器件,形成为薄板状。以下,为了简化说明,将图1中的上方简称为“上方”,将图1中的下方简称为“下方”。即,图1中的上下方向与薄板状的半导体元件2的厚度方向平行。半导体元件2的一个主面即上表面21和另一个主面即下表面22设置为彼此平行。
支承体3是作为散热板发挥功能的板状的金属部件,与半导体元件2的下表面22相对置地配置。支承体3的主体部31由铜制的板材形成。主体部31的一个主面即外表面32(即图中下侧的表面)设置为露出到模塑树脂6的外部,以便能与未图示的热沉接合。
主体部31的另一个主面即内表面33被金属化层34覆盖。在本实施方式中,金属化层34是构成支承体3的最表面35的镀层,最表面35与半导体元件2相对置。
本实施方式中的金属化层34由含有第一成分和第二成分的金属薄膜形成,该第一成分是铁族元素(即铁、钴或镍),该第二成分是铬以外的周期表第5族或第6族过渡金属元素(即钼、钨、钒、铌或钽)。具体而言,在本实施方式中,金属化层34具有与支承体3的内表面33密接的作为基底层的镍镀层、以及在该镍镀层之上形成的合金镀层。构成支承体3的最表面35的上述合金镀层含有上述第一成分和第二成分。
接合件4设置为,配置在支承体3的最表面35与半导体元件2之间,通过与最表面35接合而将半导体元件2固定于支承体3。在本实施方式中,接合件4是含银的烧结体层,通过对银膏进行热处理而形成。
底层5是为了使支承体3与模塑树脂6的粘接性提高而设置的合成树脂层,配置在支承体3的最表面35与模塑树脂6之间。即,底层5与支承体3的最表面35中的与接合件4接合的部位以外的部分粘接。在本实施方式中,底层5由含有酰亚胺基的芳香族类聚合物(例如聚酰亚胺、聚酰胺酰亚胺等)形成。模塑树脂6是含有环氧类树脂和/或马来酰亚胺类树脂的封固树脂,设置为从半导体元件2侧将支承体3与接合件4与半导体元件2的接合体S覆盖。
(效果)
在上述结构中,构成支承体3的最表面35的金属化层34与接合件4直接接合,并且隔着底层5而被模塑树脂6覆盖。在以下的说明中,将夹着接合件4的半导体元件2与支承体3的接合部称为“贴片部”。并且,将利用模塑树脂6将接合体S覆盖的结构中的、支承体3与模塑树脂6相对置的部分(即利用模塑树脂6将支承体3覆盖的部分)称为“树脂模塑部”。
如上所述,作为半导体元件2,近年广泛采用了适合高温工作的半导体器件(例如SiC器件等)。该半导体器件例如适于用作在混合动力车用功率控制单元等的功率模块中搭载的功率半导体器件。关于搭载有该半导体器件的模块(即功率模块等),要求安装结构的高耐热性。因此,需要兼顾贴片部的耐热可靠性和树脂模塑部的耐热可靠性。
从贴片部的耐热可靠性的观点出发,适合采用银膏烧结体作为接合件4。但是,银膏烧结体与Ni金属化层及Au金属化层(例如镍镀层、NiAu镀层等)的接合性不佳。因此,优选的是,支承体3的最表面35由银金属化层(例如NiAg镀层等)形成。另一方面,银金属化层与构成底层5的合成树脂、以及构成模塑树脂6的合成树脂的粘接性(尤其是高温下的粘接强度)不佳。相对于此,Ni金属化层及Au金属化层与这些合成树脂的粘接性良好。
本申请的发明人对能够确保贴片部的耐热可靠性以及树脂模塑部(即支承体3的最表面35与底层5之间的粘接部)的耐热可靠性的金属化层34的结构进行了仔细研究。结果发现使金属化层34的至少构成最表面35的部分含有铁族元素即第一成分、以及铬以外的周期表第5族或第6族过渡金属元素即第二成分的结构是有效的。以下,与比较例的评价结果进行对比来说明实施例的评价结果。
本申请的发明人利用图2A所示的测试件70,利用剪切试验机测定剪切强度,从而对树脂模塑部的粘接强度进行了评价。如图2A所示,树脂模塑部的粘接强度评价用的测试件70包括支承台71、金属化层72、底层73和块部74。支承台71相当于图1所示的半导体装置1中的支承体3的主体部31,由铜板形成。金属化层72是相当于图1所示的半导体装置1中的金属化层34的、实施例或比较例的金属化层,形成在支承台71上。底层73相当于图1所示的半导体装置1中的底层5,形成在金属化层72上。即,底层73是聚酰亚胺膜,与金属化层72直接接合。块部74相当于图1所示的半导体装置1中的树脂模塑6,固定在底层73上。
另外,本申请的发明人利用图2B所示的测试件80,以与上述同样的方法,对贴片部的接合强度进行了评价。如图2B所示,贴片部的接合强度评价用的测试件80包括支承台81、基材侧金属化层82、接合件层83、块部84、块部侧金属化层85。支承台81与图2A所示的测试件70中的支承台71是同样的,由铜板形成。基材侧金属化层82与图2A所示的测试件70中的金属化层72是同样的。即,基材侧金属化层82是相当于图1所示的半导体装置1中的金属化层34的、实施例或比较例的金属化层。接合件层83是与图1所示的半导体装置1中的接合件4对应的银膏烧结体。块部84是模拟图1中的半导体元件2的铜制块部。在块部84的下表面即接合件层83侧的面,形成有块部侧金属化层85,该块部侧金属化层85是与设在支承台81上的基材侧金属化层82同样的金属化层。即,块部84隔着块部侧金属化层85以及接合件层83,与形成在支承台81上的基材侧金属化层82接合。
图3中,柱状图表示在接合初期和热耐久后(即在250℃下放置500小时后)对常温下的贴片部的接合强度进行测定的结果。另外,纵线图表示对高温下(即225℃)的树脂模塑部的粘接强度进行测定的结果。
在图3中,NiP/CoWP表示实施例的金属化层即NiP/CoWP镀层(即在基底的非电解镍镀层之上形成有非电解CoW合金镀层的结构)的评价结果。NiP/Au表示比较例的金属化层即NiP/Au镀层(即在基底的非电解镍镀层之上形成有金镀层的结构)的评价结果。NiP/Ag表示比较例的金属化层即NiP/Ag镀层(即在基底的非电解镍镀层之上形成有银镀层的结构)的评价结果。
由图3的评价结果可知,比较例的金属化层即NiP/Au镀层的情况下,高温下的树脂模塑部的粘接强度良好。但是,在热耐久后贴片部的接合强度大幅降低。即,比较例的金属化层即NiP/Au镀层的情况下,贴片部的耐热可靠性不足。另一方面,比较例的金属化层即NiP/Ag镀层的情况下,贴片部的耐热可靠性良好。但是,高温下的树脂模塑部的粘接强度不足。相对于此,根据实施例的金属化层即NiP/CoWP镀层,高温下的树脂模塑部的粘接强度、以及贴片部的耐热可靠性均为良好。
在图4中,比较例1的金属化层是NiP镀层(即非电解镍镀层)。比较例2的金属化层是上述的NiP/Au镀层。比较例3的金属化层是NiP/PdP/Ag镀层(即在基底的非电解镍镀层之上形成有非电解钯镀层及金镀层的结构)。实施例1的金属化层是上述的NiP/CoWP镀层。实施例2的金属化层是NiP/NiWP镀层(即在基底的非电解镍镀层之上形成有非电解NiW合金镀层的结构)。实施例3的金属化层是Ni/CoW层。实施例4的金属化层是Ni/NiW层。
在图4所示的贴片部的耐热可靠性的评价结果中,将通过下式算出的“剪切强度比”为0.7以上的情况设为OK,将0.5以下的情况设为NG。
剪切强度比=(热耐久后的剪切强度)/(接合初期的剪切强度)
图4所示的树脂粘接强度(即高温下的树脂模塑部的粘接强度)的评价结果中,使用了下述的评价指标。
·OK:225℃的剪切强度为15MPa以上的情况
·NG:225℃的剪切强度为10MPa以下、或225℃的剪切破坏模式为中间层72与接合层73的粘接界面处的剥离的情况
由图4的评价结果可知,关于比较例1和比较例2的金属化层,高温下的树脂模塑部的粘接强度良好。但是,贴片部的耐热可靠性不足。另一方面,关于比较例3的金属化层,贴片部的耐热可靠性良好。但是,高温下的树脂模塑部的粘接强度不足。相对于此,关于实施例1~实施例4的金属化层,高温下的树脂模塑部的粘接强度、以及贴片部的耐热可靠性均为良好。
此外,在上述的各实施例中,作为第二成分,都采用了钨。另外,包含钨的周期表第6族过渡金属元素和铌等周期表第5族过渡金属元素是族编号相邻的过渡金属元素,单质金属中的晶格结构相同。因此,从环保的观点来看,通过将除了铬以外的可天然产出的周期表第5族或第6族过渡金属元素用作第二成分,能够期待与上述实施例同样的效果。
尤其是,钨、钼、铌以及钽彼此的晶格常数接近,彼此完全固溶、都构成酸性氧化物等化学性质近似。因此,通过将周期表第5族~第6族过渡金属元素中的第5~第6周期的元素用作第二成分,能够获得上述那样的良好效果。此外,能够与非电解铜镀液所含的铜进行置换镀且对铜具有阻隔性的钨或铌是优选的。钨和铌的内聚能大,因此认为能够通过添加来提高耐热性。
(变形例)
本发明并不限定于上述实施方式,能够对上述实施方式适当地进行变更。以下对代表性的变形例进行说明。在以下的变形例的说明中,仅针对与上述实施方式不同的部分进行说明。
本发明并不限定于在上述实施方式中示出的具体的装置结构。例如可以省略底层5。即,依次层叠了半导体元件2、接合件4和支承体3而成的接合体S可以不经由底层5而被模塑树脂6直接封固。
金属化层34并不限定于上述具体例那样的二层结构。即,例如,金属化层34也可以是三层以上的多层结构。或者,如果能够获得对铜的良好阻隔性、以及对支承体3的内表面33的良好成膜性,则金属化层34也可以是一层结构。具体而言,例如,上述的具体例中的NiP/CoWP二层镀可以变更为一层的Ni-Co-W-P合金镀。或者,上述的各具体例中的基底镍镀层可以省略。此外,在与上述的实施例1和实施例2对应的组成中,为了非电解镀处理的方便而含有磷,但是本发明并不限定于含磷的组成。即,鉴于不仅是上述的实施例1和实施例2而且在比较例中也含磷、以及实施例3和实施例4为不含磷的组成,可知利用不含磷的组成的(即例如通过电解镀而形成的)金属化层34也能够很好地获得本发明的效果。
金属化层34的形成方法并不限定于镀覆。即,金属化层34也可以通过CVD等气相成膜法良好地形成。CVD是Chemical Vapor Deposition的缩写。
支承体3可以是DBC基板或DBA基板。DBC是Direct Bonded Copper的缩写。DBA是Direct Bonded Aluminum的缩写。或者,支承体3可以是铜板等散热板与DBC基板或DBA基板的接合体。
如图5所示那样,支承体3及接合件4不仅可以安装在半导体元件2的上表面21,而且也可以安装在下表面22。即,支承体3及接合件4可以分别安装在半导体元件2的上表面21和下表面22。
变形例也并不限定于上述的例示。另外,多个变形例可以相互组合。此外,上述实施方式的全部或一部分、以及变形例的全部或一部分可以相互组合。

Claims (5)

1.一种半导体装置(1),其特征在于,
具备:
半导体元件(2);
支承体(3),在最表面(35)具有在作为基底层的非电解镍镀层之上形成有非电解CoW合金镀层而得到的金属化层(34),所述最表面与所述半导体元件相对置地配置;
接合件(4),配置在所述支承体的所述最表面与所述半导体元件之间,是含银的烧结体层,并且设置为,通过与所述最表面接合而将所述半导体元件固定于所述支承体;以及
模塑树脂(6),设置为,将接合体(S)覆盖,所述接合体(S)是所述支承体和所述接合件和所述半导体元件的接合体(S)。
2.根据权利要求1所述的半导体装置,其特征在于,
还具备在所述支承体的所述最表面与所述模塑树脂之间设置的作为合成树脂层的底层(5)。
3.根据权利要求2所述的半导体装置,其特征在于,
所述底层由含有酰亚胺基的芳香族类聚合物形成。
4.根据权利要求1~3的任一项所述的半导体装置,其特征在于,
在所述半导体元件的上表面(21)和下表面(22)分别安装有所述接合件以及所述支承体。
5.根据权利要求1~3的任一项所述的半导体装置,其特征在于,
所述金属化层还含有磷。
CN201780055573.6A 2016-09-12 2017-09-07 半导体装置 Active CN109690765B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2016-177873 2016-09-12
JP2016177873 2016-09-12
PCT/JP2017/032333 WO2018047913A1 (ja) 2016-09-12 2017-09-07 半導体装置

Publications (2)

Publication Number Publication Date
CN109690765A CN109690765A (zh) 2019-04-26
CN109690765B true CN109690765B (zh) 2023-05-09

Family

ID=61695143

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201780055573.6A Active CN109690765B (zh) 2016-09-12 2017-09-07 半导体装置

Country Status (3)

Country Link
US (1) US10763204B2 (zh)
JP (1) JP6852626B2 (zh)
CN (1) CN109690765B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7225723B2 (ja) * 2018-11-16 2023-02-21 株式会社レゾナック 半導体デバイス用樹脂組成物、及びこれを用いた半導体デバイス
JP7180490B2 (ja) 2019-03-26 2022-11-30 株式会社デンソー 半導体装置およびその製造方法
JP2023071017A (ja) 2021-11-10 2023-05-22 上村工業株式会社 銀焼結接合のためのめっき方法、銀焼結接合のためのめっき皮膜、パワーモジュール用基板、半導体素子及び半導体装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04211153A (ja) * 1990-02-26 1992-08-03 Hitachi Ltd 半導体パッケージ及びそれに用いるリードフレーム
CN102804428A (zh) * 2010-03-30 2012-11-28 大日本印刷株式会社 Led用引线框或基板、半导体装置和led用引线框或基板的制造方法
JP2013038309A (ja) * 2011-08-10 2013-02-21 Denso Corp 半導体モジュールおよびそれを備えた半導体装置

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4888449A (en) * 1988-01-04 1989-12-19 Olin Corporation Semiconductor package
JPH01209783A (ja) * 1988-02-17 1989-08-23 Fuji Kiko Denshi Kk セラミックス配線基板及びその製造法
KR920000127A (ko) * 1990-02-26 1992-01-10 미다 가쓰시게 반도체 패키지와 그것을 위한 리드프레임
US6087714A (en) * 1998-04-27 2000-07-11 Matsushita Electric Industrial Co., Ltd. Semiconductor devices having tin-based solder film containing no lead and process for producing the devices
US6143981A (en) * 1998-06-24 2000-11-07 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
US7332375B1 (en) * 1998-06-24 2008-02-19 Amkor Technology, Inc. Method of making an integrated circuit package
US7112474B1 (en) * 1998-06-24 2006-09-26 Amkor Technology, Inc. Method of making an integrated circuit package
US6194777B1 (en) * 1998-06-27 2001-02-27 Texas Instruments Incorporated Leadframes with selective palladium plating
US7042068B2 (en) * 2000-04-27 2006-05-09 Amkor Technology, Inc. Leadframe and semiconductor package made using the leadframe
US20020185716A1 (en) * 2001-05-11 2002-12-12 Abys Joseph Anthony Metal article coated with multilayer finish inhibiting whisker growth
JP3807354B2 (ja) 2001-08-06 2006-08-09 株式会社デンソー 半導体装置
JP3694512B2 (ja) 2003-04-18 2005-09-14 沖電気工業株式会社 半導体装置の製造方法
JP2007220967A (ja) 2006-02-17 2007-08-30 Sumitomo Bakelite Co Ltd 配線構造とその製造方法及び半導体装置
JP2009016520A (ja) 2007-07-04 2009-01-22 Tokyo Electron Ltd 半導体装置の製造方法及び半導体装置の製造装置
US8129229B1 (en) * 2007-11-10 2012-03-06 Utac Thai Limited Method of manufacturing semiconductor package containing flip-chip arrangement
WO2013021647A1 (ja) 2011-08-10 2013-02-14 株式会社デンソー 半導体モジュール、半導体モジュールを備えた半導体装置、および半導体モジュールの製造方法
US9490193B2 (en) * 2011-12-01 2016-11-08 Infineon Technologies Ag Electronic device with multi-layer contact
JP2016085998A (ja) 2013-02-19 2016-05-19 パナソニック株式会社 半導体装置及びその製造方法
US9059185B2 (en) * 2013-07-11 2015-06-16 Texas Instruments Incorporated Copper leadframe finish for copper wire bonding

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04211153A (ja) * 1990-02-26 1992-08-03 Hitachi Ltd 半導体パッケージ及びそれに用いるリードフレーム
CN102804428A (zh) * 2010-03-30 2012-11-28 大日本印刷株式会社 Led用引线框或基板、半导体装置和led用引线框或基板的制造方法
JP2013038309A (ja) * 2011-08-10 2013-02-21 Denso Corp 半導体モジュールおよびそれを備えた半導体装置

Also Published As

Publication number Publication date
JP2018046276A (ja) 2018-03-22
CN109690765A (zh) 2019-04-26
US10763204B2 (en) 2020-09-01
JP6852626B2 (ja) 2021-03-31
US20190198441A1 (en) 2019-06-27

Similar Documents

Publication Publication Date Title
US8593817B2 (en) Power semiconductor module and method for operating a power semiconductor module
CN109690765B (zh) 半导体装置
TWI284375B (en) Semiconductor device and manufacturing method for semiconductor device
US8198139B2 (en) Power device package and method of fabricating the same
TWI641300B (zh) 接合體及功率模組用基板
US8120153B1 (en) High-temperature, wirebondless, injection-molded, ultra-compact hybrid power module
TWI335850B (en) Joints and method for forming the same
US20240088087A1 (en) Electronic device with multi-layer contact and system
CN108475647B (zh) 电力用半导体装置以及制造电力用半导体装置的方法
US20170062305A1 (en) Bonded body, power module substrate, power module and method for producing bonded body
US20140077377A1 (en) Semiconductor device and manufacturing method of semiconductor device
US9738056B2 (en) Systems of bonded substrates and methods for bonding substrates
US11615963B2 (en) Electronic device, electronic module and methods for fabricating the same
JP5370460B2 (ja) 半導体モジュール
US20150179599A1 (en) Die substrate assembly and method
US9558859B2 (en) Multilayer substrate and method for manufacturing the same
WO2018047913A1 (ja) 半導体装置
US6809423B1 (en) Electronic module
US9496228B2 (en) Integrated circuit and method of manufacturing an integrated circuit
JP2018085366A (ja) 半導体装置の製造方法
US11462450B2 (en) Semiconductor device
Fukui et al. An Embedded SiC Module with Using NMPB Interconnection for Chevron Shaped Cu Lead and Electrodes
JP2012142320A (ja) 半導体装置の製造方法
JP2013247158A (ja) セラミックス回路基板
JP2021057518A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant