CN109686737A - 具有电源轨的半导体装置 - Google Patents

具有电源轨的半导体装置 Download PDF

Info

Publication number
CN109686737A
CN109686737A CN201811215341.5A CN201811215341A CN109686737A CN 109686737 A CN109686737 A CN 109686737A CN 201811215341 A CN201811215341 A CN 201811215341A CN 109686737 A CN109686737 A CN 109686737A
Authority
CN
China
Prior art keywords
area
unit area
contact plug
power rail
grid structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201811215341.5A
Other languages
English (en)
Other versions
CN109686737B (zh
Inventor
朴判济
梁在锡
金煐勳
李海王
千宽永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN109686737A publication Critical patent/CN109686737A/zh
Application granted granted Critical
Publication of CN109686737B publication Critical patent/CN109686737B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • H01L2027/11868—Macro-architecture
    • H01L2027/11874—Layout specification, i.e. inner core region
    • H01L2027/11875—Wiring region, routing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • H01L2027/11868—Macro-architecture
    • H01L2027/11874—Layout specification, i.e. inner core region
    • H01L2027/11881—Power supply lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Rectifiers (AREA)

Abstract

本公开提供一种半导体装置。所述半导体装置包括衬底、第一栅极结构、第一接触塞及电源轨。衬底包括在第一方向上延伸的第一单元区及第二单元区以及连接到第一单元区及第二单元区的在第二方向上相对的两端中的每一端的电源轨区。第一栅极结构在第二方向上从第一单元区与第二单元区之间的边界区域延伸到电源轨区。第一接触塞形成在电源轨区上且接触第一栅极结构的上表面。电源轨在电源轨区上在第一方向上延伸且电连接到第一接触塞。电源轨通过第一接触塞对第一栅极结构供应关断信号以将第一单元区与第二单元区电绝缘。本公开的半导体装置的相邻的单元区即使在具有高集成度的条件下，也可彼此有效地绝缘。

Description

具有电源轨的半导体装置
[相关申请的交叉参考]
本申请主张在2017年10月19日在韩国知识产权局(Korean IntellectualProperty Office，KIPO)提出申请的韩国专利申请第10-2017-0135748号的优先权，所述韩国专利申请的内容全文并入本申请供参考。
技术领域
本发明概念大体来说涉及半导体装置，且更具体来说涉及具有电源轨(powerrail)的半导体装置。
背景技术
为使半导体装置的相邻的标准单元电隔离，可将各个标准单元之间边界区域处的栅极结构移除。在此过程期间，对与栅极结构相邻的源极/漏极层施加的应力可减弱。如果在相邻的标准单元中的每一者的边缘处形成有一个栅极结构且所述一个栅极结构被移除，则半导体装置的集成度可能由于栅极结构的面积而降低。
发明内容
本发明概念的一些实施例提供一种半导体装置，所述半导体装置包括衬底、第一栅极结构、第一接触塞及电源轨。所述衬底可包括第一单元区、第二单元区以及电源轨区，所述第一单元区及所述第二单元区可在第一方向上设置，且所述电源轨区可连接到所述第一单元区及所述第二单元区的在第二方向上相对的两端中的每一端，所述第二方向与所述第一方向实质上垂直。所述第一栅极结构可在所述衬底上在所述第二方向上从所述第一单元区与所述第二单元区之间的边界区域延伸到所述电源轨区。所述第一接触塞可形成在所述衬底的所述电源轨区上且接触所述第一栅极结构的上表面。所述电源轨可在所述衬底的所述电源轨区上在所述第一方向上延伸且可电连接到所述第一接触塞。所述电源轨可通过所述第一接触塞对所述第一栅极结构供应关断信号(turn-off signal)，以将所述第一单元区与所述第二单元区彼此电绝缘。
本发明概念的另一些实施例提供一种半导体装置，所述半导体装置包括衬底、有源鳍、第一栅极结构、第一接触塞及电源轨。所述衬底可包括第一单元区、第二单元区以及电源轨区，所述第一单元区与所述第二单元区可在第一方向上设置，且所述电源轨区可连接到所述第一单元区及所述第二单元区的在第二方向上相对的两端中的每一端，所述第二方向与所述第一方向实质上垂直。所述有源鳍可在所述衬底上在所述第一方向上从所述第一单元区的至少一部分连续地延伸到所述第二单元区的至少一部分。所述有源鳍可包括位于所述第一单元区上的第一部分以及位于所述第二单元区上的第二部分。所述第一栅极结构可在所述衬底上在所述第二方向上从所述第一单元区与所述第二单元区之间的边界区域延伸到所述电源轨区。所述第一接触塞可形成在所述衬底的所述电源轨区上且接触所述第一栅极结构的上表面。所述电源轨可在所述衬底的所述电源轨区上在所述第一方向上延伸且可电连接到所述第一接触塞。所述电源轨可通过所述第一接触塞向所述第一栅极结构供应关断信号，以将所述有源鳍的所述第一部分与所述第二部分彼此电绝缘。
本发明概念的又一些实施例提供一种半导体装置，所述半导体装置包括衬底、第一栅极结构及第二栅极结构、第一接触塞及第二接触塞、第一电源轨及第二电源轨。所述衬底可包括第一电源轨区、第二电源轨区、第一单元区及第二单元区，所述第一电源轨区及所述第二电源轨区中的每一者可在第一方向上延伸，所述第一电源轨区与所述第二电源轨区可在第二方向上彼此间隔开，所述第二方向与所述第一方向实质上垂直，且所述第一单元区与所述第二单元区可设置在所述第一电源轨区与所述第二电源轨区之间并在所述第一方向上彼此接触。所述第一栅极结构与所述第二栅极结构可彼此间隔开，且所述第一栅极结构与所述第二栅极结构中的每一者可在所述衬底上在所述第二方向上从所述第一单元区与所述第二单元区之间的边界区域分别延伸到所述第一电源轨区及所述第二电源轨区。所述第一接触塞及所述第二接触塞可分别形成在所述衬底的所述第一电源轨区及所述第二电源轨区上，且所述第一接触塞及所述第二接触塞可分别接触所述第一栅极结构的上表面及所述第二栅极结构的上表面。所述第一电源轨可在所述衬底的所述第一电源轨区上在所述第一方向上延伸，且所述第一电源轨可电连接到所述第一接触塞且通过所述第一接触塞向所述第一栅极结构供应正电压。所述第二电源轨可在所述衬底的所述第二电源轨区上在所述第一方向上延伸，且所述第二电源轨可电连接到所述第二接触塞且通过所述第二接触塞向所述第二栅极结构供应地电压或负电压。所述第一单元区与所述第二单元区可彼此电绝缘。
在一些实施例中，即使在具有高集成度的条件下，相邻的单元区也可彼此有效地绝缘。
附图说明
图1至图6是示出根据本发明概念一些实施例的半导体装置的平面图及剖视图。
图7至图37是示出根据本发明概念一些实施例的半导体装置制作中的一些处理步骤的平面图及剖视图。
图38及图39是示出根据本发明概念一些实施例的半导体装置的平面图。
图40是示出根据本发明概念一些实施例的半导体装置的平面图。
具体实施方式
现将在下文中参照附图更充分地论述本发明概念，在附图中示出本发明概念的示例性实施例。
图1至图6是示出根据本发明概念一些实施例的半导体装置的平面图或剖视图。图1及图2是平面图，且图3A至图6是剖视图。具体来说，图3A至图6分别是沿图2的线A-A'、B-B'、C-C'及D-D'截取的剖视图。
图1A是示出衬底的区的平面图，图1B是示出半导体装置的主要元件的布局的平面图，且图2是图1所示区X的放大平面图。图1B仅示出栅极结构、接触塞、通孔、电源轨及配线的布局以避免使图式复杂。
首先参照图1A，所述半导体装置可形成在包括第一区I及第二区II的衬底100上。衬底100可包含例如硅、锗、硅锗等半导体材料或例如GaP、GaAs、GaSb等III-V族半导体化合物。在一些实施例中，衬底100可为绝缘体上硅(silicon-on-insulator，SOI)衬底或绝缘体上锗(germanium-on-insulator，GOI)衬底。
在一些实施例中，第一区I可为其中可形成单元的单元区，且第二区II可为其中可形成用于向单元施加各种电压(例如，源极电压、漏极电压、地电压等)的电源轨的电源轨区。在一些实施例中，第二区II可在第一方向上延伸，且多个第二区II可被形成为在第二方向上彼此间隔开。
第一区I可设置在将与第一区I连接的各个第二区II之间。换句话说，第一区I的在第二方向上相对的两端中的每一端可连接到第二区II。在一些实施例中，第一区I可包括在第一方向上设置成与其连接的多个单元区。在图式中，第一区I只包括单元区(即，第一单元区CR1及第二单元区CR2)，然而本发明概念可并非仅限于此。在下文中，第一区I及第二区II可被界定成不仅包括衬底100的一些部分而且还包括与所述部分对应的上部空间及下部空间。
在一些实施例中，第一区I可包括p型金属氧化物半导体(p-type metal oxidesemiconductor，PMOS)区及n型金属氧化物半导体(n-type metal oxide semiconductor，NMOS)区，所述PMOS区与所述NMOS区可在第二方向上彼此间隔开。
参照图1B、图2、图3A及图4至图6，所述半导体装置可包括有源鳍105、第一栅极结构282及第二栅极结构284、杂质层210、第一接触塞至第四接触塞372、374、342及344、第一通孔至第四通孔422、424、426及428、电源轨462及配线464。
半导体装置还可包括隔离图案120、第一绝缘夹层至第四绝缘夹层220、300、390及430、顶盖层290、蚀刻停止层380、第一栅极间隔件182及第二栅极间隔件184、鳍间隔件190以及第一金属硅化物图案312及第二金属硅化物图案314。
有源鳍105可通过局部地移除衬底100的上部部分来形成，且因此可包含与衬底100的材料实质上相同的材料。有源鳍105可在第一区I中在第一方向上延伸，且在第二方向上可形成多个有源鳍105。
隔离图案120可形成在衬底100上，且可覆盖每一个有源鳍105的下侧壁。因此，有源鳍105可包括下部有源图案105b及上部有源图案105a，下部有源图案105b的侧壁可被隔离图案120覆盖，上部有源图案105a从隔离图案120的上表面突出。隔离图案120可包含氧化物，例如氧化硅。
在一些实施例中，PMOS区及NMOS区中的每一者可包括具有一个或多个有源鳍105的有源区，且PMOS区与NMOS区可通过隔离图案120的位于第一区I的在第二方向上的中心部分处的部分彼此隔离开。
在图式中，每一个有源鳍105跨越第一区I的在第一方向上相对的两端延伸；然而，本发明概念可并非仅限于此。因此，有源鳍105可在第一区I中在第一方向上被划分成多个片段。
在一些实施例中，有源鳍105中的至少一个有源鳍105可在第一方向上从第一单元区CR1的至少一部分到第二单元区CR2的至少一部分连续地延伸。换句话说，有源鳍105中的至少一个有源鳍105可跨越第一单元区CR1及第二单元区CR2的位于第一单元区CR1与第二单元区CR2之间的边界的相对两侧处的部分连续地延伸。
在图式中，PMOS区包括三个有源鳍105；然而，本发明概念可并非仅限于此。因此，PMOS区及NMOS区中的每一者可包括一个或多个有源鳍105。
第一栅极结构282可在第二方向上从相邻的单元区之间的边界区域延伸，举例来说，在有源鳍105及隔离图案120上从第一单元区CR1与第二单元区CR2之间的边界区域延伸到一个第二区II。在一些实施例中，一个第一栅极结构282可在PMOS区中在第二方向上从第一单元区CR1与第二单元区CR2之间的边界区域延伸到一个第二区II，且另一个第一栅极结构282可在NMOS区中在第二方向上从第一单元区CR1与第二单元区CR2之间的边界区域延伸到一个第二区II。以上两个第一栅极结构282可在第二方向上彼此间隔开。
多个第二栅极结构284可在第一方向上彼此间隔开。第二栅极结构284中的一些第二栅极结构284可在有源鳍105及隔离图案120上在第一区I以及与第一区I相邻的两个第二区II上延伸，且第二栅极结构284中的另一些第二栅极结构284可在有源鳍105及隔离图案120上在第一区I的一部分以及与第一区I的所述一部分相邻的一个第二区II上延伸。
第一栅极结构282可包括依序堆叠的第一界面图案242、第一栅极绝缘图案252、第一逸出功控制图案262及第一栅极电极272，且第二栅极结构284可包括依序堆叠的第二界面图案244、第二栅极绝缘图案254、第二逸出功控制图案264及第二栅极电极274。
第一界面图案242及第二界面图案244可包含氧化物(例如，氧化硅)，第一栅极绝缘图案252及第二栅极绝缘图案254可包含介电常数高的金属氧化物(例如，氧化铪、氧化钽或氧化锆等)，第一逸出功控制图案262及第二逸出功控制图案264可包含金属氮化物或金属合金(例如，氮化钛、钛铝、氮化钛铝、氮化钽、氮化钽铝等)，且第一栅极电极272及第二栅极电极274可包含电阻低的金属(例如，铝、铜、钽等)或其氮化物。
第一栅极间隔件182及第二栅极间隔件184可分别形成在第一栅极结构282的侧壁及第二栅极结构284的侧壁上，且鳍间隔件190可形成在有源鳍105的侧壁上。第一栅极间隔件182及第二栅极间隔件184以及鳍间隔件190可包含氮化物，例如氮化硅、碳氮氧化硅等。
杂质层210可填充有源鳍105上的与第一栅极结构282及第二栅极结构284相邻的第三凹槽，且杂质层210的上部部分可接触第一栅极间隔件182及第二栅极间隔件184。杂质层210可具有沿第二方向具有五边形或六边形形状的横截面。当相邻的有源鳍105之间的距离小时，在相邻的有源鳍105上生长的杂质层210可彼此合并以形成单个层。在图式中，示出从相邻的三个有源鳍105生长成彼此合并的一个杂质层210；然而，本发明概念可并非仅限于此。
在一些实施例中，PMOS区中的杂质层210可包含经p型杂质掺杂的单晶硅锗层，且可用作包括第二栅极结构284的PMOS晶体管的源极/漏极层。
NMOS区中的杂质层210可包含经n型杂质掺杂的单晶碳化硅层或经n型杂质掺杂的单晶硅，且可用作包括第二栅极结构284的NMOS晶体管的源极/漏极层。
第一绝缘夹层220可形成在有源鳍105及隔离图案120上以覆盖第一栅极间隔件182的外侧壁及第二栅极间隔件184的外侧壁。第一绝缘夹层220可不填充经合并杂质层210与隔离图案120之间的空间，且因此可形成气隙225。第一绝缘夹层220可包含氧化物，例如氧化硅。
顶盖层290与第二绝缘夹层300可依序堆叠在第一绝缘夹层220、第一栅极结构282及第二栅极结构284以及第一栅极间隔件182及第二栅极间隔件184上。顶盖层290可包含氮化物(例如，氮化硅)，且第二绝缘夹层300可包含氧化物(例如，氧化硅)。
第一接触塞372及第二接触塞374可延伸穿过第二绝缘夹层300及顶盖层290以分别接触第一栅极结构282的上表面及第二栅极结构284的上表面，且第三接触塞342及第四接触塞344可延伸穿过第一绝缘夹层220及第二绝缘夹层300以及顶盖层290以接触杂质层210的上表面。
第三接触塞342可不仅在第一区I中接触杂质层210的上表面，而且还在第二区II中接触与第三接触塞342相邻的隔离图案120的上表面。第四接触塞344可仅在第一区I中接触杂质层210的上表面。
第一金属硅化物图案312及第二金属硅化物图案314可分别形成在杂质层210与第三接触塞342及第四接触塞344之间。第一金属硅化物图案312及第二金属硅化物图案314可包含金属硅化物，例如硅化钴、硅化镍、硅化钛等。
参照图3B，第一接触塞372可接触第一栅极结构282在第二区II中的一端的侧壁。
第一接触塞372可包括依序堆叠的第一势垒图案352与第一导电图案362，第二接触塞374可包括依序堆叠的第二势垒图案(图中未示出)与第二导电图案(图中未示出)，第三接触塞342可包括依序堆叠的第三势垒图案322与第三导电图案332，且第四接触塞344可包括依序堆叠的第四势垒图案324与第四导电图案334。
在图式中，第三接触塞342及第四接触塞344中的每一者接触杂质层210在第一方向上的中心上表面，然而，本发明概念可并非仅限于此。在一些实施例中，第三接触塞342及第四接触塞344中的每一者可分别与第一栅极结构282的侧壁上的第一栅极间隔件182及第二栅极结构284的侧壁上的第二栅极间隔件184自对准，或者可分别与第二栅极结构284的侧壁上的第二栅极间隔件184自对准。
蚀刻停止层380与第三绝缘夹层390可依序堆叠在第二绝缘夹层300以及第一接触塞至第四接触塞372、374、342及344上。蚀刻停止层380可包含氮化物(例如，氮化硅、碳氮化硅、碳氮氧化硅等)，第三绝缘夹层390可包含例如氧化硅。作为另外一种选择，第三绝缘夹层390可包含低介电常数介电材料(例如，经碳掺杂的氧化硅(SiCOH)或经氟掺杂的氧化硅(F-SiO2))、多孔氧化硅(porous silicon oxide)、旋涂有机聚合物或无机聚合物(例如，氢倍半硅氧烷(hydrogen silsesquioxane，HSSQ)、甲基倍半硅氧烷(methylsilsesquioxane，MSSQ)等)。
第一通孔至第四通孔422、424、426及428可延伸穿过蚀刻停止层380及第三绝缘夹层390以分别接触第一接触塞至第四接触塞372、374、342及344的上表面。第一通孔422及第三通孔426可形成在第二区II中，且第二通孔424及第四通孔428可形成在第一区I中。
第一通孔422可包括依序堆叠的第五势垒图案402与第五导电图案412，第二通孔424可包括依序堆叠的第六势垒图案(图中未示出)与第六导电图案(图中未示出)，第三通孔426可包括依序堆叠的第七势垒图案406与第七导电图案416，且第四通孔428可包括依序堆叠的第八势垒图案408与第八导电图案418。
第四绝缘夹层430可形成在第三绝缘夹层390以及第一通孔至第四通孔422、424、426及428上。电源轨462可延伸穿过第四绝缘夹层430以共同接触第一通孔422的上表面及第三通孔426的上表面，且配线464可延伸穿过第四绝缘夹层430以接触第二通孔424的上表面或第四通孔428的上表面。
电源轨462可包括依序堆叠的第九势垒图案442与第九导电图案452，且配线464可包括依序堆叠的第十势垒图案444与第十导电图案454。在一些实施例中，电源轨462可在第二区II中在第一方向上延伸，且配线464可在第一区I中在第一方向上延伸。
在一些实施例中，第二区II的与第一区I的PMOS区相邻的部分中的电源轨462可供应正电压(例如，漏极电压Vdd)，第二区II的与第一区I的NMOS区相邻的部分中的电源轨462可供应负电压或地电压(例如，源极电压Vss)。
可形成在第一区I的PMOS区中且被通过第一通孔422及第一接触塞372从电源轨462供应正电压的第一栅极结构282可被关断，且因此第一单元区CR1及第二单元区CR2中的有源鳍105的分别位于第一栅极结构282下方的第一部分及第二部分可彼此电连接。
可形成在第一区I的PMOS区中且被通过第三通孔426及第三接触塞342从电源轨462供应正电压的杂质层210可用作包括第二栅极结构284的晶体管的源极区。可形成在第一区I的PMOS区中且被通过第四通孔428及第四接触塞344从配线464供应电压的杂质层210可用作包括第二栅极结构284的晶体管的漏极区。
同样，可形成在第一区I的NMOS区中且被通过第一通孔422及第一接触塞372从电源轨462供应地电压或负电压的第一栅极结构282可被关断，且因此第一单元区CR1及第二单元区CR2中的有源鳍105的分别位于第一栅极结构282下方的第一部分及第二部分可彼此电绝缘。
可形成在第一区I的NMOS区中且被通过第三通孔426及第三接触塞342从电源轨462供应地电压或负电压的杂质层210可用作包括第二栅极结构284的晶体管的源极区。可形成在第一区I的NMOS区中且被通过第四通孔428及第四接触塞344从配线464供应电压的杂质层210可用作包括第二栅极结构284的晶体管的漏极区。
在一些实施例中，第一栅极结构282可形成在第一区I的各个单元区之间的边界区域处，例如在第一单元区CR1与第二单元区CR2之间的边界区域处被形成为延伸到第二区II，且可在第二区II中通过第一通孔422及第一接触塞372从电源轨462供应关断信号。因此，在有源鳍105的在第一栅极结构282下方在第一方向上连续延伸的部分中可不形成沟道。换句话说，有源鳍105的位于第一单元区CR1与第二单元区CR2之间边界区域的两侧处的第一部分及第二部分可彼此电绝缘。
位于第一栅极结构282上的第一通孔422及第一接触塞372可不形成在第一区I中，而是形成在第二区II中，且因此可不占用第一区I中的单元结构的空间，例如第二接触塞374及第四接触塞344或者第二通孔424及第四通孔428。换句话说，用于在第一方向上使相邻的单元电绝缘的第一栅极结构282以及用于对第一栅极结构282施加电信号的第一通孔422及第一接触塞372可不形成在第一区I中，而是形成在第二区II中，且因此用于实施第一区I中的各个单元的布局的自由度可不会受到妨碍。
图7至图37是示出根据本发明概念一些实施例的半导体装置制作中的一些处理步骤的平面图或剖视图。具体来说，图7、图9、图11、图15、图19、图22、图25、图28及图33是平面图，且图8、图10、图12至图14、图16至图18、图20至图21、图23至图24、图26至图27、图29至图32及图34至图37是剖视图。图7至图37是图1所示区X的图式。
图8、图10、图12、图26、图29及图34是沿对应的平面图的线A-A'截取的剖视图，图13、图16、图30及图35是沿对应的平面图的线B-B'截取的剖视图，图14、图17、图20、图23、图27、图31及图36是沿对应的平面图的线C-C'截取的剖视图，且图18、图21、图24、图32及图37是沿对应的平面图的线D-D'截取的剖视图。
首先参照图7及图8，可局部地移除衬底100的上部部分以形成第一凹槽110，且因此可将有源鳍105形成为从衬底100突出。
在一些实施例中，有源鳍105可在第一方向上在第一区I及第二区II中延伸，且可将多个有源鳍105形成为在第二方向上彼此间隔开。
参照图9及图10，可使用覆盖第一区I的一部分的第一蚀刻掩模(图中未示出)来对有源鳍105以及衬底100的上部部分进行蚀刻以形成第二凹槽(图中未示出)，且可形成隔离图案120来填充第二凹槽以及第一凹槽110的下部部分。
在一些实施例中，第一蚀刻掩模可覆盖有源鳍105中的位于第一区I的与第二区II相邻的部分中的一些有源鳍105，且因此可移除有源鳍105中的远离第二区II的一些有源鳍105(即有源鳍105中的处于第一区I的在第二方向上的中心部分处的一些有源鳍105及有源鳍105中的处于第二区II中的一些有源鳍105)。
参照图1B，第一区I可包括PMOS区及NMOS区，所述PMOS区与所述NMOS区可在第二方向上彼此间隔开。换句话说，PMOS区及NMOS区中的每一者可包括具有一个或多个有源鳍105的有源区，且PMOS区与NMOS区可通过隔离图案120的位于第一区I的在第二方向上的中心部分处的部分彼此分开。
隔离图案120可通过以下步骤形成：移除第一蚀刻掩模；在衬底100上形成隔离层以填充第二凹槽及第一凹槽110；以及移除隔离层的一部分直到可暴露出有源鳍105的上部部分为止。隔离图案120可填充第二凹槽并覆盖有源鳍105的下侧壁。
参照图11至图14，可在衬底100上形成第一虚设栅极结构172及第二虚设栅极结构174。第一虚设栅极结构172及第二虚设栅极结构174可通过以下步骤形成：在衬底100的有源鳍105上以及隔离图案120上依序形成虚设栅极绝缘层、虚设栅极电极层及虚设栅极掩模层；使用第二蚀刻掩模(图中未示出)对虚设栅极掩模层进行蚀刻以形成第一虚设栅极掩模162及第二虚设栅极掩模164；以及使用第一虚设栅极掩模162及第二虚设栅极掩模164作为蚀刻掩模来依序蚀刻虚设栅极电极层及虚设栅极绝缘层。因此，第一虚设栅极结构172及第二虚设栅极结构174中的每一者可在有源鳍105及隔离图案120上延伸。
第一虚设栅极结构172可包括依序堆叠在衬底100的有源鳍105上以及隔离图案120的在第二方向上与有源鳍105相邻的部分上的第一虚设栅极绝缘图案142、第一虚设栅极电极152及第一虚设栅极掩模162，且第二虚设栅极结构174可包括依序堆叠在衬底100的有源鳍150上以及隔离图案120的在第二方向上与有源鳍105相邻的部分上的第二虚设栅极绝缘图案144、第二虚设栅极电极154及第二虚设栅极掩模164。
虚设栅极绝缘层可包含氧化物(例如，氧化硅)，虚设栅极电极层可包含例如多晶硅，且虚设栅极掩模层可包含氮化物(例如，氮化硅)。虚设栅极绝缘层可通过化学气相沉积(chemical vapor deposition，CVD)工艺、原子层沉积(atomic layer deposition，ALD)工艺等形成。作为另外一种选择，虚设栅极绝缘层可通过对衬底100的上部部分执行热氧化工艺形成，且在这种情形中，虚设栅极绝缘层可不形成在隔离图案120上，而是仅形成在有源鳍105上。虚设栅极电极层及虚设栅极掩模层也可通过CVD工艺、ALD工艺等形成。
可通过使用第三蚀刻掩模(图中未示出)执行蚀刻工艺将第一虚设栅极结构172及第二虚设栅极结构174部分地移除。
在一些实施例中，可通过蚀刻工艺将第一区I及第二区II中的每一者中的第一虚设栅极结构172的在第二方向上的中心部分移除。因此，第一虚设栅极结构172可从相邻的单元区之间的边界区域延伸，例如从第一单元区CR1与第二单元区CR2之间的边界区域延伸到一个第二区II。在一些实施例中，可在各个单元区之间的边界区域处形成可在第二方向上彼此间隔开的两个第一虚设栅极结构172，所述两个第一虚设栅极结构172分别在第二方向上延伸。
多个第二虚设栅极结构174可在第一方向上彼此间隔开。可通过蚀刻工艺将第二区II中第二虚设栅极结构174中的一些第二虚设栅极结构174的在第二方向上的中心部分移除，且可通过蚀刻工艺将第一区I及第二区II中的每一者中的第二虚设栅极结构174中的其他第二虚设栅极结构174的在第二方向上的中心部分移除。因此，第二虚设栅极结构174中的一些第二虚设栅极结构174可在第一区I以及与第一区I相邻的两个第二区II上延伸，且第二虚设栅极结构174中的另一些第二虚设栅极结构174可在第一区I的一部分以及与第一区I的所述一部分相邻的一个第二区II上延伸。
参照图15至图18，可分别在第一虚设栅极结构172的侧壁及第二虚设栅极结构174的侧壁上形成第一栅极间隔件182及第二栅极间隔件184，且可在有源鳍105中的每一者的侧壁上形成鳍间隔件190。
在一些实施例中，第一栅极间隔件182及第二栅极间隔件184以及鳍间隔件190可通过以下步骤形成：在第一虚设栅极结构172及第二虚设栅极结构174、有源鳍105及隔离图案120上形成间隔件层；以及对间隔件层进行各向异性蚀刻。
可对有源鳍105的与第一虚设栅极结构172及第二虚设栅极结构174相邻的上部部分进行蚀刻以形成第三凹槽200。
具体来说，可使用第一虚设栅极结构172及第二虚设栅极结构174以及位于第一虚设栅极结构172的侧壁及第二虚设栅极结构174的侧壁上的第一栅极间隔件182及第二栅极间隔件184作为蚀刻掩模来对有源鳍105的上部部分进行蚀刻以形成第三凹槽200。在所述蚀刻工艺中还可对鳍间隔件190进行蚀刻。在图式中，对有源鳍105中的每一者中的上部有源图案105a进行了部分蚀刻以形成第三凹槽200；然而，本发明概念可并非仅限于此。举例来说，第三凹槽200可通过不仅移除上部有源图案105a而且还移除下部有源图案105b的一部分来形成。
参照图19至图21，可在有源鳍105中的每一者上形成杂质层210以填充第三凹槽200。在一些实施例中，杂质层210可通过使用有源鳍105中的每一者的被第三凹槽200暴露出的顶表面作为晶种执行选择性外延生长(selective epitaxial growth，SEG)工艺形成。
在一些实施例中，可使用硅源气体(例如，二氯硅烷(SiH2Cl2)气体)及锗源气体(例如，锗烷(GeH4)气体)来执行SEG工艺以形成单晶硅锗层。还可使用p型杂质源气体(例如，二硼烷(B2H6)气体)来形成经p型杂质掺杂的单晶硅锗层。因此，杂质层210可用作PMOS晶体管的源极/漏极区。
作为另外一种选择，可使用硅源气体(例如，二硅烷(Si2H6)气体)及碳源气体(例如，甲基硅甲烷(SiH3CH3)气体)来执行SEG工艺以形成单晶碳化硅层。作为另外一种选择，可只使用硅源气体(例如，二硅烷(Si2H6)气体)来执行SEG工艺以形成单晶硅层。也可使用n型杂质源气体(例如，磷化氢(PH3)气体)来形成经n型杂质掺杂的单晶碳化硅层或者经n型杂质掺杂的单晶硅层。因此，杂质层210可用作NMOS晶体管的源极/漏极区。
杂质层210可在垂直方向及水平方向两个方向上生长，且可不仅填充第三凹槽200而且还接触第一栅极间隔件182的一部分及第二栅极间隔件184的一部分。杂质层210的上部部分可具有沿第二方向截取的横截面，所述横截面的形状可为五边形或六边形。当有源鳍105在第二方向上彼此间隔开短的距离时，杂质层210中的在第二方向上相邻的一些杂质层210可彼此合并以形成单个层。在图式中，示出在第二方向上从相邻的三个有源鳍105生长的一个经合并杂质层210。
参照图22至图24，可在有源鳍105及隔离图案120上形成第一绝缘夹层220以覆盖第一虚设栅极结构172及第二虚设栅极结构174、第一栅极间隔件182及第二栅极间隔件184、鳍间隔件190及杂质层210，且可将第一绝缘夹层220平坦化直到可分别暴露出第一虚设栅极结构172的第一虚设栅极电极152的顶表面及第二虚设栅极结构174的第二虚设栅极电极154的顶表面为止。还可将第一虚设栅极掩模162及第二虚设栅极掩模164移除，且还可将第一栅极间隔件182的上部部分及第二栅极间隔件184的上部部分移除。经合并杂质层210与隔离图案120之间的空间可不被第一绝缘夹层220完全填充，且因此可形成气隙225。
可通过化学机械抛光(CMP)工艺和/或回蚀工艺来执行平坦化工艺。
可将暴露出的第一虚设栅极电极152及暴露出的第二虚设栅极电极154以及位于第一虚设栅极电极152及第二虚设栅极电极154下方的第一虚设栅极绝缘图案142及第二虚设栅极绝缘图案144移除以形成第一开口232以及第二开口234，第一开口232暴露出有源鳍105的顶表面、隔离图案120的顶表面及第一栅极间隔件182的内侧壁，第二开口234暴露出有源鳍105的顶表面、隔离图案120的顶表面及第二栅极间隔件184的内侧壁。
参照图25至图27，可形成第一栅极结构282及第二栅极结构284以分别填充第一开口232及第二开口234。具体来说，在可对有源鳍105的被第一开口232及第二开口234暴露出的顶表面执行热氧化工艺以分别形成第一界面图案242及第二界面图案244之后，可在第一界面图案242及第二界面图案244、隔离图案120、第一栅极间隔件182及第二栅极间隔件184以及第一绝缘夹层220上依序形成栅极绝缘层及逸出功控制层，且可在逸出功控制层上形成栅极电极层以充分填充第一开口232及第二开口234的其余部分。
栅极绝缘层、逸出功控制层及栅极电极层可通过CVD工艺或ALD工艺形成。在某一实施例中，还可对栅极电极层执行热处理工艺，例如快速热退火(rapid thermalannealing，RTA)工艺、尖峰快速热退火(spike rapid thermal annealing，spike RTA)工艺、闪光快速热退火(flash rapid thermal annealing，flash RTA)工艺或激光退火工艺(laser annealing process)。
第一界面图案242及第二界面图案244可通过CVD工艺或ALD工艺代替热氧化工艺形成，且在这种情形中，第一界面图案242及第二界面图案244可不仅形成在有源鳍105的顶表面上而且还形成在隔离图案120的顶表面以及第一栅极间隔件182的内侧壁及第二栅极间隔件184的内侧壁上。
可将栅极电极层、逸出功控制层及栅极绝缘层平坦化直到可暴露出第一绝缘夹层220的顶表面为止，以形成依序堆叠在第一界面图案242的顶表面、隔离图案120的顶表面及第一栅极间隔件182的内侧壁上的第一栅极绝缘图案252及第一逸出功控制图案262且形成填充第一逸出功控制图案262上的第一开口232的其余部分的第一栅极电极272。因此，第一栅极电极272的底部及侧壁可被第一逸出功控制图案262覆盖。另外，可形成依序堆叠在第二界面图案244的顶表面、隔离图案120的顶表面及第二栅极间隔件184的内侧壁上的第二栅极绝缘图案254及第二逸出功控制图案264，且可形成填充第二逸出功控制图案264上的第二开口234的其余部分的第二栅极电极274。因此，第二栅极电极274的底部及侧壁可被第二逸出功控制图案264覆盖。
依序堆叠的第一界面图案242、第一栅极绝缘图案252、第一逸出功控制图案262及第一栅极电极272可形成第一栅极结构282，且第一栅极结构282及杂质层210可形成NMOS晶体管或PMOS晶体管。另外，依序堆叠的第二界面图案244、第二栅极绝缘图案254、第二逸出功控制图案264及第二栅极电极274可形成第二栅极结构284，且第二栅极结构284及杂质层210可形成NMOS晶体管或PMOS晶体管。
与图1B一起参照图28、图29A以及图30至图32，可在第一绝缘夹层220、第一栅极结构282及第二栅极结构284以及第一栅极间隔件182及第二栅极间隔件184上依序形成顶盖层290及第二绝缘夹层300，且可形成延伸穿过第二绝缘夹层300及顶盖层290以接触第一栅极结构282的上表面及第二栅极结构284的上表面的第一接触塞372及第二接触塞374以及延伸穿过第一绝缘夹层220及第二绝缘夹层300以及顶盖层290以接触杂质层210的上表面的第三接触塞342及第四接触塞344。
第三接触塞342及第四接触塞344可通过形成延伸穿过第一绝缘夹层220及第二绝缘夹层300以及顶盖层290的第三开口及第四开口(图中未示出)以暴露出杂质层210的上表面以及分别填充第三开口及第四开口来形成。在一些实施例中，第三开口可不仅暴露出第一区I中的杂质层210的上表面而且还暴露出在第二方向上与第一区I相邻的第二区II中的隔离图案120的上表面。第四开口可仅暴露出第一区I中的杂质层210的上表面。
在形成第三接触塞342及第四接触塞344之前，还可通过以下步骤在杂质层210的上表面上形成第一金属硅化物图案312及第二金属硅化物图案314：在杂质层210的被第三开口及第四开口暴露出的上表面上形成金属层；对金属层进行热处理；以及移除金属层的未发生反应的部分。
第一接触塞372及第二接触塞374可通过形成延伸穿过第二绝缘夹层300以及顶盖层290的第五开口及第六开口(图中未示出)以分别暴露出第一栅极结构282的上表面及第二栅极结构284的上表面以及分别填充第五开口及第六开口来形成。在一些实施例中，第五开口可暴露出第二区II中的第一栅极结构282的上表面，且第六开口可暴露出第一区I中的第二栅极结构284的上表面。由于第一接触塞372不是形成在第一区I中而是形成在第二区II中，因此可更容易地设计第一区I中的单元的布局。
参照图29B，第五开口可不仅暴露出第一栅极结构282在第二区II中的部分的上表面而且还暴露出第一栅极结构282在第二方向上的一端的侧壁。因此，第一接触塞372可接触第一栅极结构282在第二区II中的所述一端的侧壁。
在一些实施例中，第一接触塞至第四接触塞372、374、342及344中的每一者可通过以下步骤形成：在第三开口至第六开口的底部及侧壁上以及第二绝缘夹层300的上表面上形成势垒层；在势垒层上形成导电层以填充第三开口至第六开口；以及将导电层及势垒层平坦化直至到达第二绝缘夹层300的上表面。因此，第一接触塞至第四接触塞372、374、342及344中的每一者可包括导电图案以及覆盖导电图案的底部及侧壁的势垒图案。
具体来说，第一接触塞372可包括依序堆叠的第一势垒图案352与第一导电图案362，第二接触塞374可包括依序堆叠的第二势垒图案(图中未示出)与第二导电图案(图中未示出)，第三接触塞342可包括依序堆叠的第三势垒图案322与第三导电图案332，且第四接触塞344可包括依序堆叠的第四势垒图案324与第四导电图案334。
在图式中，第三接触塞342及第四接触塞344中的每一者接触杂质层210在第一方向上的中心上表面，然而本发明概念可并非仅限于此。在一些实施例中，第三接触塞342及第四接触塞344中的每一者可分别与第一栅极结构282的侧壁上的第一栅极间隔件182及第二栅极结构284的侧壁上的第二栅极间隔件184自对准，或者可分别与第二栅极结构284的两个侧壁上的第二栅极间隔件184自对准。
与图1B一起参照图33至图37，可在第二绝缘夹层300以及第一接触塞至第四接触塞372、374、342及344上依序形成蚀刻停止层380及第三绝缘夹层390，且可穿过第三绝缘夹层390及蚀刻停止层380形成第一通孔至第四通孔422、424、426及428以分别接触第一接触塞至第四接触塞372、374、342及344。
第一通孔422及第三通孔426可形成在第二区II中，且第二通孔424及第四通孔428可形成在第一区I中。
在一些实施例中，第一通孔至第四通孔422、424、426及428可通过以下步骤形成：穿过蚀刻停止层380及第三绝缘夹层390形成第七开口至第十开口(图中未示出)以分别暴露出第一接触塞至第四接触塞372、374、342及344的上表面；在第七开口至第十开口的底部及侧壁以及第三绝缘夹层390的上表面上形成势垒层；在势垒层上形成导电层以填充第七开口至第十开口；以及将导电层及势垒层平坦化直到可暴露出第三绝缘夹层390的上表面为止。因此，第一通孔至第四通孔422、424、426及428中的每一者可包括导电图案以及覆盖导电图案的底部及侧壁的势垒图案。
具体来说，第一通孔422可包括依序堆叠的第五势垒图案402与第五导电图案412，第二通孔424可包括依序堆叠的第六势垒图案(图中未示出)与第六导电图案(图中未示出)，第三通孔426可包括依序堆叠的第七势垒图案406与第七导电图案416，且第四通孔428可包括依序堆叠的第八势垒图案408与第八导电图案418。
再次参照图1至图6，可在第三绝缘夹层390以及第一通孔至第四通孔422、424、426及428上形成第四绝缘夹层430，且可形成电源轨462以及配线464，电源轨462延伸穿过第四绝缘夹层430以接触第一通孔422的上表面及第三通孔426的上表面，配线464延伸穿过第四绝缘夹层430以接触第二通孔424的上表面或第四通孔428的上表面。
电源轨462及配线464可通过以下步骤形成：形成延伸穿过第四绝缘夹层430的第十一开口(图中未示出)以共同暴露出第一通孔422的上表面及第三通孔426的上表面以及形成延伸穿过第四绝缘夹层430的第十二开口(图中未示出)以暴露出第二通孔424的上表面或第四通孔428的上表面；在第十一开口及第十二开口的底部及侧壁以及第四绝缘夹层430的上表面上形成势垒层；在势垒层上形成导电层以填充第十一开口及第十二开口；以及将导电层及势垒层平坦化直到可暴露出第四绝缘夹层430的上表面为止。因此，电源轨462及配线464中的每一者可包括导电图案以及覆盖导电图案的底部及侧壁的势垒图案。
具体来说，电源轨462可包括依序堆叠的第九势垒图案442与第九导电图案452，且配线464可包括依序堆叠的第十势垒图案444与第十导电图案454。
在一些实施例中，电源轨462可在第二区II中在第一方向上延伸，且配线464可在第一区I中在第一方向上延伸。
还可在第四绝缘夹层430、电源轨462及配线464上形成第五绝缘夹层(图中未示出)及上部配线(图中未示出)以完成半导体装置的制作。
图38及图39是示出根据一些实施例的半导体装置的平面图。除第三接触塞及第四接触塞以及第三通孔及第四通孔外，这些半导体装置可实质上相同于或相似于参照图1至图6所示出的半导体装置。因此，相同的参考编号指代相同的元件，且为简洁起见，在下文中可省略对相同元件的详细说明。
参照图38，可相邻于第一栅极结构282在第一单元区CR1及第二单元区CR2中形成第三接触塞342及第四接触塞344，且因此可在第三接触塞342及第四接触塞344上分别形成第三通孔426及第四通孔428。换句话说，可在第一栅极结构282的相对两侧处形成分别用作源极区及漏极区的杂质层210。
在图1至图6所示半导体装置中，可相邻于第一栅极结构282在第一单元区CR1及第二单元区CR2中的每一者中形成第三接触塞342，且可在第一栅极结构282的相对两侧处形成各自用作源极区的杂质层210。
参照图39，可相邻于第一栅极结构282在第一单元区CR1及第二单元区CR2中的每一者中形成第四接触塞344，且因此可在第四接触塞344上形成第四通孔428。换句话说，可在第一栅极结构282的相对两侧处形成各自用作漏极区的杂质层210。
图40是示出根据一些实施例的半导体装置的平面图。除有源鳍外，此半导体装置可实质上相同于或相似于参照图1至图6所示出的半导体装置。因此，相同的参考编号指代相同的元件，且为简洁起见，在下文中可省略对相同元件的详细说明。
参照图40，位于第一区I的第二单元区CR2中的PMOS区及NMOS区中的每一者可包括两个有源鳍105。
换句话说，第二单元区CR2的PMOS区及NMOS区中的每一者可包括与第一单元区CR1的PMOS区及NMOS区中的每一者的有源鳍105的数目不同数目的有源鳍105。
以上半导体装置可应用于各种类型的包括电源轨的存储器装置。举例来说，所述半导体装置可应用于例如中央处理器(central processing unit，CPU)、主处理单元(mainprocessing unit，MPU)或应用处理器(application processor，AP)等逻辑装置的电源轨。另外，所述半导体装置可应用于例如动态随机存取存储器(dynamic random accessmemory，DRAM)装置或静态随机存取存储器(static random access memory，SRAM)装置等易失性存储器装置的电源轨或者例如闪存存储器装置、相变随机存取存储器(phase-change random access memory，PRAM)装置、磁性随机存取存储器(magnetic randomaccess memory，MRAM)装置、电阻式随机存取存储器(resistive random access memory，RRAM)装置等非易失性存储器装置的配线结构。
上述是对一些实施例的说明，而不应被视为对实施例的限制。尽管已阐述了几个示例性实施例，但是所属领域中的技术人员将容易理解，在不实质上背离本发明概念的新颖教示及优点的条件下，在示例性实施例中可进行许多修改。因此，所有这些修改均旨在包含在由权利要求书所界定的本发明概念的范围内。在权利要求书中，手段附加功能条款旨在涵盖执行所述功能的本文所述结构，且不仅涵盖结构等效形式且还涵盖等效结构。因此，应理解，以上是对示例性实施例的例示，而不应被视为仅限于所公开的具体示例性实施例，且对所公开的示例性实施例的修改形式以及其他示例性实施例也旨在包含在随附权利要求书的范围内。

Claims (25)

1.一种半导体装置，包括：
衬底，包括第一单元区、第二单元区以及电源轨区，所述第一单元区及所述第二单元区在第一方向上设置，且所述电源轨区连接到所述第一单元区及所述第二单元区的在第二方向上相对的两端中的每一端，所述第二方向与所述第一方向实质上垂直；
第一栅极结构，在所述衬底上在所述第二方向上从所述第一单元区与所述第二单元区之间的边界区域延伸到所述电源轨区；
第一接触塞，在所述衬底的所述电源轨区上，所述第一接触塞接触所述第一栅极结构的上表面；以及
电源轨，在所述衬底的所述电源轨区上在所述第一方向上延伸，所述电源轨电连接到所述第一接触塞且通过所述第一接触塞对所述第一栅极结构供应关断信号，以将所述第一单元区与所述第二单元区彼此电绝缘。
2.根据权利要求1所述的半导体装置，还包括：
有源鳍，在所述衬底上在所述第一方向上从所述第一单元区的至少一部分连续地延伸到所述第二单元区的至少一部分，
其中所述第一栅极结构设置在所述有源鳍上。
3.根据权利要求2所述的半导体装置，其中所述有源鳍包括：
第一部分，在所述第一栅极结构以及所述第一单元区上与所述第一栅极结构相邻的区域之下；以及
第二部分，在所述第一栅极结构及所述第二单元区上与所述第一栅极结构相邻的区域之下，且
其中所述有源鳍的所述第一部分与所述第二部分彼此电绝缘。
4.根据权利要求3所述的半导体装置，还包括：
第一杂质层，在所述有源鳍的所述第一部分上；以及
第二杂质层，在所述有源鳍的所述第二部分上。
5.根据权利要求4所述的半导体装置，还包括：
第二接触塞，在所述第一单元区及所述电源轨区上，所述第二接触塞接触所述第一杂质层的上表面且电连接到所述电源轨；
第三接触塞，在所述第二单元区上，所述第三接触塞接触所述第二杂质层的上表面；以及
配线，在所述第二单元区上，所述配线电连接到所述第三接触塞。
6.根据权利要求5所述的半导体装置，还包括：
第二栅极结构，在所述第一单元区上在所述第一方向上与所述第一栅极结构间隔开，所述第二栅极结构在所述第一方向上相邻于所述第一杂质层；以及
第三栅极结构，在所述第二单元区上在所述第一方向上与所述第一栅极结构间隔开，所述第三栅极结构在所述第一方向上相邻于所述第二杂质层，
其中所述第一杂质层用作包括所述第二栅极结构的第一晶体管的源极区，且所述第二杂质层用作包括所述第三栅极结构的第二晶体管的漏极区。
7.根据权利要求5所述的半导体装置，还包括：
第一通孔，在所述电源轨区上，所述第一通孔接触所述第二接触塞的上表面及所述电源轨。
8.根据权利要求4所述的半导体装置，还包括：
第二接触塞，在所述第一单元区及所述电源轨区上，所述第二接触塞接触所述第一杂质层的上表面且电连接到所述电源轨；以及
第三接触塞，在所述第二单元区及所述电源轨区上，所述第三接触塞接触所述第二杂质层的上表面且电连接到所述电源轨。
9.根据权利要求8所述的半导体装置，还包括：
第二栅极结构，在所述第一单元区上在所述第一方向上与所述第一栅极结构间隔开，所述第二栅极结构在所述第一方向上相邻于所述第一杂质层；以及
第三栅极结构，在所述第二单元区上在所述第一方向上与所述第一栅极结构间隔开，所述第三栅极结构在所述第一方向上相邻于所述第二杂质层，
其中所述第一杂质层用作包括所述第二栅极结构的第一晶体管的源极区，且所述第二杂质层用作包括所述第三栅极结构的第二晶体管的源极区。
10.根据权利要求4所述的半导体装置，还包括：
第二接触塞，在所述第一单元区上，所述第二接触塞接触所述第一杂质层的上表面；
第一配线，在所述第一单元区上，所述第一配线电连接到所述第二接触塞；
第三接触塞，在所述第二单元区上，所述第三接触塞接触所述第二杂质层的上表面；以及
第二配线，在所述第二单元区上，所述第二配线电连接到所述第三接触塞。
11.根据权利要求10所述的半导体装置，还包括：
第二栅极结构，在所述第一单元区上在所述第一方向上与所述第一栅极结构间隔开，所述第二栅极结构在所述第一方向上相邻于所述第一杂质层；以及
第三栅极结构，在所述第二单元区上在所述第一方向上与所述第一栅极结构间隔开，所述第三栅极结构在所述第一方向上相邻于所述第二杂质层，
其中所述第一杂质层用作包括所述第二栅极结构的第一晶体管的漏极区，且所述第二杂质层用作包括所述第三栅极结构的第二晶体管的漏极区。
12.根据权利要求4所述的半导体装置，其中所述第一杂质层及所述第二杂质层中的每一者包含经p型杂质掺杂的硅锗。
13.根据权利要求12所述的半导体装置，其中所述电源轨向所述第一栅极结构供应正电压。
14.根据权利要求4所述的半导体装置，其中所述第一杂质层及所述第二杂质层中的每一者包含经n型杂质掺杂的硅或经n型杂质掺杂的碳化硅。
15.根据权利要求14所述的半导体装置，其中所述电源轨向所述第一栅极结构供应地电压或负电压。
16.根据权利要求1所述的半导体装置：
其中所述电源轨区包括在所述第二方向上彼此间隔开的第一电源轨区与第二电源轨区，在所述第一电源轨区及所述第二电源轨区上分别设置有第一电源轨及第二电源轨，
其中所述第一栅极结构包括在所述第二方向上彼此间隔开的两个第一栅极结构，所述两个第一栅极结构从所述第一单元区与所述第二单元区之间的所述边界区域分别延伸到所述第一电源轨区及所述第二电源轨区，且
其中所述第一电源轨供应正电压且所述第二电源轨供应地电压或负电压。
17.根据权利要求16所述的半导体装置，其中所述两个第一栅极结构分别在p型金属氧化物半导体区及n型金属氧化物半导体区上。
18.根据权利要求1所述的半导体装置，还包括：
第二通孔，在所述电源轨区上，所述第二通孔接触所述第一接触塞的上表面及所述电源轨。
19.根据权利要求18所述的半导体装置，其中所述第二通孔接触所述第一接触塞的侧壁的一部分。
20.一种半导体装置，包括：
衬底，包括第一单元区、第二单元区以及电源轨区，所述第一单元区与所述第二单元区在第一方向上设置，且所述电源轨区连接到所述第一单元区及所述第二单元区的在第二方向上相对的两端中的每一端，所述第二方向与所述第一方向实质上垂直；
有源鳍，在所述衬底上在所述第一方向上从所述第一单元区的至少一部分连续地延伸到所述第二单元区的至少一部分，所述有源鳍包括：
第一部分，在所述第一单元区上；以及
第二部分，在所述第二单元区上；
第一栅极结构，在所述衬底上在所述第二方向上从所述第一单元区与所述第二单元区之间的边界区域延伸到所述电源轨区；
第一接触塞，在所述衬底的所述电源轨区上，所述第一接触塞接触所述第一栅极结构的上表面；以及
电源轨，在所述衬底的所述电源轨区上在所述第一方向上延伸，所述电源轨电连接到所述第一接触塞，
其中所述电源轨通过所述第一接触塞向所述第一栅极结构供应关断信号，以将所述有源鳍的所述第一部分与所述第二部分彼此电绝缘。
21.根据权利要求20所述的半导体装置，还包括：
第一杂质层，在所述有源鳍的所述第一部分上；
第二杂质层，在所述有源鳍的所述第二部分上；以及
第二接触塞，在所述第一单元区及所述电源轨区上，所述第二接触塞接触所述第一杂质层的上表面且电连接到所述电源轨。
22.根据权利要求21所述的半导体装置，还包括：
第三接触塞，在所述第二单元区上，所述第三接触塞接触所述第二杂质层的上表面；以及
配线，在所述第二单元区上，所述配线电连接到所述第三接触塞。
23.根据权利要求22所述的半导体装置，还包括：
第二栅极结构，在所述第一单元区上在所述第一方向上与所述第一栅极结构间隔开，所述第二栅极结构在所述第一方向上相邻于所述第一杂质层；以及
第三栅极结构，在所述第二单元区上在所述第一方向上与所述第一栅极结构间隔开，所述第三栅极结构在所述第一方向上相邻于所述第二杂质层，
其中所述第一杂质层用作包括所述第二栅极结构的第一晶体管的源极区，且所述第二杂质层用作包括所述第三栅极结构的第二晶体管的漏极区。
24.一种半导体装置，包括：
衬底，包括第一电源轨区、第二电源轨区、第一单元区及第二单元区，所述第一电源轨区及所述第二电源轨区中的每一者在第一方向上延伸，所述第一电源轨区与所述第二电源轨区在第二方向上彼此间隔开，所述第二方向与所述第一方向实质上垂直，且所述第一单元区与所述第二单元区设置在所述第一电源轨区与所述第二电源轨区之间并在所述第一方向上彼此接触；
彼此间隔开的第一栅极结构与第二栅极结构，所述第一栅极结构与所述第二栅极结构中的每一者在所述衬底上在所述第二方向上从所述第一单元区与所述第二单元区之间的边界区域分别延伸到所述第一电源轨区及所述第二电源轨区；
第一接触塞及第二接触塞，分别在所述衬底的所述第一电源轨区及所述第二电源轨区上，所述第一接触塞及所述第二接触塞分别接触所述第一栅极结构的上表面及所述第二栅极结构的上表面；
第一电源轨，在所述衬底的所述第一电源轨区上在所述第一方向上延伸，所述第一电源轨电连接到所述第一接触塞且通过所述第一接触塞向所述第一栅极结构供应正电压；以及
第二电源轨，在所述衬底的所述第二电源轨区上在所述第一方向上延伸，所述第二电源轨电连接到所述第二接触塞且通过所述第二接触塞向所述第二栅极结构供应地电压或负电压，
其中所述第一单元区与所述第二单元区彼此电绝缘。
25.根据权利要求24所述的半导体装置，其中所述第一单元区及所述第二单元区分别包括p型金属氧化物半导体区及n型金属氧化物半导体区，所述p型金属氧化物半导体区及所述n型金属氧化物半导体区分别相邻于所述第一电源轨区及所述第二电源轨区且在所述第二方向上彼此间隔开，且
其中所述第一栅极结构及所述第二栅极结构分别设置在所述p型金属氧化物半导体区及所述n型金属氧化物半导体区上。
CN201811215341.5A 2017-10-19 2018-10-18 具有电源轨的半导体装置 Active CN109686737B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020170135748A KR102403031B1 (ko) 2017-10-19 2017-10-19 반도체 장치
KR10-2017-0135748 2017-10-19

Publications (2)

Publication Number Publication Date
CN109686737A true CN109686737A (zh) 2019-04-26
CN109686737B CN109686737B (zh) 2024-03-01

Family

ID=66171223

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811215341.5A Active CN109686737B (zh) 2017-10-19 2018-10-18 具有电源轨的半导体装置

Country Status (4)

Country Link
US (1) US10957765B2 (zh)
KR (1) KR102403031B1 (zh)
CN (1) CN109686737B (zh)
TW (1) TWI786166B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3514833B1 (en) * 2018-01-22 2022-05-11 GLOBALFOUNDRIES U.S. Inc. A semiconductor device and a method
US10748889B2 (en) * 2018-06-15 2020-08-18 Samsung Electronics Co., Ltd. Power grid and standard cell co-design structure and methods thereof
US11862637B2 (en) * 2019-06-19 2024-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Tie off device
US11803682B2 (en) * 2020-01-22 2023-10-31 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device including standard cell having split portions
KR20220159589A (ko) 2021-05-26 2022-12-05 삼성전자주식회사 표준 셀을 포함하는 집적회로 칩
US20230128985A1 (en) * 2021-10-22 2023-04-27 International Business Machines Corporation Early backside first power delivery network
US20230317610A1 (en) * 2022-03-30 2023-10-05 International Business Machines Corporation Cell optimization through source resistance improvement

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090026505A1 (en) * 2007-07-27 2009-01-29 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same
JP2012079931A (ja) * 2010-10-01 2012-04-19 Elpida Memory Inc 半導体装置およびその製造方法
US20130181271A1 (en) * 2012-01-17 2013-07-18 Elpida Memory, Inc. Semiconductor device and manufacturing method thereof
CN105374813A (zh) * 2014-08-29 2016-03-02 台湾积体电路制造股份有限公司 单元布局和结构
CN105470132A (zh) * 2014-09-03 2016-04-06 中芯国际集成电路制造(上海)有限公司 鳍式场效应管的形成方法
US20160211251A1 (en) * 2015-01-16 2016-07-21 Taiwan Semiconductor Manufacturing Company., Ltd. Semiconductor device layout, memory device layout, and method of manufacturing semiconductor device
US20160336183A1 (en) * 2015-05-14 2016-11-17 Globalfoundries Inc. Methods, apparatus and system for fabricating finfet devices using continuous active area design
CN106169455A (zh) * 2015-05-20 2016-11-30 三星电子株式会社 半导体器件
CN106847812A (zh) * 2015-10-15 2017-06-13 三星电子株式会社 集成电路器件

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7214991B2 (en) * 2002-12-06 2007-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. CMOS inverters configured using multiple-gate transistors
US9064725B2 (en) * 2012-12-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with embedded MOS varactor and method of making same
US8921940B2 (en) * 2013-03-15 2014-12-30 Samsung Electronics Co., Ltd. Semiconductor device and a method for fabricating the same
KR102175854B1 (ko) * 2013-11-14 2020-11-09 삼성전자주식회사 반도체 소자 및 이를 제조하는 방법
US20150311122A1 (en) 2014-04-28 2015-10-29 Globalfoundries Inc. Forming gate tie between abutting cells and resulting device
US10361195B2 (en) 2014-09-04 2019-07-23 Samsung Electronics Co., Ltd. Semiconductor device with an isolation gate and method of forming
US9547741B2 (en) 2014-10-20 2017-01-17 Globalfoundries Inc. Methods, apparatus, and system for using filler cells in design of integrated circuit devices
US9337099B1 (en) 2015-01-30 2016-05-10 Globalfoundries Inc. Special constructs for continuous non-uniform active region FinFET standard cells
KR102311929B1 (ko) 2015-04-01 2021-10-15 삼성전자주식회사 반도체 소자 및 이의 제조 방법
DE102015113605B4 (de) 2015-08-18 2018-09-27 Infineon Technologies Austria Ag Halbleitervorrichtung, die einen vertikalen PN-Übergang zwischen einem Bodybereich und einem Driftbereich enthält
CN107924945B (zh) * 2015-09-25 2021-10-01 英特尔公司 在两侧上具有金属的功率门
JP6591291B2 (ja) * 2016-01-07 2019-10-16 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090026505A1 (en) * 2007-07-27 2009-01-29 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same
JP2012079931A (ja) * 2010-10-01 2012-04-19 Elpida Memory Inc 半導体装置およびその製造方法
US20130181271A1 (en) * 2012-01-17 2013-07-18 Elpida Memory, Inc. Semiconductor device and manufacturing method thereof
CN105374813A (zh) * 2014-08-29 2016-03-02 台湾积体电路制造股份有限公司 单元布局和结构
CN105470132A (zh) * 2014-09-03 2016-04-06 中芯国际集成电路制造(上海)有限公司 鳍式场效应管的形成方法
US20160211251A1 (en) * 2015-01-16 2016-07-21 Taiwan Semiconductor Manufacturing Company., Ltd. Semiconductor device layout, memory device layout, and method of manufacturing semiconductor device
US20160336183A1 (en) * 2015-05-14 2016-11-17 Globalfoundries Inc. Methods, apparatus and system for fabricating finfet devices using continuous active area design
CN106169455A (zh) * 2015-05-20 2016-11-30 三星电子株式会社 半导体器件
CN106847812A (zh) * 2015-10-15 2017-06-13 三星电子株式会社 集成电路器件

Also Published As

Publication number Publication date
TW201924058A (zh) 2019-06-16
KR20190043777A (ko) 2019-04-29
US20190123140A1 (en) 2019-04-25
KR102403031B1 (ko) 2022-05-27
TWI786166B (zh) 2022-12-11
US10957765B2 (en) 2021-03-23
CN109686737B (zh) 2024-03-01

Similar Documents

Publication Publication Date Title
CN109686737A (zh) 具有电源轨的半导体装置
US9780097B2 (en) Dual-port SRAM devices and methods of manufacturing the same
US7851309B2 (en) Selective epitaxy vertical integrated circuit components and methods
JP7427012B2 (ja) フィン形ブリッジ領域によって結合された垂直に積み重ねられたナノシートを有するトランジスタ・チャネル
TWI681563B (zh) 半導體裝置
US20160343708A1 (en) Semiconductor devices and methods of manufacturing the same
KR101397598B1 (ko) 반도체 집적 회로 장치 및 그 제조 방법
US20230215868A1 (en) Semiconductor device and method of manufacturing the same
US9608117B2 (en) Semiconductor devices including a finFET
CN107430996A (zh) 具有抬高的有源区域的场效应晶体管及其制造方法
CN111276490B (zh) 一种三维存储器及其制作方法
CN108511447A (zh) 垂直存储器件
JP2005094005A (ja) 縦形歪シリコン（ｓｔｒａｉｎｅｄｓｉｌｉｃｏｎ）・デバイスの方法および構造
CN106531719A (zh) 包括接触塞的半导体装置
US9812450B2 (en) Semiconductor devices and methods of manufacturing the same
US9385051B2 (en) Method for the formation of a FinFET device having partially dielectric isolated fin structure
US9240482B2 (en) Asymmetric stressor DRAM
JP2022523346A (ja) フィン形ブリッジ領域によって結合された垂直に積み重ねられたナノシートを有するトランジスタ・チャネル
TW202044515A (zh) 半導體裝置
CN111223938B (zh) 晶体管
US20210184038A1 (en) Semiconductor devices
CN110970486A (zh) 半导体器件
US20230352547A1 (en) Semiconductor devices
US11956964B2 (en) Semiconductor memory device and method of manufacturing thereof
US20240072177A1 (en) Semiconductor devices

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant