CN1096748C - 具抗扰性的动态cmos电路 - Google Patents

具抗扰性的动态cmos电路 Download PDF

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CN1096748C
CN1096748C CN96122428A CN96122428A CN1096748C CN 1096748 C CN1096748 C CN 1096748C CN 96122428 A CN96122428 A CN 96122428A CN 96122428 A CN96122428 A CN 96122428A CN 1096748 C CN1096748 C CN 1096748C
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nfet
node
pfet
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phase inverter
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CN1154604A (zh
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J·J·科维诺
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International Business Machines Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits

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  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Logic Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

一种抗扰性有所改进的动态CMOS电路，包括：第一和第二NFET叠置器件，分别连接在地与第一节点之间。输入节点接离接地点最近的第一NFET器件，时钟节点接离第一节点最近的第二NFET器件。第一节点与叠置的NFET器件形成的一个节点之间连接有一个PFET器件。第一NFET器件和PFET器件形成供接收输入信号用的倒相器，通过调节倒相器的PFET/NFET比值调节倒相器的转接点，从而提高电路的抗扰性。

Description

具抗扰性的动态CMOS电路
本发明涉及动态互补金属氧化物半导体(CMOS)电路，更具体地说，涉及一种抗扰性有所改进的高速CMOS电路。
在高速时控制动态CMOS电路的许多应用中，接收电路取一叠置方式的场效应晶体管(FET)器件由时钟信号和输入数据信号驱动。输入数据信号往往经驱动后直接输入NFET(n型FET)中。然而，这类接收电路不具抗扰性，噪声容限由NFET器件的大小控制。解决这个问题的方法是用静态倒相器缓冲输入数据信号，但费用大。
因此，本发明的目的是提供一种抗扰性有所改进的动态计时CMOS电路。
按照本发明的使接收电路修改成数据是通过最直接接地的器件输入的，并且时钟输入器件叠置在数据输入器件上方。此外，在输入与叠置时钟器件及输入器件形成的节点之间接上一个PFET(P型FET)器件。接收输入信号的PFET器件和NFET器件形成倒相器。信号输入断路点的设定不是按传统的作法那样通过调节NFET阈电压Vt而是通过调节倒相器的PFET/NFET比值进行的。PFET/NFET比值最好在大约1∶8至1∶4的范围。
为达到上述和其它优点，按照本发明在实施例中即将说明的目的，本发明提供的抗扰性有所改进的CMOS接收电路包括：叠置的第一和第二NFET器件，分别连接在地与第一节点之间，一个输入节点连接到距接地点最近的第一NFET器件，一个时钟接点连接到距所述第一节点最近的第二NNEF器件；一个PFET器件，连接在所述输入节点与由叠置的NFET器件形成的一个节点之间；所述第一NFET器件和所述PFET器件形成倒相器，供接收输入信号用，倒相器的转接点可以通过调节倒相器的PFET/NFET比值加以调节，从而提高电路的抗扰性。
上述电路方案可用于各种用途中，包括(但不局限于)CMOS接收机、动态“与”/“与非”门、动态多路复用电路和动态差动输入电路。不言而喻，上述一般性的说明和下面的详细说明都是举例性质的，其目的是进一步说明所提出的本发明。
参看附图阅读下面本发明最佳实施例的详细说明可以更好地理解本发明的上述和其它目的、观点和优点。附图中：
图1是装有常规CMOS接收电路的动态“与”电路的原理图；
图2是采用本发明经改进的CMOS接收电路的动态“与”电路的原理图；
图3是本发明应用在动态多路复用电路中的接收电路的原理图；
图4是本发明应用于差动输入用途的接收电路的原理图。
参看附图，更具体地说，参看图1，首先说明含有常规高速接收电路的动态“与”电路来举例说明本发明要解决的问题。“与”电路接收时钟信号(CLKL)输入数据信号(IN)和外部引发的复原(RST)信号。不言而喻，若RST节点接地，电路就成为自复原电路。时钟信号一般是内部产生的，而且没有噪声，输入数据信号则是芯片外产生的，而且有噪声。
在此电路中，第一NFET器件12用来接收输入到电路的数据信号(IN)。时钟信号(CLKL)输入到叠置在NFET器件12与地之间的第二NFET器件14。电路平常工作时，在时间t0，节点16预充电而处于高电位，输出节点18则经倒相器20预充电而处于低电位。PFET 22由倒相器20驱动以维持这个预充电状态。
NFET器件12栅极上的输入数据信号(IN)给NFET器件12加上了偏压而使其导通，而当时钟信号(CLKL)以脉冲形式加到NFET器件14的栅极时，节点16处于放电状态，通过倒相器20促使输出节点18处于高电位。在复原操作时，时钟信号(CLKL)脉冲加上之后，复原信号(RST)转入低电平，促使节点16通过“与非”门24、倒相器链26和PFET器件28恢复高电位，并使输出节点18通过同样的“与非”门24和倒相器链26和NFET器件32而输入低电位。由于输出节点18是低电位，与非门24的输出变为高电位，将PFET器件28和NFET器件32关断。于是电路恢复到其预充电的电平。
再看看包括NFET器件12和14的接收电路。这些常规的接收输入电路经常出现的问题是，由于输入信号直接输入NFET器件，因而电路没有充分的抗扰性。阈值电压Vt一般为0.4伏，是NFET器件的转接点。此外，NFET器件本身也是造成源极至接地点通路中一定量噪声的原因。图1中，噪声容限由PFET器件22控制。
为减少输入噪声和缓冲输入信号，有人采用象图1中所示的34和36的倒相器。这样做虽然提高了电路的抗扰性，但电路却显著地慢下来了。此外，还有人用“或非”型的输入电路来减少DRAM(动态随机存取存储器)器件中的噪声，但同样也使电路慢下来。
有鉴于此，高速电路中就需要有一个促使抗扰性有所改进的CMOS接收电路。抗扰性问题的解决办法不应使用电路显著慢下来。
图2示出了按本发明修改的图1电路。图2中，CMOS接收电路是通过对调NFET叠置器件12和14的位置进行修改的。这样做使时钟信号(静噪信号)NFET器件14处在叠置器件顶部，输入信号(噪声信号)NFET器件12离接地点极近。此外，在源极电压Vdd与NFET12与14之间的节点38之间还加上PFET器件36。输入信号(IN)连接PFET器件36的栅极。这样，输入信号就输入到包括PFET器件36和NFET器件12的倒相器。阈值电压Vt取决于输入数据信号(IN)，可根据PFET16和NFET 12的器件强度比加以调节。这里使用的器件强度一词是指器件所能传导的电流量。倒相器的转接点可通过改变PFET 36和NFET12的尺寸比加以调节，从而提高电路的抗扰性。
具体PFET/NFET器件强度比的选择牵涉到电路性能(即速率)和噪声容限的平衡问题。具体地说，增加PFET36的尺寸会提高噪声容限但会牵制动态“与”电路的性能。PFET器件36的器件强度为NFET器件34强度的大约1/8至1/4的范围时，通常可以使电路具有良好的抗扰性和相当好的性能。
本发明的接收电路不局限于图2的动态“与”电路，它可应用于任何需要高速(“与”/“与非”)电路且要求提高其中一个输入信号抗扰性的用途。
图3示出了应用本发明原理的动态多路复用电路。图3中，有噪声的各数据输入可以连接到输入节点42和44。早到达且可局部加以缓冲的各控制输入接输入节点42和44。节点42处的输入信号输入由晶体管52和54组成的倒相器，节点44处的输入信号则输入由晶体管56和58组成的倒相器。本发明多路复用实施例的倒相器PFET/NFET器件强度比与图2实施例的一样。
图4示出了用于差动输入的实施例。这里，有噪声的数据输入连接到节点62和64。这些有噪声的输入分别连接由NFET器件66和PFET器件68组成的倒相器和由NFET器件72和PFET器件74组成的倒相器。第二输入信号为时钟或控制信号CLK，加到两叠置器件顶部输入端的NFET器件76和78上。
虽然本发明是就上述一些实施例说明的，但本技术领域的行家们都知道，在不脱离本说明书所附权利要求书的精神实质和范围的前提下是可以对上述实施例进行修改的。

Claims (4)

1.一种动态CMOS电路，包括：
第一和第二叠置的NFET器件，连接在第一节点与地之间，第二NFET器件离接地点最近；
第一数据输入端，连接到所述第一NFET器件，所述数据输入端相对地静噪；
第二时钟输入端，连接到所述第二NFET器件，所述时钟输入端有噪声；
一个PFET器件，连接在一个源极电压与由第一和第二NFET器件形成的一个节点之间，PFET器件连接到所述数据输入端，从而使PFET器件和第二NFET器件形成一个倒相器，通过调节PFET/NFET比值来设定输入信号断路点，从而提高了接收电路的抗扰性。
2.如权利要求1所述的CMOS接收电路，其特征在于还包括：
一个输出节点，通过一个倒相器耦合到所述第一节点；和
复原装置，供预充电所述第一节点使其处于高电位，并预充电所述输出节点使其处于低电位，所述第一和第二输入同时出现时促使所述第一节点放电，并使所述输出节点通过所述倒相器而处于高电位，这之后所述复原装置再次预充电第一节点使其处于高电位，并再次预充电所述输出节点使其处于低电位。
3.如权利要求1所述的动态CMOS电路，特征在于还包括：
第三和第四叠置NFET器件，连接在所述第一节点与地之间，第四NFET器件离接地点最近；
第三输入端，接第三NFET器件，所述第三输入端相对静噪；
第四输入端，接第四NFET器件，所述第四输入端有噪声；和
第二PFET器件，连接在源电压与由第三和第四NFET器件形成的一个节点之间，第二PFET的栅极接第四输入端从而使PFET器件和第四NFET器件形成第二倒相器，通过调节第二倒相器的PFET/NFET比值设定输入信号的断路点，从而提高所述动态CMOS电路第四输入端的抗扰性。
4.如权利要求1-3中任一项所述的动态CMOS电路，其特征在于，第一和第二换流器的PFET/NFET比值约在1∶8至1∶4的范围。
CN96122428A 1995-10-24 1996-10-03 具抗扰性的动态cmos电路 Expired - Fee Related CN1096748C (zh)

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US547269 1990-07-03
US547,269 1990-07-03
US08/547,269 US5650733A (en) 1995-10-24 1995-10-24 Dynamic CMOS circuits with noise immunity

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CN1154604A (zh) 1997-07-16
KR970024173A (ko) 1997-05-30
SG43393A1 (en) 1997-10-17
EP0771074A3 (en) 1998-02-25
JPH09148918A (ja) 1997-06-06
EP0771074A2 (en) 1997-05-02
US5650733A (en) 1997-07-22

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