CN109659274A - 形成导电接触结构至半导体装置的方法及所产生的结构 - Google Patents

形成导电接触结构至半导体装置的方法及所产生的结构 Download PDF

Info

Publication number
CN109659274A
CN109659274A CN201811113696.3A CN201811113696A CN109659274A CN 109659274 A CN109659274 A CN 109659274A CN 201811113696 A CN201811113696 A CN 201811113696A CN 109659274 A CN109659274 A CN 109659274A
Authority
CN
China
Prior art keywords
contact
conducting wire
gate
grid
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201811113696.3A
Other languages
English (en)
Other versions
CN109659274B (zh
Inventor
谢瑞龙
拉尔斯·W·赖柏曼
丹尼尔·恰尼莫盖姆
朴灿柔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries US Inc
Original Assignee
GlobalFoundries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GlobalFoundries Inc filed Critical GlobalFoundries Inc
Publication of CN109659274A publication Critical patent/CN109659274A/zh
Application granted granted Critical
Publication of CN109659274B publication Critical patent/CN109659274B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816Aspects relating to the layout of the pattern or to the size of vias or trenches
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895Local interconnects; Local pads, as exemplified by patent document EP0896365
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226Via connections in a multilevel interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Geometry or layout of the interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642Isolation within the component, i.e. internal isolation
    • H01L29/0649Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41791Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/1418Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181On opposite sides of the body

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明涉及形成导电接触结构至半导体装置的方法及所产生的结构,揭示于本文的一种例示方法可包括:形成接触蚀刻结构于位在第一及第二下导电结构之上的一层绝缘材料中,其中该接触蚀刻结构的至少一部分横向位在该第一及该第二下导电结构之间,形成邻近该接触蚀刻结构的第一侧的第一导电线路及第一导电接触以及形成邻近该接触蚀刻结构的第二侧的第二导电线路及第二导电接触,其中该第一及该第二导电线路之间的间隔大约等于该接触蚀刻结构的一尺寸。

Description

形成导电接触结构至半导体装置的方法及所产生的结构
技术领域
本揭示内容大致有关于半导体装置的制造,且尤其关于形成导电接触结构至半导体装置的各种新颖方法及所产生的新颖结构。
背景技术
现代集成电路(IC)产品包括:形成于面积很小的半导体衬底或芯片上的大量主动及被动半导体装置(亦即,电路组件)。例如,主动半导体装置包括各种类型的晶体管,例如场效应晶体管(FET)、双极晶体管等等。被动半导体装置的例子包括电容器、电阻器等等。这些半导体装置配置成为IC产品的各种功能组件的一部分的各种电路,例如,微处理器(逻辑区)、内存阵列(内存区)、ASIC等等。如同所有电子装置,IC产品中的半导体装置需要通过布线电气连接使得它们可按设计运作。在IC产品中,完成此类布线是通过形成于半导体衬底之上的多个金属化层。
通常,由于大量的半导体装置(亦即,电路组件)以及现代集成电路的必要复杂布局,所以在有半导体装置制造于其上的相同装置层级内无法建立个别半导体装置的电气连接或“布线排列”。因此,构成 IC产品的整体布线图案的各种电气连接被形成于金属化系统中,其包含形成于产品的装置层级之上的一或更多附加堆栈的所谓的“金属化层”。这些金属化层通常由数层绝缘材料构成,以及在该绝缘材料层中形成导电金属线路或导电通孔。一般而言,导电线路提供层内 (intra-level)电气连接,同时导电通孔在导电线路的不同层级之间提供层间(inter-level)连接或垂直连接。这些导电线路及导电通孔可由各种不同材料构成,例如铜、钨、铝等等(以及适当的阻障层)。集成电路产品中的第一金属化层通常被称为“M1”层。通常,多个导电通孔(通常被称为“V0”通孔)用来在M1层与较低层级导电结构(所谓的装置层级接触(以下会有更完整的解释))之间建立电气连接。在有些更先进的装置中,在装置层级接触与V0通孔之间形成由导电线路(有时称为“M0”层)构成的另一金属化层。
图1的横截面图图示由形成于半导体衬底12中及之上的晶体管装置11构成的例示IC产品10。也图示多个所谓的“CA接触”结构14 用于建立电气连接至装置11的示意图标源极/漏极区20,以及有时被称为“CB接触”结构的栅极接触结构16。如图1所示,CB栅极接触16通常垂直位在包围装置11的隔离材料13之上,亦即,CB栅极接触 16通常不位在界定衬底12中的主动区之上,但是在有些先进架构中可能会如此。
晶体管11包含例示栅极结构22,亦即,栅极绝缘层22A与栅极电极22B,栅极帽盖24,侧壁间隔体26及示意图示源极/漏极区20。如上述,在制程流程的这一点,隔离区13也已形成于衬底12中。在图标于图1的制造点,数层绝缘材料30A、30B,亦即,层间介电质材料,已形成于衬底12之上。其他数层材料未图示于附图,例如接触蚀刻止挡层及其类似者。也图示例示突起外延源极/漏极区32与源极/漏极接触结构34,其通常包括所谓的“沟槽硅化物”(TS)结构36。CA接触结构14的形式可为离散的接触组件,亦即,在从上面观看时有大致像方形的形状或圆柱形形状的一或更多个别接触插塞(contact plug),其形成于层间介电质材料中。在其他的应用中,CA接触结构14也可为接触底下线路型特征的线路型特征,例如,接触源极/漏极区20的TS结构36,且通常在与晶体管11的栅极宽度方向平行的方向延伸越过源极 /漏极区20上的整个主动区,亦即,进出1的图纸的平面。CA接触14 与CB接触16在工业内都被视为装置层级接触。
图1图标IC产品10的例示例子,其包括产品10的多层级金属化系统的所谓M0金属化层。该M0金属化层形成于一层绝缘材料46中,例如,低k绝缘材料,且被形成为可建立电气连接至装置层级接触–CA 接触14与CB接触16。图1也图标产品10的所谓M1金属化层,其形成于一层绝缘材料38中,例如,低k绝缘材料。提供所谓V0通孔40 的多个导电通孔以在M0金属化层与M1金属化层之间建立电气连接。 M0金属化层及M1金属化层两者通常(各自)包括按需要路由越过产品10的多条金属线路44、42。M0金属化层的形成有助于减少形成于衬底 12上的电路的总电阻。不过,在有些IC产品中,可省略MO金属化层且使M1金属化层的V0通孔40与CA接触14及CB接触16接触。
通常通过在相关绝缘材料层中形成实质越过整个衬底的长连续沟槽而形成金属化线路(例如,线路44、42)。之后,这些金属化沟槽填满一或更多导电材料且执行一或更多化学机械研磨(CMP)制程以移除在沟槽外的多余导电材料。在典型制程流程的此时,净结果是金属化线路为延伸越过整个衬底的相对长连续结构。最终,必须移除或“切掉”部分的连续金属化线路以建立集成电路的功能布线图案,亦即,单一连续金属化线路可切成数个互相电气隔离的较小片段,使得这些个别的、小的“切断后”片段各自可被金属化系统的其他组件接触。不过,把这些连续金属化线路切成较小片段可能会是挑战性高又费时的制程,会造成加工失误且对产品产出有不利的影响。
形成用于IC产品的各种晶体管装置必须互相电气隔离以在电路中正确地运转。通常,这是通过在衬底12中形成沟槽,且用例如二氧化硅的绝缘材料填满沟槽来实现。在产业内,这些隔离区有时可称为“扩散阻断(diffusion break)”。图2的简化平面图图标IC产品10的一部分,其中例示单一扩散阻断(SDB)结构50使IC产品的两个例示电路结构52及54沿着直线56互相分离。在一实施例中,区段52可为NAND2 电路结构,同时区段54可为MUX电路结构。也图示于图2的是由栅极帽盖24与在晶体管装置的源极/漏极区的沟槽硅化物区36构成的多个晶体管结构。各种金属线路60也图示于图2。
如圆圈区70所示,已形成CA接触结构14(以虚线图示)用来建立电气连接至晶体管在SDB 50的相对两侧的源极/漏极区。为了做成金属线路60与底下CA接触结构14之间的连接,在各个金属线路60的末端之间必须有尖端对尖端间隔(tip-to-tip spacing)72。这通常是通过执行光刻及蚀刻制程以在各个线路60的一层绝缘材料(未图示)中界定分离的沟槽,之后在使用双镶嵌加工技术的同时形成CA接触结构 14及金属线路60两者来实现。在制作此类连接时的另一典型要求是金属线路60的末端需要与CA接触结构14重叠一段距离74以确保金属线路60与CA接触结构14之间有充分的接触面积,致使整体接触配置的电阻相对于设计过程所预期的不会增加。通常,在IC产品包括SDB 隔离结构时,CA源极/漏极接触结构14必须在对应至各种晶体管装置的栅极结构的栅极间距的距离处被接触,以充分利用所达成的空间节省。晶体管在现代IC产品上的栅极间距目前很小且预料会随着未来开发的产品而进一步减小。可惜,如果现代晶体管装置有极小尺寸,半导体装置在现代IC产品上的堆积密度增加,以及晶体管装置在现代IC 产品上的栅极间距极小且一直递减的话,对于具有此一尖端对尖端配置的此类金属线路60来直接图案化沟槽会极具挑战性。也图示于图2 中的圆圈区80的是形成接触隔开的CB栅极接触结构16(形成为可接触不同晶体管装置上的栅极结构)的金属线路60。在接触栅极接触结构 16的金属线路60也以尖端对尖端组构配置时,在金属线路60的末端之间在此组构下有更多间隔。尽管如此,形成相对于栅极接触结构16 有所欲尺寸及位置的这些线路60仍然是极具挑战性的制程,如果没有准确地完成,可能导致装置失效。
本揭示内容针对形成导电接触结构至半导体装置的各种新颖方法以及所产生的新颖结构,这可避免或至少减少上述问题中的一或更多的影响。
发明内容
以下提出本发明的简化概要以提供本发明的一些方面的基本理解。此概要并非本发明的穷举式总览。它不是旨在识别本发明的关键或重要组件或者是描绘本发明的范畴。唯一的目的是要以简要的形式提出一些概念作为以下更详细的说明的前言。
大致上,本揭示内容针对形成导电接触结构至半导体装置的各种新颖方法及所产生的新颖结构。揭示于本文的一种例示方法可包括:在第一及第二下导电结构之上形成包含第一材料的一层绝缘材料,以及在该层绝缘材料中形成接触蚀刻结构,其中该接触蚀刻结构包含与该第一材料不同的第二材料,且其中该接触蚀刻结构的至少一部分横向位在该第一下导电结构的至少一部分与该第二下导电结构的至少一部分之间。在此实施例中,该方法也包括:形成邻近该接触蚀刻结构的第一侧的第一导电线路及第一导电接触,其中该第一导电接触导电地耦合至该第一下导电结构,以及形成邻近该接触蚀刻结构的第二侧的第二导电线路及第二导电接触,其中该第二导电接触导电地耦合至该第二下导电结构,且其中该第一及该第二导电线路之间的间隔大约等于该接触蚀刻结构的尺寸。
附图说明
参考以下结合附图的说明可明白本揭示内容,其中类似的组件以相同的附图标记表示,且其中:
图1及图2图示用于集成电路产品的装置层级接触及金属化层的各种例示先前技术配置;以及
图3至图12图示揭示于本文用于形成导电接触结构至半导体装置的各种新颖方法以及所产生的新颖装置结构。
尽管揭示于本文的专利目标容易做成各种修改及替代形式,然而本文仍以附图为例图示本发明的几个特定具体实施例且详述于本文。不过,应了解本文所描述的特定具体实施例并非旨在把本发明限定为本文所揭示的特定形式,反而是,本发明应涵盖落在如随附权利要求书所界定的本发明精神及范畴内的所有修改、等价及替代性陈述。
具体实施方式
以下描述本发明的各种示意具体实施例。为了清楚说明,本专利说明书没有描述实际具体实作的所有特征。当然,应了解,在开发任一此类的实际具体实施例时,必需做许多与具体实作有关的决策以达成开发人员的特定目标,例如遵循与系统相关及商务有关的限制,这些都会随着每一个具体实作而有所不同。此外,应了解,此类开发既复杂又花时间但对本技艺一般技术人员而言,在阅读本揭示内容后仍将如例行工作一般。
此时以参照附图来描述本发明。示意图标于附图的各种结构、系统及装置仅供解释以及避免本领域技术人员所熟知的细节混淆本发明。尽管如此,仍纳入附图以描述及解释本揭示内容的示意实施例。应使用与相关技艺技术人员所熟悉的意思一致的方式理解及解释用于本文的字汇及词组。本文没有特别定义的术语或词组(亦即,与本领域技术人员所理解的普通惯用意思不同的定义)旨在用术语或词组的一致用法来说明。如果术语或词组旨在具有特定的意思时(亦即,不同于本领域技术人员所理解的意思),则会在本专利说明书中以直接明白地提供特定定义的方式清楚地陈述用于该术语或词组的特定定义。
本揭示内容大致有关于形成导电接触结构至半导体装置的各种新颖方法及所产生的新颖结构。揭示于本文的方法及装置使用各种技术可用来制造IC产品,例如NMOS、PMOS、CMOS等等,且可用来制造各种不同的产品,例如内存产品、逻辑产品、ASIC等等。本领域技术人员在读完本申请后应了解,揭示于本文的方法及装置可用于形成使用处于各种不同组构的晶体管装置的集成电路产品,例如平面装置、 FinFET装置等等。晶体管装置的栅极结构可用“栅极优先(gate first)”或者是“取代栅极(replacement gate)”制造技术。因此,揭示于本文的专利目标应不被视为受限于晶体管的任何特定形式或形成晶体管装置的栅极结构的方式。当然,揭示于本文的发明应不被视为受限于图示及描述于本文的例示实施例。此时参考附图,更详细地描述揭示于本文的方法及装置的各种例示具体实施例。
图3至图12图标形成导电接触结构至在集成电路(IC)产品100上的半导体装置的各种新颖方法及所产生的新颖结构。本领域技术人员在读完本申请后应了解,揭示于本文的新颖的接触蚀刻结构180可用来形成导电地耦合至建立于集成电路产品上的各种不同结构的各种不同导电接触结构。本申请特别讨论揭示于本文的新颖的栅极接触蚀刻结构180的两个例示实施例:单一扩散阻断(SDB)隔离结构142与栅极接触蚀刻椿(gate contactetching post)143。当然,揭示于本文的本发明应不被视为受限于这两个例示实施例。
图3的简化平面图图标IC产品100的一例示具体实施例。产品100 大体包含用于形成于半导体衬底102中及之上的各种晶体管装置的多个栅极106(以1至6编号以便参考)。在图示于此的例示实施例中,该晶体管装置为FinFET装置,但是揭示于本文的本发明应不被视为受限于包括FinFET晶体管装置的IC产品。多个鳍片103已使用传统制造技术形成于衬底102中,且已形成横过鳍片103的栅极106。也图示于该平面图的是导电地耦合至晶体管装置的源极/漏极区的例示源极/漏极接触结构120(例如,沟槽硅化物结构)。如以下所详述的,将通过3 号栅极来形成单一扩散阻断(SDB)。该平面图也图示(以虚线)将形成为可接触在将变成SDB隔离区者的相对两侧上的源极/漏极区的CA接触结构130。也图示于图3平面图的是(以虚线),将形成CB栅极接触结构132以接触4号及5号栅极的栅极结构108的位置。
图中也包括在按平面图所示处绘出的两个横截面图(“X-X”及“Y-Y”)。更特别的是,横截面图X-X是在将形成CA接触结构130的位置处沿着晶体管装置的栅极-长度方向穿过栅极106绘出。在晶体管装置为FinFET装置的情形下,视图X-X应理解为横截面图是沿着对应至FinFET装置的栅极长度(电流输送)方向的方向穿过晶体管的鳍片长轴绘出。横截面图Y-Y是在将形成CB栅极接触结构132的位置处沿着晶体管装置的栅极-长度方向穿过栅极106绘出。CB栅极接触结构132 位在隔离材料104的垂直上方。应注意,相关平面图没有反映图示于横截面图X-X及Y-Y的加工操作的所有方面以免使图形过于复杂且有助于更加了解揭示于本文的专利目标。
衬底102可具有各种组构,例如图示块硅组构。衬底102也可具有绝缘体上覆硅(SOI)组构,其包括块硅层、埋藏绝缘层及主动层,其中半导体装置形成于主动层中及之上。衬底102可由硅制成或可由除硅以外的材料制成。因此,应了解用语“衬底”或“半导体衬底”涵盖所有半导体材料及此类材料的所有形式。另外,附图未图示各种掺杂区,例如,晕圈植入区、井区及其类似者。
图3图示在执行数个制程操作之后的IC产品100。首先,如上述,形成鳍片103,以及形成在鳍片103之上的栅极106。在图示于此的例示实施例中,晶体管装置的栅极106包含使用传统取代栅极制造技术制成的栅极结构108。每个栅极106包括示意图标的最终栅极结构108、栅极帽盖110及侧壁间隔体112。侧壁间隔体112与栅极帽盖110可由各种不同材料构成,例如氮化硅、SiNC、SiN、SiCO及SiNOC等等,且可由相同或不同的材料制成。通常,栅极结构108的材料是依序形成于在移除牺牲栅极电极(未图示)后的间隔体112与牺牲栅极绝缘层(未图示)之间的栅极空腔中。栅极结构108通常包含高k栅极绝缘层(未图示),例如氧化铪,电介质常数大于10的材料等等,以及用作栅极结构108的栅极电极的一或更多导电材料层。例如,可沉积一或更多功函数调整金属层及块状导电材料以形成该栅极电极结构。
仍参考图3,在形成最终栅极结构108之前,通过执行外延成长制程,在主动区103(或在FinFET装置的情形下,为鳍片)的暴露部分上形成外延半导体材料116,亦即,在装置的源极/漏极区中。外延材料 116可形成至任何所欲厚度。不过,应了解,所有应用中不一定会形成外延材料116。附图没有图示其他的材料层,例如接触蚀刻止挡层及其类似者。也图示通常包括所谓“沟槽硅化物”(TS)结构(未单独图标) 的例示源极/漏极接触结构120。如图标,源极/漏极接触结构120的上表面通常与栅极帽盖110的上表面大约齐平。
在形成外延材料116后,毯覆沉积一层绝缘材料121(例如,二氧化硅)于衬底上。之后,使用位于牺牲栅极结构上方作为研磨止挡层 (polish stop layer)的原始栅极帽盖(未图示),执行CMP制程以平坦化该层绝缘材料121。这时,执行传统取代栅极制程以移除原始栅极帽盖及牺牲栅极结构而形成最终栅极结构108。这时,在产品100上形成栅极帽盖110。接下来,移除绝缘材料121高出源极/漏极区的部分且在装置的源极/漏极区中形成上述的源极/漏极接触结构120。
也图示于图3的是例示下栅极接触结构124,其经形成可建立通到 4号及5号栅极的栅极结构108的电气接触。图3的平面图未图标下栅极接触结构124。下栅极接触结构124的形成可通过形成在栅极帽盖 110之上的带图案蚀刻屏蔽层(未图示),其选择性地暴露出栅极帽盖 110用于4号及5号栅极的部分,在此将形成下栅极接触结构124。之后,执行蚀刻制程以移除栅极帽盖110的暴露部分以便暴露用于4号及5号栅极的栅极结构108的一部分。这时,移除该带图案蚀刻屏蔽且沉积一或更多导电材料以便接触栅极结构108的暴露部分。之后,使用栅极帽盖110与该层绝缘材料121作为研磨止挡层,执行CMP制程以移除多余导电材料。之后,毯覆沉积另一层绝缘材料122(例如,二氧化硅)于产品100上。若需要,在该层绝缘材料122的上表面上可执行视需要的CMP制程。应注意,图标于此的平面图不打算图示该层绝缘材料122或121以免使图形过于复杂。本领域技术人员在读完本申请后应了解,在一例示具体实施例中,该层绝缘材料122的厚度122X 大到足以顺应最终CA接触结构130(及CB接触结构132)的垂直高度以及形成用于产品100的金属化系统的第一或最下面金属线路层(例如, M0或M1)的垂直厚度。
图4图示在开口134及136形成于该层绝缘材料122中之后的IC 产品100。开口134及136的形成是通过在产品100之上形成带图案蚀刻屏蔽层(未图示),例如光阻剂、OPL等等,之后,通过该带图案蚀刻屏蔽层来执行一或更多蚀刻制程。图4图标在带图案屏蔽层已被移除之后的产品100。开口134的位置对应至将通过3号栅极的栅极结构 108来形成的SBD隔离区,以下会有更完整的描述。开口136的位置对应至将形成栅极接触蚀刻椿或柱,以及两个紧密间隔(密集包装)的栅极接触,以下会有更完整的描述。
图5图示在形成毯覆蚀刻屏蔽138(亦即,区块屏蔽)于产品100 之上后的产品100。如图示,蚀刻屏蔽138填满开口136但是让开口 134暴露供进一步加工操作。
图6图示在通过该层绝缘材料122的开口134来执行一或更多蚀刻制程以便在衬底102中界定沟槽140之后的产品100。如图示,这些蚀刻制程移除栅极帽盖110的一部分及3号栅极的实质所有栅极结构 108以及衬底102的数个部分。在这些蚀刻制程结束时,在衬底102 中界定沟槽140。沟槽140的深度可随着特定应用而有所不同,但是应形成够深的沟槽140致使形成于其中的绝缘材料可用作有效的SDB隔离区。
图7图示在执行数个制程操作之后的产品100。首先,移除蚀刻屏蔽138。之后,沉积绝缘材料,例如氮化硅、SiNC、SiN、SiCO及SiNOC 等等或SiN与SiO2的组合等等,以便过填(over-fill)开口134及136 而实质填满沟槽140。接下来,执行CMP或回蚀制程以移除位于该层绝缘材料122上表面之上多余数量的绝缘材料。这些制程操作导致形成在沟槽140中的SDB隔离结构142与在开口136中的开口134与栅极接触蚀刻椿或柱143。应注意,SDB隔离结构142与栅极接触蚀刻椿或柱143的上表面与该层绝缘材料122的上表面实质齐平。
图8图示在执行数个制程操作之后的产品100。首先,在产品100 之上形成带图案蚀刻屏蔽(未图示)。如图8的平面图所示,该带图案蚀刻屏蔽包含CA接触开口145与CB接触开口147。CA接触开口145 位于源极/漏极接触结构120在SDB隔离结构142的相对两侧的部分之上,在此将形成CA接触结构130。CA接触开口145也暴露SBD隔离结构142的一部分。CB接触开口147位在形成于4号及5号栅极上的下栅极接触结构124之上。CB接触开口147也暴露栅极接触蚀刻椿或柱 143。接下来,通过该带图案蚀刻屏蔽来执行一或更多蚀刻制程以对SDB 隔离结构142与栅极接触蚀刻椿或柱143选择性地移除绝缘材料122 的暴露部分。此蚀刻制程导致形成多个CA源极/漏极接触开口150A、 150B(参考视图X-X;全体用附图标记150表示)及多个CB栅极接触开口152A、152B(参考视图Y-Y;全体用附图标记152表示)。CA源极/漏极接触开口150暴露源极/漏极接触结构120在SDB隔离结构142的相对两侧的底下部分。CB栅极接触开口152暴露下栅极接触结构124 导电地耦合至4号及5号栅极的栅极结构108的部分。之后,移除该带图案蚀刻屏蔽。应注意,在有些应用中,可能不存在下栅极接触结构124。在此一情形下,CB栅极接触开口152会暴露出个别晶体管装置的导电栅极结构的数个部分。
应注意,由于存在有SDB隔离结构142,所以开口150的一边会自对准于SDB隔离结构142,亦即,开口150之间的间隔150X的建立是通过相对于SDB隔离结构142选择性蚀刻来实现,而不是简单地图案化该层绝缘材料122。相比于企图使用传统屏蔽及蚀刻制程直接图案化开口150而在该层绝缘材料122中简单地形成对应类型的开口150,用于界定间隔150X的此技术可提供更大的制程控制。同样,由于存在有栅极接触蚀刻椿或柱143,开口152的一边自对准于栅极接触蚀刻椿或柱143,亦即,开口152之间的间隔152X的建立是通过相对于栅极接触蚀刻椿或柱143选择性蚀刻来实现,而不是简单地图案化该层绝缘材料122。相比于企图使用传统屏蔽及蚀刻制程直接图案化开口152 而在该层绝缘材料122中简单地形成对应类型的开口152,界定间隔 152X的此技术可提供更大的制程控制。
图9图示在执行数个制程操作之后的产品100。首先,在产品之上形成带图案蚀刻屏蔽(未图示)以便在该层绝缘材料122中界定多条金属线路沟槽。如图9的平面图所示,该带图案蚀刻屏蔽包含至少连续有一段距离的第一矩形开口157,在此开口157横跨位在SDB隔离结构 142(可能是2、3及4号栅极)及第二连续大致矩形开口159的相对两侧的CA源极/漏极接触开口150。在图示实施例中,开口157位在2 至6号栅极之上,在位于SDB隔离结构142的相对两侧的CA源极/漏极接触开口150之上,且暴露出SDB隔离结构142的一部分。在图示实施例中,开口159位在1至6号的所有栅极之上,在CB接触开口152 之上,且暴露出栅极接触蚀刻椿或柱143。接下来,通过该带图案蚀刻屏蔽来执行一或更多蚀刻制程以对SDB隔离结构142与栅极接触蚀刻椿或柱143选择性地移除绝缘材料122的暴露部分。此蚀刻制程导致在SDB隔离结构142的相对两侧的开口157下面形成金属线路沟槽 154A及154B(全体用附图标记154表示),以及在在栅极接触蚀刻椿或柱143的相对两侧的开口159下面形成金属线路沟槽155A及155B(全体用附图标记155表示)。参考视图X-X,金属线路沟槽154A与暴露底下源极/漏极接触结构120的CA源极/漏极接触开口150A连通,同时金属线路沟槽154B与暴露底下源极/漏极接触结构120的CA源极/漏极接触开口150B连通。同样,参考视图Y-Y,金属线路沟槽155A与暴露在4号栅极上的底下下栅极接触结构124的CB栅极接触开口152A 连通,同时金属线路沟槽155B与暴露在5号栅极上的底下下栅极接触结构124的CB栅极接触开口152B连通。
继续参考图9,由于存在有SDB隔离结构142,所以每个沟槽154 的一边自对准于SDB隔离结构142,亦即,沟槽154A及154B之间的尖端对尖端间隔154X的建立是通过相对于SDB隔离结构142选择性蚀刻来实现,而不是简单地图案化该层绝缘材料122中的对应沟槽。相比于企图使用传统屏蔽及蚀刻制程直接图案化开口150而在该层绝缘材料122中简单地形成对应的个别沟槽154A、154B,用于界定间隔154X 的此技术可提供更大的制程控制。同样,由于存在有栅极接触蚀刻椿或柱143,所以每个沟槽155的一边自对准于栅极接触蚀刻椿或柱143,亦即,沟槽155A及155B之间的尖端对尖端间隔155X的建立是通过相对于栅极接触蚀刻椿或柱143选择性蚀刻来实现,而不是简单地图案化该层绝缘材料122。相比于企图使用传统屏蔽及蚀刻制程直接图案化独立沟槽155A、155B而在该层绝缘材料122中简单地形成对应的个别沟槽155A、155B,用于界定间隔155X的此技术可提供更大的制程控制。
图10图示在执行数个制程操作以形成CA接触130、CB接触132 及金属线路156、160之后的产品100。首先,形成一或更多共形阻障层(未单独图示)以便用阻障材料对开口150、152、154及155予以衬垫。接下来,毯覆沉积一层导电材料(例如铜、含金属材料、金属化合物等等)于产品100上以便过填开口150、152、154及155。这时,执行CMP制程以从该层绝缘材料122、SDB隔离结构142与栅极接触蚀刻椿或柱143的上表面移除导电材料的多余部分。这些制程操作导致形成开口150A中的CA接触130A、开口150B中的CA接触130B、开口152A 中的CB接触132A以及开口152B中的CB接触132B。这些制程操作也导致形成多个实体独立的金属线路156A、156B、160A及160B,这些金属线路是通过沉积及研磨来实现,而不是切割先前形成的连续金属线路。金属线路156A导电地耦合至CA接触130A,金属线路156B导电地耦合至CA接触130B,金属线路160A导电地耦合至CB接触132A,以及金属线路160B导电地耦合至CB接触130B。应注意,在一例示具体实施例中,金属线路156及160的上表面与SDB隔离结构142、栅极接触蚀刻椿或柱143及位在金属线路之间的绝缘材料122(绝缘材料122 未图示于横截面图)的上表面实质齐平或共平面。应注意,在揭示于本文的IC产品中,SDB隔离结构142明显高于先前技术的SDB隔离结构。亦即,相比于先前技术产品,SDB结构142的上表面所在的层级明显高于其他结构(例如栅极帽盖110)的上表面的层级。
本领域技术人员在读完本申请后应了解,揭示于本文的方法为装置设计者在制造集成电路产品时提供数个额外选项。例如,图11图示故意在沉积于沟槽140内的绝缘材料中形成气隙168的具体实施例。此一气隙168的形成可通过增加其电介质常数来增加SDB结构142的有效性。气隙168可通过控制绝缘材料的沉积来形成,使得在沟槽140 内有“夹止(pinch off)”且不会完全填满沟槽140。图12图示沟槽 140及在其上的开口可填满不同绝缘材料的另一具体实施例。例如,相比于用于SDB隔离结构142上半部的材料的k值,沟槽140的下半部可填满有相对较低k值的材料170(例如,有3.3或更小的k值的材料)。本领域技术人员在读完本申请后应了解,除揭示及描述于本文的例示实施例之外,SDB结构142与栅极接触蚀刻椿143只构成揭示于本文的新颖的接触蚀刻结构180的两个实施例,它们在各种情况中可用来形成导电接触结构。例如,在一具体实施例中,揭示于本文的方法可包括:形成第一及第二下导电结构(例如,源极/漏极接触结构120或下栅极接触结构124(若有的话)),以及形成由第一材料制成的一层绝缘材料(例如,层122)于第一及第二下导电结构之上。之后,该方法可包括:形成接触蚀刻结构180于该层绝缘材料中,其中接触蚀刻结构180 由与该第一材料不同的第二材料制成。也应注意,接触蚀刻结构180 的至少一部分横向位在第一下导电结构的至少一部分与第二下导电结构的至少一部分之间。在接触蚀刻结构180为SDB结构142的情形下,接触蚀刻结构180可位在源极/漏极接触结构120的整体之间(在装置的垂直方向与栅极宽度方向两者)。该方法也可包括:形成邻近接触蚀刻结构180的第一侧的第一导电线路及第一导电接触,其中该第一导电接触导电地耦合至该第一下导电结构。在接触蚀刻结构180为SDB 结构142的情形下,该第一导电接触可为导电地耦合至源极/漏极接触结构120的其中一者的CA接触。在接触蚀刻结构180为栅极接触蚀刻椿143的情形下,该第一导电接触可为导电地耦合至下栅极接触结构 124的其中一者(或栅极结构)的CB栅极接触。该方法也可包括:形成邻近该接触蚀刻结构的第二侧的第二导电线路及第二导电接触,该接触蚀刻结构的第二侧与该接触蚀刻结构的第一侧相反,其中该第二导电接触导电地耦合至该第二下导电结构,以及其中该第一及第二导电线路的间隔大约等于接触蚀刻结构180的尺寸。
参考图10,新颖的接触蚀刻结构180也呈现数个新颖结构。例如,在至少一些应用中,该第一导电线路(例如,线路156A或160A)的至少一部分可位在接触蚀刻结构180的第一侧上且与其接触,同时该第二导电线路(例如,线路156B或160B)的至少一部分位在接触蚀刻结构 180的第二侧上且与其接触。也应注意,接触蚀刻结构180可具有取决于特定应用而有所不同的垂直高度180A。在一实施例中,垂直高度180A 可大于该层绝缘材料122的厚度122X。也应注意,在有些情形下,可形成该第一导电线路、该第二导电线路及接触蚀刻结构180,使得该第一导电线路的上表面181、该第二导电线路的上表面182以及接触蚀刻结构180的上表面183全都大约位于在半导体衬底之上的相同第一层级。甚至在其他情况中,该层绝缘材料122的上表面184位在第一层级。如视图X-X所示,在有些应用中,接触蚀刻结构180可延伸进入形成于半导体衬底102中的沟槽140。参考视图Y-Y,在有些应用中,接触蚀刻结构180的一部分可位在第一及第二下导电结构(例如,下栅极接触结构124)中的各者的表面上且与其接触。仍参考视图Y-Y,在其他的应用中,接触蚀刻结构180的底面180B可位于在第一及第二下导电结构之间的一层绝缘材料121上且与其接触。当然,在审查完本申请后,本领域技术人员会明白,除以上所提及的以外,仍有更独特的结构及方法。
以上所揭示的特定具体实施例均仅供图解说明,因为本领域技术人员在受益于本文的教导后显然可以不同但等价的方式来修改及实施本发明。例如,可用不同的顺序完成以上所提出的制程步骤。此外,除非在以下权利要求书有提及,否则不希望本发明受限于本文所示的构造或设计的细节。因此,显然可改变或修改以上所揭示的特定具体实施例,而所有此类变体都被视为仍在本发明的范畴与精神内。应注意,在本专利说明书及随附权利要求书中为了描述各种制程或结构而使用的例如“第一”、“第二”、“第三”或“第四”用语只是用来作为该步骤/结构的简写参考,不一定暗示是以该顺序执行/形成该步骤/结构。当然,取决于确切的权利要求语言,可能需要或不需要该制程的顺序。因此,本文提出以随附的权利要求书寻求保护。

Claims (24)

1.一种方法,包含:
形成第一下导电结构及第二下导电结构;
在该第一下导电结构及该第二下导电结构之上形成包含第一材料的一层绝缘材料;
在该层绝缘材料中形成接触蚀刻结构,其中,该接触蚀刻结构包含与该第一材料不同的第二材料,且其中,该接触蚀刻结构的至少一部分横向位在该第一下导电结构的至少一部分与该第二下导电结构的至少一部分之间;
形成邻近该接触蚀刻结构的第一侧的第一导电线路及第一导电接触,其中,该第一导电接触导电地耦合至该第一下导电结构;以及
形成邻近该接触蚀刻结构的第二侧的第二导电线路及第二导电接触,该接触蚀刻结构的该第二侧与该接触蚀刻结构的该第一侧相反,其中,该第二导电接触导电地耦合至该第二下导电结构,且其中,该第一导电线路与该第二导电线路之间的间隔大约等于该接触蚀刻结构的尺寸。
2.如权利要求1所述的方法,其中,该第一导电线路的至少一部分位在该接触蚀刻结构的该第一侧上且与该接触蚀刻结构的该第一侧接触,以及该第二导电线路的至少一部分位在该接触蚀刻结构的该第二侧上且与该接触蚀刻结构的该第二侧接触。
3.如权利要求1所述的方法,其中,该接触蚀刻结构具有大于该层绝缘材料的厚度的垂直高度。
4.如权利要求1所述的方法,其中,该第一导电线路的一边与该第二导电线路的一边各自自对准于该接触蚀刻结构。
5.如权利要求1所述的方法,其中,形成该第一导电线路、该第二导电线路及该接触蚀刻结构,使得该第一导电线路的上表面、该第二导电线路的上表面及该接触蚀刻结构的上表面全都大约位于在半导体衬底之上的相同第一层级。
6.如权利要求5所述的方法,其中,该层绝缘材料具有位在该第一层级的上表面。
7.如权利要求1所述的方法,其中,该接触蚀刻结构的一部分延伸进入形成于半导体衬底中的沟槽。
8.如权利要求1所述的方法,其中,该接触蚀刻结构位在该第一下导电结构的整体与该第二下导电结构的整体之间。
9.如权利要求1所述的方法,其中,该接触蚀刻结构为通过集成电路产品的第一栅极来形成的单一扩散阻断(SDB)结构,该第一导电接触为导电地耦合至邻近该SDB结构的第一侧的第一源极/漏极区的第一源极/漏极接触,以及该第二导电接触为导电地耦合至邻近该SDB结构的第二侧的第二源极/漏极区的第二源极/漏极接触。
10.如权利要求9所述的方法,其中,该第一源极/漏极区用于第一晶体管且该第二源极/漏极区用于与该第一晶体管不同的第二晶体管。
11.如权利要求1所述的方法,其中,该接触蚀刻结构的一部分位在该第一下导电结构及该第二下导电结构中的各者的表面上且与该表面接触。
12.如权利要求1所述的方法,其中,该接触蚀刻结构的底面位于在该第一下导电结构及该第二下导电结构之间的第二层绝缘材料上且与该第二层绝缘材料接触。
13.如权利要求1所述的方法,其中,该接触蚀刻结构为栅极接触蚀刻椿,该第一导电接触为导电地耦合至第一栅极的栅极结构的第一下栅极接触结构的第一栅极接触,以及该第二导电接触为导电地耦合至第二栅极的栅极结构的第二下栅极接触结构的第二栅极接触。
14.一种方法,包含:
通过集成电路产品的第一栅极来形成单一扩散阻断(SDB)结构;以及
形成第一导电线路及第一导电源极/漏极接触于该SDB结构的第一侧上且形成第二导电线路及第二导电源极/漏极接触于该SDB结构的第二侧上,该第二侧与该第一侧相反,其中,该第一导电源极/漏极接触导电地耦合至位在该SDB结构的该第一侧上的第一源极/漏极区,以及该第二导电源极/漏极接触导电地耦合至位在该SDB结构的该第二侧上的第二源极/漏极区,其中,该第一导电线路及该第二导电线路的尖端对尖端间隔大约等于该SDB结构的尺寸。
15.如权利要求14所述的方法,其中,该第一导电线路的一边与该第二导电线路的一边各自自对准于该SDB结构。
16.如权利要求14所述的方法,其中,形成该第一导电线路、该第二导电线路及该SDB结构,使得该第一导电线路的上表面、该第二导电线路的上表面及该SDB结构的上表面全都大约位于在半导体衬底之上的相同第一层级。
17.如权利要求16所述的方法,其中,该方法进一步包含:在该半导体衬底之上形成一层绝缘材料,其中,该层绝缘材料具有位在该第一层级的上表面。
18.如权利要求16所述的方法,其中,该SDB结构的一部分延伸进入形成于该半导体衬底中的沟槽。
19.如权利要求18所述的方法,其中,该SDB结构包含第一材料,以及该层绝缘材料包含与该第一材料不同的第二材料。
20.如权利要求14所述的方法,其中,该方法进一步包含:
形成一第一下栅极接触结构及第二下栅极接触结构,两者各自通到第二栅极及第三栅极中的各者的栅极结构;
在该第二栅极及该第三栅极之上形成一层绝缘材料;
在该层绝缘材料中形成栅极接触蚀刻椿;以及
形成第三导电线路及第一栅极接触于该栅极接触蚀刻椿的第一侧上,以及形成第四导电线路及第二栅极接触于该栅极接触蚀刻椿的第二侧上,该栅极接触蚀刻椿的该第二侧与该栅极接触蚀刻椿的该第一侧相反,其中,该第一栅极接触导电地耦合至位在该栅极接触蚀刻椿的该第一侧上的该第一下栅极接触结构,且该第二栅极接触导电地耦合至位在该栅极接触蚀刻椿的该第二侧上的该第二下栅极接触结构,其中,该第三导电线路与该第四导电线路之间的尖端对尖端间隔大约等于该栅极接触蚀刻椿的尺寸。
21.一种方法,包含:
形成第一下栅极接触结构及第二下栅极接触结构,两者各自通到第一栅极及第二栅极中的各者的栅极结构;
在该第一及该第二栅极之上形成一层绝缘材料;
在该层绝缘材料中形成栅极接触蚀刻椿;以及
形成第一导电线路及第一栅极接触于该栅极接触蚀刻椿的第一侧上,以及形成第二导电线路及第二栅极接触于该栅极接触蚀刻椿的第二侧上,该栅极接触蚀刻椿的该第二侧与该栅极接触蚀刻椿的该第一侧相反,其中,该第一栅极接触导电地耦合至位在该栅极接触蚀刻椿的该第一侧上的该第一下栅极接触结构,以及该第二栅极接触导电地耦合至位在该栅极接触蚀刻椿的该第二侧上的该第二下栅极接触结构,其中,该第一导电线路与该第二导电线路之间的尖端对尖端间隔大约等于该栅极接触蚀刻椿的尺寸。
22.如权利要求21所述的方法,其中,该栅极接触蚀刻椿包含第一材料,且该层绝缘材料包含与该第一材料不同的第二材料。
23.如权利要求21所述的方法,其中,该第一导电线路的一边与该第二导电线路的一边各自自对准于该栅极接触蚀刻椿。
24.如权利要求21所述的方法,其中,形成该第一导电线路、该第二导电线路、该栅极接触蚀刻椿及该层绝缘材料,使得该第一导电线路的上表面、该第二导电线路的上表面、该栅极接触蚀刻椿的上表面及该层绝缘材料的上表面全都大约位于在半导体衬底之上的相同第一层级。
CN201811113696.3A 2017-10-10 2018-09-25 形成导电接触结构至半导体装置的方法及所产生的结构 Active CN109659274B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/728,632 US10290544B2 (en) 2017-10-10 2017-10-10 Methods of forming conductive contact structures to semiconductor devices and the resulting structures
US15/728,632 2017-10-10

Publications (2)

Publication Number Publication Date
CN109659274A true CN109659274A (zh) 2019-04-19
CN109659274B CN109659274B (zh) 2023-08-08

Family

ID=65994066

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811113696.3A Active CN109659274B (zh) 2017-10-10 2018-09-25 形成导电接触结构至半导体装置的方法及所产生的结构

Country Status (3)

Country Link
US (1) US10290544B2 (zh)
CN (1) CN109659274B (zh)
TW (1) TWI688020B (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111640752A (zh) * 2020-01-21 2020-09-08 福建省晋华集成电路有限公司 存储器及其形成方法
CN113497144A (zh) * 2020-04-01 2021-10-12 中芯国际集成电路制造(上海)有限公司 半导体结构及半导体结构的形成方法
CN113497143A (zh) * 2020-04-01 2021-10-12 中芯国际集成电路制造(上海)有限公司 半导体结构及半导体结构的形成方法

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102018127143A1 (de) * 2017-11-30 2019-06-06 Intel Corporation Plugs für verbindungsleitungen für die herstellung einer fortschrittlichen integrierten schaltungsstruktur
EP3718142A4 (en) * 2017-11-30 2021-09-22 Intel Corporation STRUCTURING RIBS FOR THE PRODUCTION OF AN INTEGRATED CIRCUIT
US10559470B2 (en) * 2018-01-22 2020-02-11 Globalfoundries Inc. Capping structure
US10580685B2 (en) * 2018-07-27 2020-03-03 Globalfoundries Inc. Integrated single diffusion break
KR102492304B1 (ko) 2018-10-01 2023-01-27 삼성전자주식회사 반도체 소자
JP2021044399A (ja) * 2019-09-11 2021-03-18 キオクシア株式会社 半導体装置およびその製造方法
US11158536B2 (en) * 2020-01-07 2021-10-26 International Business Machines Corporation Patterning line cuts before line patterning using sacrificial fill material
US11404323B2 (en) * 2020-04-29 2022-08-02 Taiwan Semiconductor Manufacturing Co., Ltd. Formation of hybrid isolation regions through recess and re-deposition
DE102020119859A1 (de) 2020-04-29 2021-11-04 Taiwan Semiconductor Manufacturing Co., Ltd. Bildung von hybrid-isolationsregionen durch aussparen und erneutes abscheiden
US20220293517A1 (en) * 2021-03-10 2022-09-15 Intel Corporation Stacked vias with bottom portions formed using selective growth
TWI834355B (zh) * 2021-10-26 2024-03-01 鈺創科技股份有限公司 具有直接連接到閘極、汲極和源極的金屬互連的電晶體結構

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5602423A (en) * 1994-11-01 1997-02-11 Texas Instruments Incorporated Damascene conductors with embedded pillars
US20020187606A1 (en) * 2000-06-16 2002-12-12 Drynan John M. Interconnect line selectively isolated from an underlying contact plug
US20040130035A1 (en) * 2003-01-07 2004-07-08 Zhen-Cheng Wu Method of forming copper interconnects
JP2007142468A (ja) * 2001-02-06 2007-06-07 Toshiba Corp 半導体装置
US20150380302A1 (en) * 2014-06-30 2015-12-31 Lam Research Corporation Selective formation of dielectric barriers for metal interconnects in semiconductor devices
US9412616B1 (en) * 2015-11-16 2016-08-09 Globalfoundries Inc. Methods of forming single and double diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products
US9490317B1 (en) * 2015-05-14 2016-11-08 Globalfoundries Inc. Gate contact structure having gate contact layer
US9570442B1 (en) * 2016-04-20 2017-02-14 Qualcomm Incorporated Applying channel stress to Fin field-effect transistors (FETs) (FinFETs) using a self-aligned single diffusion break (SDB) isolation structure
US20170287787A1 (en) * 2015-04-09 2017-10-05 Samsung Electronics Co., Ltd. Method for designing layout of semiconductor device and method for manufacturing semiconductor device using the same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6303488B1 (en) 1997-02-12 2001-10-16 Micron Technology, Inc. Semiconductor processing methods of forming openings to devices and substrates, exposing material from which photoresist cannot be substantially selectively removed
FR2911432A1 (fr) 2007-01-11 2008-07-18 Stmicroelectronics Crolles Sas Interconnexions d'un circuit electronique integre
CN102024744B (zh) 2009-09-16 2013-02-06 中国科学院微电子研究所 半导体器件及其制造方法
CN102376630B (zh) 2010-08-20 2013-08-14 中国科学院微电子研究所 半导体器件及其局部互连结构的制造方法
CN102468221B (zh) 2010-11-11 2014-10-22 中国科学院微电子研究所 采用后栅工艺制备cmos器件中接触孔的方法
DE102011002769B4 (de) 2011-01-17 2013-03-21 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Halbleiterbauelement und Verfahren zur Herstellung einer Hybridkontaktstruktur mit Kontakten mit kleinem Aspektverhältnis in einem Halbleiterbauelement
US9553028B2 (en) 2014-03-19 2017-01-24 Globalfoundries Inc. Methods of forming reduced resistance local interconnect structures and the resulting devices
US9984932B1 (en) * 2016-11-08 2018-05-29 Globalfoundries Inc. Semiconductor fin loop for use with diffusion break
US9935104B1 (en) * 2017-05-08 2018-04-03 Globalfoundries Inc. Fin-type field effect transistors with single-diffusion breaks and method

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5602423A (en) * 1994-11-01 1997-02-11 Texas Instruments Incorporated Damascene conductors with embedded pillars
US20020187606A1 (en) * 2000-06-16 2002-12-12 Drynan John M. Interconnect line selectively isolated from an underlying contact plug
JP2007142468A (ja) * 2001-02-06 2007-06-07 Toshiba Corp 半導体装置
US20040130035A1 (en) * 2003-01-07 2004-07-08 Zhen-Cheng Wu Method of forming copper interconnects
US20150380302A1 (en) * 2014-06-30 2015-12-31 Lam Research Corporation Selective formation of dielectric barriers for metal interconnects in semiconductor devices
US20170287787A1 (en) * 2015-04-09 2017-10-05 Samsung Electronics Co., Ltd. Method for designing layout of semiconductor device and method for manufacturing semiconductor device using the same
US9490317B1 (en) * 2015-05-14 2016-11-08 Globalfoundries Inc. Gate contact structure having gate contact layer
US9412616B1 (en) * 2015-11-16 2016-08-09 Globalfoundries Inc. Methods of forming single and double diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products
US20170141211A1 (en) * 2015-11-16 2017-05-18 Globalfoundries Inc. Single and double diffusion breaks on integrated circuit products comprised of finfet devices
US9570442B1 (en) * 2016-04-20 2017-02-14 Qualcomm Incorporated Applying channel stress to Fin field-effect transistors (FETs) (FinFETs) using a self-aligned single diffusion break (SDB) isolation structure

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111640752A (zh) * 2020-01-21 2020-09-08 福建省晋华集成电路有限公司 存储器及其形成方法
CN111640752B (zh) * 2020-01-21 2021-12-17 福建省晋华集成电路有限公司 存储器及其形成方法
CN113497144A (zh) * 2020-04-01 2021-10-12 中芯国际集成电路制造(上海)有限公司 半导体结构及半导体结构的形成方法
CN113497143A (zh) * 2020-04-01 2021-10-12 中芯国际集成电路制造(上海)有限公司 半导体结构及半导体结构的形成方法

Also Published As

Publication number Publication date
TW201916195A (zh) 2019-04-16
CN109659274B (zh) 2023-08-08
US10290544B2 (en) 2019-05-14
US20190109045A1 (en) 2019-04-11
TWI688020B (zh) 2020-03-11

Similar Documents

Publication Publication Date Title
CN109659274A (zh) 形成导电接触结构至半导体装置的方法及所产生的结构
US11444082B2 (en) Semiconductor apparatus having stacked gates and method of manufacture thereof
KR102346409B1 (ko) 3차원 메모리 장치의 쓰루 어레이 컨택 구조
TWI707459B (zh) 用於形成三維記憶體元件的方法
CN109698166B (zh) 形成晶体管装置的栅极接触结构、交叉耦合接触结构的方法
TWI670762B (zh) 形成相鄰電晶體之閘極之氣隙及在電晶體之主動區上面之閘極接觸的方法
CN110121778B (zh) 三维存储器件
US9553028B2 (en) Methods of forming reduced resistance local interconnect structures and the resulting devices
KR20200121811A (ko) 3차원 소자 및 이를 형성하는 방법
CN107689342A (zh) 在形成半导体装置后形成衬底穿孔(tsv)及金属化层的方法
KR20180052169A (ko) 반도체 소자
US20190096677A1 (en) Methods of forming a gate contact structure for a transistor
CN109326597B (zh) 使用栅极绝缘破裂的一次性可编程存储器
US11342261B2 (en) Integrated circuit with an interconnection system having a multilevel layer providing multilevel routing tracks and method of manufacturing the same
CN109300780A (zh) 形成栅极接触点的导电间隔物的方法以及所得装置
CN102789972A (zh) 半导体器件的制造方法
US11677401B2 (en) 3D integrated count
CN106611712B (zh) 半导体结构及其形成方法
TW201714249A (zh) 具有鏡像落著區之多層三維結構
KR101925685B1 (ko) 반도체 디바이스 및 그 제조 방법
WO2021243686A1 (en) Contact pad structure and method of forming the same
US20240215238A1 (en) Three-dimensional nand memory device and method of forming the same
US20220102380A1 (en) Connections from buried interconnects to device terminals in multiple stacked devices structures
KR20120111375A (ko) 3차원 반도체 기억 소자 및 그 제조 방법
US20240215236A1 (en) Three-dimensional nand memory device and method of forming the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right
TA01 Transfer of patent application right

Effective date of registration: 20210226

Address after: California, USA

Applicant after: Lattice chip (USA) integrated circuit technology Co.,Ltd.

Address before: Greater Cayman Islands, British Cayman Islands

Applicant before: GLOBALFOUNDRIES INC.

GR01 Patent grant
GR01 Patent grant