CN109616511A - 一种纵向多重pn结的vdmos分压环的设计方法 - Google Patents
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Abstract
本发明提供了一种纵向多重PN结的VDMOS分压环的设计方法,包括以下工艺流程:N型衬底片准备;Zero光刻、刻蚀形成光刻标记;BP光刻、BP注入,注入硼,去胶后做BP高温推阱,形成深BP阱;薄N型EPI生长;NW高能普注,注入磷;Pw光刻,Pw注入,注入硼;去胶后做推阱,并用LOCOS的方式形成FOX区域;Ptop光刻,Ptop注入,注入硼;去胶后做短时间的推阱,然后做N+光刻注入,P+光刻注入,其中Ptop、PW、BP均为P型区域;ILD沉积,孔刻蚀,Metal沉积,Metal光刻刻蚀;实现了VDMOS终端纵向PNPN,Ptop/NW/BP/Nepi多层结构;如果不做Ptop光刻注入,那么就是实现了VDMOS终端纵向NPN,NW/BP/Nepi多层结构。
Description
技术领域
本发明涉及半导体功率器件领域,尤其涉及一种纵向多重PN结的VDMOS分压环的设计方法。
背景技术
VDMOS是80年代以来发展迅猛的一种半导体功率器件,其在高压大电流领域的贡献非常大。VDMOS的设计主要分两个部分,一个是元胞区域,一个是边缘分压环区域。元胞区域主要是电流通路,在VDMOS的漏极加高压时,元胞区域的PN结耗尽区近似为平行平面结,耐压比较高,若边缘不做任何处理,由于边缘元胞处平面结的曲率效应,会使击穿电压降低,所以器件还需要有终端结构。
现有终端技术有很多,主要可归纳分类为场限环(FLR)、场板(FP)、结终端扩展(JTE)等,其中面积比较小的是JTE技术,是一个单独大PN结终端,但是此技术需要Pring距离截止环N+保持一定距离,即此技术的面积不是最优化的。本专利设计一种新型的纵向复合PN结结构的终端,可以实现更小的终端面积。
发明内容
本发明的目的在于针对上述现有技术的不足,提供了一种纵向多重PN结的VDMOS分压环的设计方法,在耐压跟传统结构保持一致的条件下,实现更小的终端面积,进而降低成本
为实现上述目的,本发明采用了如下技术方案:
本发明提供了一种纵向多重PN结的VDMOS分压环的设计方法,其特征在于,包括以下工艺流程:
1)衬底片准备;根据不同的耐压等级选择不同的N型电阻率,接着做Zero光刻、刻蚀,Zero仅用于后续的光刻对准,然后做BP光刻,BP注入注入硼;
2)去胶后做BP高温推阱,形成深BP阱;
3)薄N型EPI生长;
4)NW高能普注,注入磷;
5)Pw光刻,Pw注入,注入硼;
6)去胶后做推阱,并用LOCOS的方式形成FOX区域;
7)Ptop光刻,Ptop注入,注入硼;
8)去胶后做短时间的推阱,然后做N+光刻注入,P+光刻注入,其中Ptop、PW、BP均为P型区域;
9)ILD沉积,孔刻蚀,Metal沉积,Metal光刻刻蚀。
进一步,所述步骤2)中,温度为1150℃,时间为300mins。
进一步,步骤3)中,所述生长厚度为4um~5.0um。
进一步,所述步骤4)中,能量为300kev~360kev,剂量为0.8E12~1.2E12。
进一步,所述步骤5)中,能量为80Kev,剂量为0.5E13~1.5E13。
进一步,所述步骤7)中,能量180Kev,剂量2.9E12。
进一步,所述NW位于所述BP上部。
进一步,所述Ptop位于所述NW上部。
进一步,所述Ptop跟所述BP通过所述PW连接。
进一步,所述NW位于所述Ptop与所述BP中间并与所述PW平行。
本发明的有益效果为:设计方法,优化VDMOS终端结构,在相同耐压下可以实现更小的终端长度。因为主结P型区域BP,可以受到原衬底Nepi耗尽,还能受到顶部NW的辅助耗尽,当BP完全耗尽后实现耐高压。原传统结构主结P型区域Pring,可以受到衬底Nepi耗尽,还需要横向NW耗尽,当Pring完全耗尽后实现耐高压,但是由于有横向NW,使得终端长度比较长;
1)VDMOS终端纵向PNPN,Ptop/NW/BP/Nepi多层结构;
2)如果不做Ptop光刻注入,那么就是实现了VDMOS终端纵向NPN,NW/BP/Nepi多层结构。
附图说明
图1为本发明现有技术的结构示意图;
图2为本发明步骤1)的结构示意图;
图3为本发明步骤2)的结构示意图;
图4为本发明步骤3)的结构示意图;
图5为本发明步骤4)的结构示意图;
图6为本发明步骤5)的结构示意图;
图7为本发明步骤6)的结构示意图;
图8为本发明步骤7)的结构示意图;
图9为本发明步骤8)的结构示意图;
图10为本发明的一种纵向多重PN结的VDMOS分压环的结构示意图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白,下面结合附图,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅用以解释本发明,并不用于限定本发明。
请参阅图10,一种纵向多重PN结的VDMOS分压环的设计方法,包括以下步骤:
1)请参阅图2,衬底片准备;VDMOS的衬底片为N型掺磷epi1硅衬底,根据不同的耐压等级需求选择不同的N型电阻率。然后做Zero光刻、刻蚀,Zero仅用于后续的光刻对准,然后做BP光刻,BP1注入BP注入硼。
2)如图3所示,去胶后做BP1高温推阱,温度1150℃,时间300mins,形成深BP阱;
3)如图4,薄N型EPI4生长,厚度为为4um~5.0um。
其中,厚度太厚或者太薄都不能很好的形成所谓的Resurf结构。
4)如图5,NW5高能普注,注入磷,能量为300kev~360kev,,剂量为0.8E12~1.2E12;
其中,能量越高,注入深度越深,体内浓度越均匀,330Kev是常见的高能注入能量。
1.0E12是中心剂量,剂量越高,耐压越低,剂量越低,越不容易辅助BP耗尽。
5)如图6,Pw光刻,Pw6注入,注入硼,能量为80Kev,剂量为0.5E13~1.5E13;
6)如图7,去胶后做推阱,并用LOCOS的方式形成FOX区域7;
7)如图8,Ptop光刻,Ptop8注入,注入硼,能量180Kev,剂量2.9E12;
8)如图9,去胶后做短时间的推阱,然后做N+9光刻注入,P+10光刻注入,因为Ptop8、PW6、BP1均为P型区域;
9)如图10,ILD12沉积,孔刻蚀,Metal11沉积,Metal11光刻刻蚀。
所述NW5位于所述BP1上部。
所述Ptop8位于所述NW5上部。
所述Ptop8跟所述BP1通过所述PW6连接。
所述NW5位于所述Ptop8与所述跟BP1中间并与所述PW6平行。
以上所述实施例仅表达了本发明的实施方式,其描述较为具体和详细,但并不能因此而理解为对本发明专利范围的限制。应当指出的是,对于本领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干变形和改进,这些都属于本发明的保护范围。因此,本发明专利的保护范围应以所附权利要求为准。
Claims (10)
1.一种纵向多重PN结的VDMOS分压环的设计方法,其特征在于,包括以下工艺流程:
1)衬底片准备;根据不同的耐压等级选择不同的N型电阻率,接着做Zero光刻、刻蚀,Zero仅用于后续的光刻对准,然后做BP光刻,BP注入硼
2)去胶后做BP高温推阱,形成深BP阱;
3)薄N型EPI生长;
4)NW高能普注,注入磷;
5)Pw光刻,Pw注入,注入硼;
6)去胶后做推阱,并用LOCOS的方式形成FOX区域;
7)Ptop光刻,Ptop注入,注入硼;
8)去胶后做短时间的推阱,然后做N+光刻注入,P+光刻注入,其中,Ptop、PW、BP均为P型区域;
9)ILD沉积,孔刻蚀,Metal沉积,Metal光刻刻蚀。
2.根据权利要求1所述的一种纵向多重PN结的VDMOS分压环的设计方法,其特征在于:所述步骤2)中,温度为1150℃,时间为300mins。
3.根据权利要求1所述的一种纵向多重PN结的VDMOS分压环的设计方法,其特征在于:步骤3)中,所述生长厚度为4um~5.0um。。
4.根据权利要求1所述的一种纵向多重PN结的VDMOS分压环的设计方法,其特征在于:所述步骤4)中,能量为300kev~360kev,剂量为0.8E12~1.2E12。
5.根据权利要求1所述的一种纵向多重PN结的VDMOS分压环的设计方法,其特征在于:所述步骤5)中,能量为80Kev,剂量为0.5E13~1.5E13。
6.根据权利要求1所述的一种纵向多重PN结的VDMOS分压环的设计方法,其特征在于:所述步骤7)中,能量180Kev,剂量2.9E12。
7.根据权利要求1所述的一种纵向多重PN结的VDMOS分压环的设计方法,其特征在于:所述NW位于所述BP上部。
8.根据权利要求1所述的一种纵向多重PN结的VDMOS分压环的设计方法,其特征在于:所述Ptop位于所述NW上部。
9.根据权利要求1所述的一种纵向多重PN结的VDMOS分压环的设计方法,其特征在于:所述Ptop跟所述BP通过所述PW连接。
10.根据权利要求1所述的一种纵向多重PN结的VDMOS分压环的设计方法,其特征在于:所述NW位于所述Ptop与所述BP中间并与所述PW平行。
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