CN109616511A - 一种纵向多重pn结的vdmos分压环的设计方法 - Google Patents

一种纵向多重pn结的vdmos分压环的设计方法 Download PDF

Info

Publication number
CN109616511A
CN109616511A CN201811550606.7A CN201811550606A CN109616511A CN 109616511 A CN109616511 A CN 109616511A CN 201811550606 A CN201811550606 A CN 201811550606A CN 109616511 A CN109616511 A CN 109616511A
Authority
CN
China
Prior art keywords
vdmos
photoetching
longitudinal direction
junction
ptop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201811550606.7A
Other languages
English (en)
Other versions
CN109616511B (zh
Inventor
杜蕾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Vergiga Semiconductor Co Ltd
Original Assignee
Shenzhen Wei Wei Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Wei Wei Semiconductor Co Ltd filed Critical Shenzhen Wei Wei Semiconductor Co Ltd
Priority to CN201811550606.7A priority Critical patent/CN109616511B/zh
Publication of CN109616511A publication Critical patent/CN109616511A/zh
Application granted granted Critical
Publication of CN109616511B publication Critical patent/CN109616511B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本发明提供了一种纵向多重PN结的VDMOS分压环的设计方法，包括以下工艺流程：N型衬底片准备；Zero光刻、刻蚀形成光刻标记；BP光刻、BP注入，注入硼，去胶后做BP高温推阱，形成深BP阱；薄N型EPI生长；NW高能普注，注入磷；Pw光刻，Pw注入，注入硼；去胶后做推阱，并用LOCOS的方式形成FOX区域；Ptop光刻，Ptop注入，注入硼；去胶后做短时间的推阱，然后做N+光刻注入，P+光刻注入，其中Ptop、PW、BP均为P型区域；ILD沉积，孔刻蚀，Metal沉积，Metal光刻刻蚀；实现了VDMOS终端纵向PNPN，Ptop/NW/BP/Nepi多层结构；如果不做Ptop光刻注入，那么就是实现了VDMOS终端纵向NPN，NW/BP/Nepi多层结构。

Description

一种纵向多重PN结的VDMOS分压环的设计方法
技术领域
本发明涉及半导体功率器件领域，尤其涉及一种纵向多重PN结的VDMOS分压环的设计方法。
背景技术
VDMOS是80年代以来发展迅猛的一种半导体功率器件，其在高压大电流领域的贡献非常大。VDMOS的设计主要分两个部分，一个是元胞区域，一个是边缘分压环区域。元胞区域主要是电流通路，在VDMOS的漏极加高压时，元胞区域的PN结耗尽区近似为平行平面结，耐压比较高，若边缘不做任何处理，由于边缘元胞处平面结的曲率效应，会使击穿电压降低，所以器件还需要有终端结构。
现有终端技术有很多，主要可归纳分类为场限环(FLR)、场板(FP)、结终端扩展(JTE)等，其中面积比较小的是JTE技术，是一个单独大PN结终端，但是此技术需要Pring距离截止环N+保持一定距离，即此技术的面积不是最优化的。本专利设计一种新型的纵向复合PN结结构的终端，可以实现更小的终端面积。
发明内容
本发明的目的在于针对上述现有技术的不足，提供了一种纵向多重PN结的VDMOS分压环的设计方法，在耐压跟传统结构保持一致的条件下，实现更小的终端面积，进而降低成本
为实现上述目的，本发明采用了如下技术方案：
本发明提供了一种纵向多重PN结的VDMOS分压环的设计方法，其特征在于，包括以下工艺流程：
1)衬底片准备；根据不同的耐压等级选择不同的N型电阻率，接着做Zero光刻、刻蚀，Zero仅用于后续的光刻对准，然后做BP光刻，BP注入注入硼；
2)去胶后做BP高温推阱，形成深BP阱；
3)薄N型EPI生长；
4)NW高能普注，注入磷；
5)Pw光刻，Pw注入，注入硼；
6)去胶后做推阱，并用LOCOS的方式形成FOX区域；
7)Ptop光刻，Ptop注入，注入硼；
8)去胶后做短时间的推阱，然后做N+光刻注入，P+光刻注入，其中Ptop、PW、BP均为P型区域；
9)ILD沉积，孔刻蚀，Metal沉积，Metal光刻刻蚀。
进一步，所述步骤2)中，温度为1150℃，时间为300mins。
进一步，步骤3)中，所述生长厚度为4um～5.0um。
进一步，所述步骤4)中，能量为300kev～360kev，剂量为0.8E12～1.2E12。
进一步，所述步骤5)中，能量为80Kev，剂量为0.5E13～1.5E13。
进一步，所述步骤7)中，能量180Kev，剂量2.9E12。
进一步，所述NW位于所述BP上部。
进一步，所述Ptop位于所述NW上部。
进一步，所述Ptop跟所述BP通过所述PW连接。
进一步，所述NW位于所述Ptop与所述BP中间并与所述PW平行。
本发明的有益效果为：设计方法，优化VDMOS终端结构，在相同耐压下可以实现更小的终端长度。因为主结P型区域BP，可以受到原衬底Nepi耗尽，还能受到顶部NW的辅助耗尽，当BP完全耗尽后实现耐高压。原传统结构主结P型区域Pring，可以受到衬底Nepi耗尽，还需要横向NW耗尽，当Pring完全耗尽后实现耐高压，但是由于有横向NW，使得终端长度比较长；
1)VDMOS终端纵向PNPN，Ptop/NW/BP/Nepi多层结构；
2)如果不做Ptop光刻注入，那么就是实现了VDMOS终端纵向NPN，NW/BP/Nepi多层结构。
附图说明
图1为本发明现有技术的结构示意图；
图2为本发明步骤1)的结构示意图；
图3为本发明步骤2)的结构示意图；
图4为本发明步骤3)的结构示意图；
图5为本发明步骤4)的结构示意图；
图6为本发明步骤5)的结构示意图；
图7为本发明步骤6)的结构示意图；
图8为本发明步骤7)的结构示意图；
图9为本发明步骤8)的结构示意图；
图10为本发明的一种纵向多重PN结的VDMOS分压环的结构示意图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，下面结合附图，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本发明。
请参阅图10，一种纵向多重PN结的VDMOS分压环的设计方法，包括以下步骤：
1)请参阅图2，衬底片准备；VDMOS的衬底片为N型掺磷epi1硅衬底，根据不同的耐压等级需求选择不同的N型电阻率。然后做Zero光刻、刻蚀，Zero仅用于后续的光刻对准，然后做BP光刻，BP1注入BP注入硼。
2)如图3所示，去胶后做BP1高温推阱，温度1150℃，时间300mins，形成深BP阱；
3)如图4，薄N型EPI4生长，厚度为为4um～5.0um。
其中，厚度太厚或者太薄都不能很好的形成所谓的Resurf结构。
4)如图5，NW5高能普注，注入磷，能量为300kev～360kev，，剂量为0.8E12～1.2E12；
其中，能量越高，注入深度越深，体内浓度越均匀，330Kev是常见的高能注入能量。
1.0E12是中心剂量，剂量越高，耐压越低，剂量越低，越不容易辅助BP耗尽。
5)如图6，Pw光刻，Pw6注入，注入硼，能量为80Kev，剂量为0.5E13～1.5E13；
6)如图7，去胶后做推阱，并用LOCOS的方式形成FOX区域7；
7)如图8，Ptop光刻，Ptop8注入，注入硼，能量180Kev，剂量2.9E12；
8)如图9，去胶后做短时间的推阱，然后做N+9光刻注入，P+10光刻注入，因为Ptop8、PW6、BP1均为P型区域；
9)如图10，ILD12沉积，孔刻蚀，Metal11沉积，Metal11光刻刻蚀。
所述NW5位于所述BP1上部。
所述Ptop8位于所述NW5上部。
所述Ptop8跟所述BP1通过所述PW6连接。
所述NW5位于所述Ptop8与所述跟BP1中间并与所述PW6平行。
以上所述实施例仅表达了本发明的实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

1.一种纵向多重PN结的VDMOS分压环的设计方法，其特征在于，包括以下工艺流程：
1)衬底片准备；根据不同的耐压等级选择不同的N型电阻率，接着做Zero光刻、刻蚀，Zero仅用于后续的光刻对准，然后做BP光刻，BP注入硼
2)去胶后做BP高温推阱，形成深BP阱；
3)薄N型EPI生长；
4)NW高能普注，注入磷；
5)Pw光刻，Pw注入，注入硼；
6)去胶后做推阱，并用LOCOS的方式形成FOX区域；
7)Ptop光刻，Ptop注入，注入硼；
8)去胶后做短时间的推阱，然后做N+光刻注入，P+光刻注入，其中，Ptop、PW、BP均为P型区域；
9)ILD沉积，孔刻蚀，Metal沉积，Metal光刻刻蚀。
2.根据权利要求1所述的一种纵向多重PN结的VDMOS分压环的设计方法，其特征在于：所述步骤2)中，温度为1150℃，时间为300mins。
3.根据权利要求1所述的一种纵向多重PN结的VDMOS分压环的设计方法，其特征在于：步骤3)中，所述生长厚度为4um～5.0um。。
4.根据权利要求1所述的一种纵向多重PN结的VDMOS分压环的设计方法，其特征在于：所述步骤4)中，能量为300kev～360kev，剂量为0.8E12～1.2E12。
5.根据权利要求1所述的一种纵向多重PN结的VDMOS分压环的设计方法，其特征在于：所述步骤5)中，能量为80Kev，剂量为0.5E13～1.5E13。
6.根据权利要求1所述的一种纵向多重PN结的VDMOS分压环的设计方法，其特征在于：所述步骤7)中，能量180Kev，剂量2.9E12。
7.根据权利要求1所述的一种纵向多重PN结的VDMOS分压环的设计方法，其特征在于：所述NW位于所述BP上部。
8.根据权利要求1所述的一种纵向多重PN结的VDMOS分压环的设计方法，其特征在于：所述Ptop位于所述NW上部。
9.根据权利要求1所述的一种纵向多重PN结的VDMOS分压环的设计方法，其特征在于：所述Ptop跟所述BP通过所述PW连接。
10.根据权利要求1所述的一种纵向多重PN结的VDMOS分压环的设计方法，其特征在于：所述NW位于所述Ptop与所述BP中间并与所述PW平行。
CN201811550606.7A 2018-12-18 2018-12-18 一种纵向多重pn结的vdmos分压环的设计方法 Active CN109616511B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201811550606.7A CN109616511B (zh) 2018-12-18 2018-12-18 一种纵向多重pn结的vdmos分压环的设计方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201811550606.7A CN109616511B (zh) 2018-12-18 2018-12-18 一种纵向多重pn结的vdmos分压环的设计方法

Publications (2)

Publication Number Publication Date
CN109616511A true CN109616511A (zh) 2019-04-12
CN109616511B CN109616511B (zh) 2021-11-26

Family

ID=66010620

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811550606.7A Active CN109616511B (zh) 2018-12-18 2018-12-18 一种纵向多重pn结的vdmos分压环的设计方法

Country Status (1)

Country Link
CN (1) CN109616511B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114114857A (zh) * 2022-01-25 2022-03-01 威海银创微电子技术有限公司 平面VDMOS中overlay偏差效应的解决方法、装置及介质

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63227063A (ja) * 1987-03-17 1988-09-21 Tdk Corp 高耐圧半導体装置
US5171699A (en) * 1990-10-03 1992-12-15 Texas Instruments Incorporated Vertical DMOS transistor structure built in an N-well CMOS-based BiCMOS process and method of fabrication
US20040206989A1 (en) * 2003-04-16 2004-10-21 Kabushiki Kaisha Toshiba Semiconductor device
CN101281907A (zh) * 2008-05-14 2008-10-08 电子科技大学 一种半导体器件及其提供的低压电源的应用
CN201430141Y (zh) * 2009-07-10 2010-03-24 西安芯派电子科技有限公司 一种新型的高压mos管
CN102420251A (zh) * 2011-12-05 2012-04-18 电子科技大学 一种具有非均匀浮岛结构的vdmos器件
CN103633089A (zh) * 2012-08-20 2014-03-12 上海华虹宏力半导体制造有限公司 多晶硅电阻及其制造方法
US20150206967A1 (en) * 2013-05-29 2015-07-23 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device
CN107403837A (zh) * 2016-05-20 2017-11-28 北大方正集团有限公司 一种横向双扩散金属氧化物半导体结构
CN108666368A (zh) * 2017-03-30 2018-10-16 无锡同方微电子有限公司 一种超结mosfet渐变终端结构及其制作方法

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63227063A (ja) * 1987-03-17 1988-09-21 Tdk Corp 高耐圧半導体装置
US5171699A (en) * 1990-10-03 1992-12-15 Texas Instruments Incorporated Vertical DMOS transistor structure built in an N-well CMOS-based BiCMOS process and method of fabrication
US5317180A (en) * 1990-10-03 1994-05-31 Texas Instruments Incorporated Vertical DMOS transistor built in an n-well MOS-based BiCMOS process
US20040206989A1 (en) * 2003-04-16 2004-10-21 Kabushiki Kaisha Toshiba Semiconductor device
CN101281907A (zh) * 2008-05-14 2008-10-08 电子科技大学 一种半导体器件及其提供的低压电源的应用
CN201430141Y (zh) * 2009-07-10 2010-03-24 西安芯派电子科技有限公司 一种新型的高压mos管
CN102420251A (zh) * 2011-12-05 2012-04-18 电子科技大学 一种具有非均匀浮岛结构的vdmos器件
CN103633089A (zh) * 2012-08-20 2014-03-12 上海华虹宏力半导体制造有限公司 多晶硅电阻及其制造方法
US20150206967A1 (en) * 2013-05-29 2015-07-23 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device
CN107403837A (zh) * 2016-05-20 2017-11-28 北大方正集团有限公司 一种横向双扩散金属氧化物半导体结构
CN108666368A (zh) * 2017-03-30 2018-10-16 无锡同方微电子有限公司 一种超结mosfet渐变终端结构及其制作方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114114857A (zh) * 2022-01-25 2022-03-01 威海银创微电子技术有限公司 平面VDMOS中overlay偏差效应的解决方法、装置及介质
CN114114857B (zh) * 2022-01-25 2022-05-10 威海银创微电子技术有限公司 平面VDMOS中overlay偏差效应的解决方法、装置及介质

Also Published As

Publication number Publication date
CN109616511B (zh) 2021-11-26

Similar Documents

Publication Publication Date Title
CN105190852B (zh) 改进的vjfet器件
JP5188037B2 (ja) 半導体装置
KR101638754B1 (ko) 반도체 장치
JP4564510B2 (ja) 電力用半導体素子
US10002920B1 (en) System and method for edge termination of super-junction (SJ) devices
CN107768428B (zh) 一种横向双扩散金属氧化物半导体(ldmos)器件及其制造方法
WO2013074291A1 (en) Method and system fabricating floating guard rings in gan materials
JP2011096757A (ja) 炭化珪素半導体装置
CN105261643B (zh) 一种高击穿电压氮化镓基高电子迁移率晶体管
JPWO2015166608A1 (ja) 炭化珪素半導体装置
US20120241899A1 (en) Power semiconductor device
WO2020002653A1 (en) Mosfet in sic with self-aligned lateral mos channel
WO2014199558A1 (ja) 半導体装置の製造方法
CN104241338A (zh) 一种SiC金属氧化物半导体晶体管及其制作方法
CN106158948A (zh) Ⅲ族氮化物增强型hemt器件及其制作方法
CN104638023A (zh) 一种垂直型恒流二极管及其制造方法
CN101916779A (zh) 可完全消除衬底辅助耗尽效应的soi超结ldmos结构
KR101222847B1 (ko) 반도체 장치 및 그 제조방법
CN108231880B (zh) 一种增强型GaN基HEMT器件及其制备方法
CN103178087A (zh) 超高压ldmos器件结构及制备方法
CN109616511A (zh) 一种纵向多重pn结的vdmos分压环的设计方法
US9257544B2 (en) Semiconductor device and fabrication method of semiconductor device
CN107819025A (zh) 半导体装置和半导体装置的制造方法
CN102376779A (zh) SiC肖特基二极管及其制作方法
JP2010114285A (ja) 半導体装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CP03 Change of name, title or address

Address after: 518000 1301, building 3, Chongwen Park, Nanshan Zhiyuan, No. 3370 Liuxian Avenue, Fuguang community, Taoyuan Street, Nanshan District, Shenzhen, Guangdong

Patentee after: Shenzhen Weizhao Semiconductor Co.,Ltd.

Address before: 518055 Tian Liao building 1115, Tian Liao Industrial Zone, Nanshan District Taoyuan street, Shenzhen, Guangdong, China 1115

Patentee before: VANGUARD SEMICONDUCTOR CO.,LTD.

CP03 Change of name, title or address