CN109473443A - 存储装置 - Google Patents

存储装置 Download PDF

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Publication number
CN109473443A
CN109473443A CN201810113346.0A CN201810113346A CN109473443A CN 109473443 A CN109473443 A CN 109473443A CN 201810113346 A CN201810113346 A CN 201810113346A CN 109473443 A CN109473443 A CN 109473443A
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insulating film
layer
electrode layer
conductive layer
semiconductor layer
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CN201810113346.0A
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山中贵哉
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Kioxia Corp
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Toshiba Memory Corp
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Abstract

实施方式提供一种能够容易地形成存储器孔，能够使制造良率提高的存储装置。存储装置具备：导电层；第1电极层，设置在导电层上；第2电极层，设置在导电层与第1电极层间，包含与第1电极层不同的材料；半导体柱，在从导电层朝向第1电极层的第1方向上贯穿第1及第2电极层地延伸，具有连接在导电层的端部；第1绝缘膜，包含位于半导体柱与第1电极层间、及半导体柱与第2电极层间、及半导体柱与导电层间的部分，沿半导体柱在第1方向上延伸；第2绝缘膜，设置在导电层与第1绝缘膜间；及第3绝缘膜，设置在第1绝缘膜与第2电极层间。所述第2、第3绝缘膜、第2电极层及导电层包含第1元素，第2及第3绝缘膜包含第1元素的氧化物或氮化物。

Description

存储装置
[相关申请案]
本申请享有以日本专利申请2017-173246号(申请日：2017年9月8日)为基础申请的优先权。本申请是通过参照该基础申请而包含基础申请的全部内容。
技术领域
实施方式涉及一种存储装置。
背景技术
包含三维配置的存储单元的存储装置的开发不断进展。例如，在NAND(Not-And，与非)型存储装置中，具有积层着多个电极层的构造，存储单元设置在将多个电极层在其积层方向上贯穿的存储器孔与各电极层交叉的部分。为了使这种存储装置的存储容量变大，优选使电极层的积层数变大。然而，随着电极层的积层数变大，而变得难以形成存储器孔。
发明内容
实施方式提供一种能够容易地形成存储器孔且能够使制造良率提高的存储装置。
实施方式的存储装置具备：导电层；第1电极层，设置在所述导电层上；第2电极层，设置在所述导电层与所述第1电极层之间，且包含与所述第1电极层不同的材料；半导体柱，在从所述导电层朝向所述第1电极层的第1方向上贯穿所述第1电极层及所述第2电极层地延伸，且具有连接在所述导电层的端部；第1绝缘膜，包含位于所述半导体柱与所述第1电极层之间、及所述半导体柱与所述第2电极层之间、及所述半导体柱与所述导电层之间的部分，且沿所述半导体柱在所述第1方向上延伸；第2绝缘膜，设置在所述导电层与所述第1绝缘膜之间；及第3绝缘膜，设置在所述第1绝缘膜与所述第2电极层之间。所述第2绝缘膜、所述第3绝缘膜、所述第2电极层及所述导电层包含第1元素，所述第2绝缘膜及所述第3绝缘膜包含所述第1元素的氧化物或氮化物。
附图说明
图1是表示第1实施方式的存储装置的示意性剖视图。
图2是表示第1实施方式的存储装置的一部分的示意性剖视图。
图3(a)～(c)、图4(a)及(b)、图5(a)及(b)、图6(a)及(b)、图7(a)及(b)是表示第1实施方式的存储装置的制造过程的示意性剖视图。
图8(a)及(b)是表示比较例的存储装置的制造过程的示意性剖视图。
图9是表示第1实施方式的变化例的存储装置的示意性剖视图。
图10是表示第2实施方式的存储装置的示意性剖视图。
图11(a)及(b)、图12(a)及(b)、图13、图14(a)及(b)、图15(a)及(b)、图16(a)及(b)是表示第2实施方式的存储装置的制造过程的示意性剖视图。
具体实施方式
以下，一边参照附图，一边对实施方式进行说明。对附图中的相同的部分标注相同的编号而适当省略其详细的说明，并针对不同的部分进行说明。此外，附图是示意性或概念性图，各部分的厚度与宽度的关系、部分间的大小的比率等未必与实物相同。另外，即便在表示相同的部分的情况下，有时也根据附图而使相互的尺寸或比率不同地表示。
此外，使用各图中所示的X轴、Y轴及Z轴来说明各部分的配置及构成。X轴、Y轴及Z轴相互正交，分别表示X方向、Y方向及Z方向。另外，有时将Z方向设为上方，并将其相反方向设为下方而进行说明。
[第1实施方式]
图1是表示第1实施方式的存储装置1的示意性剖视图。存储装置1例如是包含三维配置的存储单元MC的NAND型非易失性存储装置。
像图1所示那样，存储装置1包含电路DC、及设置在电路DC之上的存储单元阵列MCA。另外，存储装置1还包含源极线SL及配线层IL。源极线SL配置在电路DC与存储单元阵列MCA之间。配线层IL设置在存储单元阵列MCA的上方。
电路DC例如包含设置在衬底10的上层的晶体管Tr、以及D1配线及D2配线。衬底10例如是硅衬底。
存储单元阵列MCA包含积层在源极线SL之上的多个电极层。电极层包含多条字线WL、选择栅极SGS、及选择栅极SGD。字线WL配置在选择栅极SGS与选择栅极SGD之间。
存储单元阵列MCA还包含半导体柱20及绝缘膜30。半导体柱20在多个电极层的积层方向(Z方向)上贯穿所述多个电极层。半导体柱20在其下端连接在源极线SL。绝缘膜30沿半导体柱20在Z方向上延伸，且包含位于半导体柱20与各电极层之间的部分。
存储单元MC设置在半导体柱20与字线WL交叉的部分。位于半导体柱20与字线WL之间的绝缘膜30的部分是作为存储单元MC的电荷保持部而发挥功能。在半导体柱20与选择栅极SGS交叉的部分，设置源极侧选择晶体管STS。另外，在半导体柱20与选择栅极SGD交叉的部分，设置漏极侧选择晶体管STD。
源极线SL例如设置为在X方向及Y方向上扩展的板状，且包含金属层40及半导体层50。半导体层50设置在金属层40之上，半导体柱20的下端连接在半导体层50。
配线层IL例如包含M0配线、M1配线及M2配线。另外，配线层IL包含电连接在半导体柱20的位线BL。字线WL、选择栅极SGS及SGD例如在未图示的部分分别连接在多条M0配线。
另一方面，电路DC的D2配线例如经由设置在存储单元阵列MCA的周边的接触插塞CP而连接在M0配线。另外，源极线SL也经由另一接触插塞CP而连接在M0配线。
此外，存储装置1具有设置于在X方向上相邻的字线WL间、选择栅极SGS间及选择栅极SGD间的狭缝ST。在狭缝ST的内部例如设置连接导体CB。连接导体CB例如是在Y方向及Z方向上扩展的板状导体，且连接在源极线SL。另外，连接导体CB在未图示的部分连接在例如M0配线。
在配线层IL中，例如，M0配线经由M1配线及M2配线而相互连接。由此，存储单元阵列MCA的各要素可电连接在电路DC，并使存储装置1动作。
图2是表示第1实施方式的存储装置1的一部分的示意性剖视图。图2是表示源极线SL与半导体柱20的连接区域的剖视图。半导体柱20在其下端20B连接在半导体层50。像图2所示那样，下端20B位于半导体层50中。
在半导体层50与选择栅极SGS之间设置层间绝缘膜21。另外，在选择栅极SGS与字线WL之间设置层间绝缘膜25。半导体柱20例如以包围绝缘性芯60的周围的方式设置。绝缘性芯60贯穿层间绝缘膜21、选择栅极SGS、层间绝缘膜25及字线WL地在Z方向上延伸。
像图2所示那样，绝缘膜30例如具有在从字线WL朝向半导体柱20的方向上积层着第1膜33、第2膜35及第3膜37的构造。第1膜33及第3膜37例如是氧化硅膜，第2膜35例如是氮化硅膜。绝缘膜30具有在第1膜33与第3膜37之间捕获电荷的功能。而且，第1膜33例如作为阻挡绝缘膜而发挥功能，第3膜37例如作为隧道绝缘膜而发挥功能。
绝缘膜30具有位于半导体柱20与半导体层50之间的部分。在该例中，在绝缘膜30与半导体层50之间设置绝缘膜43。另外，在绝缘膜30与选择栅极SGS之间设置绝缘膜45。绝缘膜43是通过使半导体层50氧化或氮化而形成。绝缘膜45是通过使选择栅极SGS氧化或氮化而形成。例如，半导体层50及选择栅极SGS是包含硅元素(Si)的半导体，绝缘膜43及45例如包含氧化硅或氮化硅。
层间绝缘膜21与绝缘膜43的上端相接，例如具有在X方向上位于比绝缘膜43的外缘43d更靠内侧且与绝缘膜30相接的端面21p。另外，层间绝缘膜25与绝缘膜45的上端相接，例如具有在X方向上位于比绝缘膜45的外缘45d更靠内侧且与绝缘膜30相接的端面25p。
接下来，参照图3～图7来说明第1实施方式的存储装置1的制造方法。图3(a)～图7(b)是表示存储装置1的制造过程的示意性剖视图。
像图3(a)所示那样，在层间绝缘膜15之上积层金属层40及半导体层50。层间绝缘膜15是覆盖电路DC的绝缘膜，例如是利用TEOS(tetraethoxysilane，四乙氧基硅烷)-CVD(Chemical Vapor Deposition，化学气相沉积)而形成的氧化硅膜。金属层40例如是利用CVD而形成的钨层。半导体层50例如是利用CVD而形成的多晶硅层。
此外，将层间绝缘膜21、25、牺牲膜27及半导体层31形成在半导体层50之上。层间绝缘膜21例如是氧化硅膜，利用CVD而形成在半导体层50之上。半导体层31例如是多晶硅层，利用CVD而形成在层间绝缘膜21之上。
接着，在半导体层31之上交替地积层层间绝缘膜25及牺牲膜27。层间绝缘膜25例如是利用CVD而形成的氧化硅膜。牺牲膜27例如是利用CVD而形成的氮化硅膜。此外，为了方便起见，图3(a)及以下的各图中所记载的层间绝缘膜25及牺牲膜27比实际的积层数更少地表示。
像图3(b)所示那样，形成从最上层的牺牲膜27的上表面到达半导体层50的深度的存储器孔MH1。例如，选择性地去除层间绝缘膜25及牺牲膜27，而形成具有到达半导体层31的深度d1的存储器孔MH1。然后，在存储器孔MH1的底部，选择性地去除半导体层31及层间绝缘膜21，而使存储器孔MH1延长至到达半导体层50为止。在该情况下，优选层间绝缘膜21的Z方向的厚度比层间绝缘膜25的Z方向的厚度更薄。
层间绝缘膜25及牺牲膜27例如利用各向异性RIE(Reactive Ion Etching，反应性离子蚀刻)而选择性地被去除。此时，通过将半导体层31用作蚀刻终止膜，可使存储器孔MH1的底面位置的控制性提高。例如，半导体层31及层间绝缘膜21依序被蚀刻，但能够使其蚀刻速度比层间绝缘膜25及牺牲膜27的蚀刻速度更慢。由此，例如能够避免半导体层50被去除而金属层40在存储器孔MH1的底面露出。
像图3(c)所示那样，在存储器孔MH1的底部，形成使半导体层31及50热氧化而成的绝缘膜43及45。绝缘膜43及45例如是氧化硅层。绝缘膜43形成在存储器孔MH1的底面，绝缘膜45形成在半导体层31的端面上。此外，绝缘膜43及45并不限于通过热氧化而形成，也可例如利用利用氧自由基的氧化、或利用氮自由基的氮化而形成。也就是说，绝缘膜43及45也可为氮化硅膜。
像图4(a)所示那样，在存储器孔MH1的内部嵌埋牺牲层47。牺牲层47例如是非晶硅层。例如，利用CVD形成非晶硅层，将存储器孔MH1的内部嵌埋，且覆盖牺牲膜27的上表面。然后，使嵌埋存储器孔MH1的部分残留地将非晶硅层去除。非晶硅层是例如利用CMP(ChemicalMechanical Polishing，化学机械抛光)而被去除。
像图4(b)所示那样，将层间绝缘膜55及牺牲膜57积层在使牺牲层47露出的牺牲膜27的表面上。层间绝缘膜55例如是氧化硅膜，牺牲膜57例如是氮化硅膜。层间绝缘膜55及牺牲膜57交替地积层。
像图5(a)所示那样，选择性地去除层间绝缘膜55及牺牲膜57，而形成存储器孔MH2。层间绝缘膜55及牺牲膜57例如利用各向异性RIE而被去除。另外，存储器孔MH2以与嵌埋存储器孔MH1的牺牲层47连通的方式形成。
像图5(b)所示那样，通过选择性地去除牺牲层47，而形成将存储器孔MH1与存储器孔MH2连通而成的存储器孔MH。牺牲层47例如利用湿式蚀刻而选择性地被去除。此时，设置在存储器孔MH1的底面的绝缘膜43防止半导体层50被牺牲层47的蚀刻液蚀刻。另外，绝缘膜45防止半导体层31被牺牲层47的蚀刻液蚀刻。像这样，通过使用将存储器孔MH1与存储器孔MH2连通的两个阶段的形成方法，能够容易地形成纵横比大的存储器孔MH。
像图6(a)所示那样，形成覆盖存储器孔MH的内表面的绝缘膜30。绝缘膜30例如利用ALD(Atomic Layer Deposition，原子层沉积法)而形成。
像图6(b)所示那样，在存储器孔MH的底面，选择性地去除绝缘膜30及绝缘膜43。绝缘膜30及绝缘膜43例如利用各向异性RIE而被去除。此时，因存储器孔MH2相对于存储器孔MH1的对准偏移，而绝缘膜30及绝缘膜43的各自的一部分残留在存储器孔MH的底面上。
另外，在绝缘膜30及绝缘膜43的蚀刻过程中，半导体层50的一部分也被蚀刻。因此，对绝缘膜30及绝缘膜43进行蚀刻后的存储器孔MH的底面MHB位于比绝缘膜43更靠下方的高度(level)。此时，存储器孔MH的底面MHB是以不到达金属层40而位于半导体层50中的方式形成。
像图7(a)所示那样，形成覆盖存储器孔MH的内表面的半导体柱20。半导体柱20例如是利用CVD而形成的多晶硅层。半导体柱20在存储器孔MH的底面MHB，与半导体层50相接。由此，能够降低半导体柱20与源极线SL之间的接触电阻。
像图7(b)所示那样，以将存储器孔MH的内部嵌埋的方式形成绝缘性芯60。绝缘性芯60例如是氧化硅，利用CVD而形成。接着，通过将牺牲膜27及57替换为金属膜、例如钨膜，而形成字线WL及选择栅极SGD，从而完成存储单元阵列MCA。
图8(a)及(b)是表示比较例的存储装置2的制造过程的示意性剖视图。图8(a)是表示与牺牲层47连通的存储器孔MH2的剖视图。图8(b)是表示将存储器孔MH1与存储器孔MH2连通而成的存储器孔MH的剖视图。
像图8(a)所示那样，在该例中，在牺牲层47与半导体层50之间未设置绝缘膜43，且在半导体层31与牺牲层47之间未设置绝缘膜45。因此，在牺牲层47的蚀刻过程中，无法避免半导体层31及半导体层50被蚀刻。
结果，像图8(b)所示那样，在去除牺牲层47之后，形成半导体层31及半导体层50被蚀刻而成的空间31s及50s。由此，例如形成为金属层40在存储器孔MH的底面露出，半导体柱20与金属层40相接。结果，有半导体柱20与源极线SL之间的接触电阻变大的担忧。此外，也有因半导体层31及半导体层50的向X方向及Y方向的蚀刻的进展，而相邻的存储器孔MH间连通，从而图8(b)所示的积层构造倒塌的担忧。
相对于此，在本实施方式的存储装置1中，通过设置绝缘膜43及45，能够防止半导体层31及半导体层50的蚀刻，而避免这种不良情况。由此，能够使存储装置1的制造良率提高。
图9是表示第1实施方式的变化例的存储装置3的示意性剖视图。存储装置3是通过与图3(a)～图7(b)所示的制造过程相同的步骤而形成。
像图9所示那样，存储装置3具有在半导体层50与绝缘膜30之间具有绝缘膜43，但在选择栅极SGS与绝缘膜30之间未设置绝缘膜45的构造。这种构造能够通过例如在图3(a)所示的积层构造中省略半导体层31而形成。在该例中，选择栅极SGS包含与字线WL及选择栅极SGD相同的材料。另外，绝缘膜43防止牺牲层47的蚀刻液造成的半导体层50的蚀刻。
[第2实施方式]
图10是表示第2实施方式的存储装置4的示意性剖视图。存储装置4的源极线SL包含金属层40、以及半导体层50、70及80。半导体层70与半导体柱20的侧面20s相接，源极线SL是经由半导体层70而电连接在半导体柱20。
像图10所示那样，半导体层50设置在金属层40之上，半导体层70设置在半导体层50之上。半导体层80设置在半导体层70之上。半导体层50、70及80例如是硅层。
选择栅极SGS隔着层间绝缘膜21而设置在半导体层80之上。另外，多条字线WL隔着层间绝缘膜25而积层在选择栅极SGS之上。此外，未图示的选择栅极SGD设置在字线WL的上方。
存储器孔MH贯通多条字线WL、选择栅极SGS、层间绝缘膜21、25及半导体层70、80且设置为到达半导体层50的深度。在存储器孔MH的内部，设置半导体柱20、绝缘膜30及绝缘性芯60。绝缘膜30例如具有包含第1膜33、第2膜35及第3膜37的积层构造。
在半导体层50与绝缘膜30之间设置绝缘膜93，在半导体层80与绝缘膜30之间设置绝缘膜95。此外，在选择栅极SGS与绝缘膜30之间设置绝缘膜97。
层间绝缘膜21与绝缘膜95的上端相接。另外，层间绝缘膜21的端面21p例如在X方向上位于比绝缘膜95的外缘95d更靠内侧且与绝缘膜30相接。另外，层间绝缘膜25与绝缘膜97的上端相接。此外，层间绝缘膜25的端面25p例如在X方向上位于比绝缘膜97的外缘97d更靠内侧且与绝缘膜30相接。
接下来，参照图11～图16来说明第2实施方式的存储装置4的制造方法。图11(a)～图16(b)是表示存储装置4的制造过程的示意性剖视图。
像图11(a)所示那样，在金属层40之上积层半导体层50、73及80。在半导体层50与半导体层73之间形成绝缘膜75。另外，在半导体层73与半导体层80之间形成绝缘膜77。
金属层40隔着层间绝缘膜而设置在衬底10的上方(参照图1)。半导体层50、73及80例如是利用CVD而形成的多晶硅层。绝缘膜75及77例如是氧化硅膜。
在半导体层80之上隔着层间绝缘膜21形成半导体层31。此外，在半导体层31之上，交替地积层层间绝缘膜25及牺牲膜27。半导体层31例如是低电阻的多晶硅层，层间绝缘膜21及25例如是氧化硅膜。牺牲膜27例如是氮化硅膜。
像图11(b)所示那样，形成从最上层的层间绝缘膜25到达半导体层50的深度的存储器孔MH1。存储器孔MH1例如利用各向异性RIE而形成。在存储器孔MH1的形成过程中，半导体层31作为蚀刻终止层而发挥功能。此外，半导体层31、层间绝缘膜21、半导体层80、绝缘膜77、半导体层73及绝缘膜75分别选择性地依序被蚀刻。由此，变得容易使存储器孔MH1的底面位于半导体层50的内部。
像图12(a)所示那样，在存储器孔MH1的底部形成绝缘膜93、94、95及97。绝缘膜93、94、95及97例如通过使在存储器孔MH1的内表面露出的半导体层50、73、80及半导体层31分别热氧化而形成。绝缘膜93、94、95及97例如是氧化硅膜。
像图12(b)所示那样，在存储器孔MH1的内部形成牺牲层47。牺牲层47例如是利用CVD而形成的非晶硅层。例如，以将存储器孔MH1的内部嵌埋且覆盖作为最上层的层间绝缘膜25的方式形成非晶硅层之后，利用CMP去除形成在层间绝缘膜25之上的部分，由此形成嵌埋存储器孔MH1的内部的牺牲层47。
像图13所示那样，在积层层间绝缘膜25及牺牲膜27而成的积层体之上交替地积层层间绝缘膜55及牺牲膜57。接着，形成从层间绝缘膜55的最上层起连通到牺牲层47的存储器孔MH2。存储器孔MH2例如通过利用各向异性RIE选择性地去除层间绝缘膜55及牺牲膜57而形成。
像图14(a)所示那样，选择性地去除嵌埋存储器孔MH1的牺牲层47。绝缘膜93、94、95及97是在去除牺牲层47的过程中，分别保护半导体层50、73、80及31使它们不被牺牲层47的蚀刻液所蚀刻。此外，在图14(a)及其以后的图中，为了方便起见，省略了层间绝缘膜55及牺牲膜57。
像图14(b)所示那样，在存储器孔MH1的内部形成半导体柱20、绝缘膜30及绝缘性芯60。半导体柱20、绝缘膜30及绝缘性芯60也形成在未图示的存储器孔MH2的内部(参照图7(b))。此外，在本实施方式中，在存储器孔MH1的底面，无需为了形成半导体柱20而选择性地去除绝缘膜30的一部分(参照图6(b))，绝缘膜30、半导体柱20及绝缘性芯60在存储器孔MH1及MH2的内部依序形成。
接着，以将层间绝缘膜21、25、牺牲膜27、半导体层80、31、未图示的层间绝缘膜55及牺牲膜57断开的方式形成狭缝ST。此时，半导体层31及绝缘膜77作为蚀刻终止层而发挥功能。例如，半导体层31作为去除层间绝缘膜25、55、牺牲层27及57时的蚀刻终止层而发挥功能。此外，绝缘膜77作为用来使狭缝ST的底面位于半导体层73的上表面的高度的蚀刻终止层而发挥功能。也就是说，狭缝ST是以半导体层73的上表面露出在其底面的方式形成。
像图15(a)所示那样，在狭缝ST的内壁上形成绝缘膜110。例如，通过在形成覆盖狭缝ST的内表面的绝缘膜之后，利用各向异性RIE去除覆盖狭缝ST的底面的部分，而形成绝缘膜110。
像图15(b)所示那样，经由狭缝ST而选择性地去除半导体层73。半导体层73例如利用湿式蚀刻而被去除。此时，绝缘膜75、77及110保护半导体层50、80及31使它们不被半导体层73的蚀刻液所蚀刻。
像图16(a)所示那样，在通过半导体层73的去除所形成的空间73s中，去除绝缘膜30、75及77，而使半导体柱20的侧面20s露出。绝缘膜30、75及77例如利用经由狭缝ST而供给的蚀刻液而被去除。绝缘膜110例如是氮化硅膜，且形成为在去除绝缘膜30、75及77之后仍残留在狭缝ST的内壁上的厚度。
像图16(b)所示那样，在空间73s的内部形成半导体层70。例如，在露出于空间73s的内部的半导体柱20、半导体层50及80的各自的表面上沉积硅层，以嵌埋空间73s的内部。由此，形成半导体层70。半导体层70形成为电连接在半导体柱20、半导体层50及80。
接着，在去除绝缘膜110之后，选择性地去除牺牲膜25及55。然后，在去除牺牲膜25及55而成的空间内形成例如金属层。结果，形成多条字线WL。此外，在狭缝ST内形成绝缘膜65，而完成存储装置4(参照图10)。
在本实施方式的存储装置4中，也通过设置绝缘膜93、94、95及97，而能够在牺牲层47的去除过程中，防止半导体层31、50、73及80的蚀刻。由此，能够防止因半导体柱20隔着绝缘膜30形成在金属层40之上而产生的不良情况、例如金属原子向半导体柱20的扩散。另外，也能够避免相邻的存储器孔MH间连通所造成的积层构造的倒塌。
对本发明的若干个实施方式进行了说明，但这些实施方式是作为示例而提出的，并不意图限定发明的范围。这些新颖的实施方式能以其它各种方式实施，可在不脱离发明的主旨的范围内，进行各种省略、替换及变更。这些实施方式或其变化包含在发明的范围或主旨内，并且包含在权利要求书所记载的发明及其均等的范围内。
[符号的说明]
1、2、3、4 存储装置
10 衬底
15、21、25、55 层间绝缘膜
20 半导体柱
20B 下端
20s 侧面
21p、25p 端面
27、57 牺牲膜
30、43、45、75、77、93、94、95、97、110 绝缘膜
31、50、70、73、80 半导体层
31s、73s 空间
33 第1膜
35 第2膜
37 第3膜
40 金属层
43d、45d、95d、97d 外缘
47 牺牲层
60 绝缘性芯
BL 位线
CB 连接导体
CP 接触插塞
D1、D2、M0、M1、M2 配线
DC 电路
IL 配线层
MC 存储单元
MCA 存储单元阵列
MH、MH1、MH2 存储器孔
MHB 底面
SGD、SGS 选择栅极
SL 源极线
ST 狭缝
STD、STS 选择晶体管
Tr 晶体管
WL 字线

Claims (5)

1.一种存储装置，其特征在于具备：
导电层；
第1电极层，设置在所述导电层上；
第2电极层，设置在所述导电层与所述第1电极层之间，且包含与所述第1电极层不同的材料；
半导体柱，在从所述导电层朝向所述第1电极层的第1方向上贯穿所述第1电极层及所述第2电极层地延伸，且具有连接在所述导电层的端部；
第1绝缘膜，包含位于所述半导体柱与所述第1电极层之间、及所述半导体柱与所述第2电极层之间、及所述半导体柱与所述导电层之间的部分，且沿所述半导体柱在所述第1方向上延伸；
第2绝缘膜，设置在所述导电层与所述第1绝缘膜之间；及
第3绝缘膜，设置在所述第1绝缘膜与所述第2电极层之间；
所述第2绝缘膜、所述第3绝缘膜、所述第2电极层及所述导电层包含第1元素，
所述第2绝缘膜及所述第3绝缘膜包含所述第1元素的氧化物或氮化物。
2.根据权利要求1所述的存储装置，其特征在于还具备第1层间绝缘膜，所述第1层间绝缘膜设置在所述导电层与所述第2电极层之间，且与所述第1绝缘膜及所述第2绝缘膜相接；
所述第1层间绝缘膜在与所述第2绝缘膜相接的部分，具有位于比所述第2绝缘膜的外缘更靠内侧且与所述第1绝缘膜相接的端面。
3.根据权利要求1或2所述的存储装置，其特征在于还具备第2层间绝缘膜，所述第2层间绝缘膜设置在所述第1电极层与所述第2电极层之间，且与所述第1绝缘膜及所述第3绝缘膜相接，
所述第2层间绝缘膜在与所述第3绝缘膜相接的部分，具有位于比所述第3绝缘膜的外缘更靠内侧且与所述第1绝缘膜相接的端面。
4.根据权利要求1或2所述的存储装置，其特征在于，
所述导电层及所述第2电极层包含多晶硅。
5.一种存储装置，其特征在于具备：
导电层；
多个电极层，积层在所述导电层上；
半导体柱，在所述电极层的积层方向上贯穿所述多个电极层地延伸，且具有连接在所述导电层的端部；
第1绝缘膜，包含位于所述半导体柱与所述多个电极层之间、及所述半导体柱与所述导电层之间的部分，且沿所述半导体柱在所述积层方向上延伸；及
第2绝缘膜，设置在所述导电层与所述第1绝缘膜之间；
所述第2绝缘膜及所述导电层包含第1元素，
所述第2绝缘膜包含所述第1元素的氧化物或氮化物。
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