CN109427715B - 半导体封装及制作半导体封装、重布线层及内连结构的方法 - Google Patents
半导体封装及制作半导体封装、重布线层及内连结构的方法 Download PDFInfo
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- CN109427715B CN109427715B CN201710992228.7A CN201710992228A CN109427715B CN 109427715 B CN109427715 B CN 109427715B CN 201710992228 A CN201710992228 A CN 201710992228A CN 109427715 B CN109427715 B CN 109427715B
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Abstract
一种制作半导体封装的方法包括提供具有至少一个接点的衬底以及在所述衬底上形成重布线层。所述形成所述重布线层包括在所述衬底之上形成介电材料层以及对所述介电材料层执行双重曝光工艺。接着执行显影工艺并在所述介电材料层中形成双重镶嵌开口。在所述双重镶嵌开口之上及所述介电材料层之上形成晶种金属层。在所述晶种金属层之上形成金属层。形成重布线图案,所述重布线图案位于所述双重镶嵌开口中且电连接所述至少一个接点。
Description
技术领域
本发明实施例涉及一种制作半导体封装的方法。
背景技术
集成电路(integrated circuit,IC)的封装技术涉及将集成电路(IC)管芯包封在包封材料(encapsulation material)中并构建所需重布线层。形成鳍片节距重布线层(fin-pitch redistribution layer)使得能够制作具有高集成度的较小封装。
发明内容
根据本发明的一些实施例,一种制作半导体封装的方法包括至少以下步骤。提供具有至少一个接点的衬底以及在所述衬底上形成重布线层。形成重布线层包括至少以下步骤。在衬底之上形成介电材料层。对所述介电材料层执行双重曝光工艺。执行显影工艺并在介电材料层中形成双重镶嵌开口。在双重镶嵌开口之上及介电材料层之上形成晶种金属层。在晶种金属层之上形成金属层。形成重布线图案,所述重布线图案位于双重镶嵌开口中且电连接所述至少一个接点。
附图说明
结合附图阅读以下详细说明,会最好地理解本发明的各个方面。应注意,根据本行业中的标准惯例,各种特征并非按比例绘制。事实上,为论述清晰起见,可任意增大或减小各种特征的尺寸。
图1至图7示意性地说明根据一些实施例的制作半导体封装的方法形成重布线层的各工艺的各种阶段。
图8至图14示意性地说明根据一些实施例的制作半导体封装的方法形成另一重布线层的各工艺的各种阶段。
图15说明根据一些实施例的半导体封装中的重布线层的示意性布局俯视图。
图16示意性地说明根据一些实施例的具有一个或多个重布线层的半导体封装。
图17至图20示意性地说明根据一些实施例的制作半导体封装的方法的各种阶段。
图21示意性地说明根据一些实施例的具有一个或多个重布线层的半导体封装。
具体实施方式
以下公开内容提供用于实作所提供主题的不同特征的许多不同的实施例或实例。以下阐述组件及排列的具体实例以简化本公开内容。当然,这些仅为实例且不旨在进行限制。举例来说,以下说明中将第一特征形成在第二特征“之上”或第二特征“上”可包括其中第一特征及第二特征被形成为直接接触的实施例,且也可包括其中第一特征与第二特征之间可形成有附加特征、进而使得所述第一特征与所述第二特征可能不直接接触的实施例。另外,本公开内容可能在各种实例中重复使用参考编号及/或字母。这种重复使用是出于简洁及清晰的目的,而不是自身表示所论述的各种实施例及/或配置之间的关系。
此外,为易于说明,本文中可能使用例如“之下(beneath)”、“下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示的一个组件或特征与另一(其他)组件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括装置在使用或操作中的不同取向。设备可具有其他取向(旋转90度或处于其他取向),且本文中所用的空间相对性描述语可同样相应地进行解释。
也可包括其他特征及工艺。举例来说,可包括测试结构,以帮助对三维(3D)封装或三维集成电路(3DIC)装置进行验证测试。所述测试结构可例如包括在重布线层中或在衬底上形成的测试接垫(testpad),以容许对3D封装或3DIC进行测试、对探针及/或探针卡(probe card)进行使用等。可对中间结构以及最终结构执行验证测试。另外,本文中所公开的结构及方法可结合包括对已知良好管芯的中间验证的测试方法论一起使用,以提高良率并降低成本。
图1至图7示意性地说明根据一些实施例的制作半导体封装的方法形成重布线层的各工艺的各种阶段。参照图1,提供具有多个接点(contact)104的衬底102。在一些实施例中,在衬底102上形成第一介电材料层110,第一介电材料层110覆盖接点104。在一些实施例中,衬底102可包括一个或多个半导体芯片或者半导体晶片或重构晶片(reconstitutedwafer)的复数个管芯。在一些实施例中,衬底102是包括模塑在模塑化合物(molding compound)中的多个管芯的重构晶片。在一些实施例中,接点104是所述管芯的接点接垫(contactpad)或导电接垫。在一些实施例中,举例来说,衬底102可为单晶半导体衬底,例如硅衬底、绝缘体上硅(silicon-on-insulator,SOI)衬底、或绝缘体上锗(germanium-on-insulator,GOI)衬底。根据实施例,半导体衬底可包括其他导电层、掺杂区、或其他半导体元件(例如,晶体管、二极管等)。所述实施例旨在用于说明目的,而不旨在限制本发明的范围。
参照图1,在一些实施例中,可通过例如旋转涂布工艺(spin-coating process)等涂布工艺或者包括化学气相沉积(chemical vapor deposition,CVD)工艺的沉积工艺来形成第一介电材料层110。在一些实施例中,第一介电材料层110可为正性感光性材料层(positive photo-sensitive material layer)。在一些实施例中,第一介电材料层110的材料可为正型感光性材料,包括聚酰亚胺、苯并环丁烯(benzocyclobutene,BCB)、聚苯并恶唑(polybenzooxazole,PBO)、或任何其他适合的感光性聚合物材料或其他光刻胶材料。在一些实施例中,第一介电材料层110的材料可为正性光刻胶材料,且所述正性光刻胶材料可为H-线(H-line)光刻胶材料、I-线(I-line)光刻胶材料、宽频(wide-band)光刻胶材料、或深紫外光(deep-UV)光刻胶材料。
参照图2,对第一介电材料层110执行第一曝光工艺E1以形成第一曝光部分110A。在一些实施例中,使用具有第一图案PT1的掩模MK1执行第一曝光工艺E1,从光源(图中未示出)辐射的光或照明(如箭头所示)穿过掩模MK1。在一些实施例中,第一图案PT1包括多个开口PTO1。在一些实施例中,通过第一曝光工艺E1将第一图案PT1的图像转移到第一介电材料层110。在图2中,通过第一曝光工艺E1使用光或照明将第一介电材料层110局部地曝光,且在第一介电材料层110的暴露于穿过开口PTO1的光的暴露区(示出为斑点区)中形成第一曝光部分110A。在一些实施例中,通过调整能量源(例如,光源)的能量水平或能量剂量及/或曝光时间,可精确地控制曝光区的深度(光可到达的深度)。在一些实施例中,以第一能量剂量执行第一曝光工艺E1,且第一曝光部分110A形成为具有深度d1及在水平方向x(垂直于第一介电材料层110的厚度方向z)上的底部大小(bottom size)S1。在一些实施例中,第一曝光部分110A的深度d1实质上等于第一介电材料层110的厚度T1。在一些实施例中,第一介电材料层110的厚度T1介于从约10微米到约30微米范围内,且第一能量剂量介于约50mJ/cm2到约100mJ/cm2范围内。在一些实施例中,第一曝光部分110A构成潜在图案且所述潜在图案是对第一图案PT1的再现。也就是说,第一曝光部分110A的位置及形状对应于且实质上模拟开口PTO1的位置及形状。在一些实施例中,第一曝光部分110A的潜在图案包括通孔开口图案。根据实施例,出于放大或减小的目的,以任意特定比率将掩模的图案的图像完全地或局部地转移到目标材料层或结构。所述实施例旨在用于说明目的,而不旨在限制本发明的范围。
对于正性感光性材料或正性光刻胶材料,暴露于适合波长(其取决于材料)的光会使得所述正性感光性材料或正性光刻胶材料发生化学反应,且经处理的部分将在后续显影工艺期间变得更加可溶解或容易得多地被移除。在一些实施例中,由于第一介电材料层110是正性感光性材料层,因此第一介电材料层110的第一曝光部分110A发生化学反应且在后续显影工艺期间变得可溶解。
参照图3,对第一介电材料层110执行第二曝光工艺E2以形成第二曝光部分110B。在一些实施例中,使用具有第二图案PT2的掩模MK2执行第二曝光工艺E2,光或照明(如箭头所示)穿过掩模MK2。在一些实施例中,掩模MK1、MK2可指代同一掩模的不同部分或两个掩模。在一些实施例中,第二图案PT2包括多个开口PTT1。在一些实施例中,通过第二曝光工艺E2将第二图案PT2的图像转移到第一介电材料层110。在图3中,通过第二曝光工艺E2使用光或照明将第一介电材料层110局部地曝光,且在第一介电材料层110的暴露于穿过开口PTT1的光的暴露区(示出为斑点区)中形成第二曝光部分110B。在一些实施例中,第二曝光部分110B的位置及形状对应于且实质上模拟开口PTT1的位置及形状。在一些实施例中,以第二能量剂量执行第二曝光工艺E2,且第二曝光部分110B形成为具有深度d2及在水平方向x(垂直于第一介电材料层110的厚度方向z)上的底部大小S2。在一些实施例中,第二曝光部分110B的深度d2小于第一介电材料层110的厚度T1。在一些实施例中,第二曝光部分110B的深度d2小于第一曝光部分110A的深度d1。在一个实施例中,第二能量剂量低于第一能量剂量。在一些实施例中,第二能量剂量介于从约50mJ/cm2到约100mJ/cm2范围内。在一些实施例中,第二曝光部分110B构成潜在图案且所述潜在图案是对第二图案PT2的再现。在一些实施例中,深度的比率d2/d1可为约0.4~0.6。在一些实施例中,第一曝光部分110A的位置与第二曝光部分110B的部份的位置交叠。在一些实施例中,第二曝光部分110B的潜在图案包括沟槽开口图案。
在一些实施例中,可将第一曝光工艺E1及第二曝光工艺E2视作双重曝光工艺(double exposure process)。在一些实施例中,此种双重曝光工艺仅需要一个感光性介电材料层,与执行两次传统光刻曝光工艺相比,此种双重曝光工艺的工艺步骤大为简化,因此会降低成本且节省时间来形成重布线层(redistribution layer,RDL)。
在一些实施例中,通过执行两个接连的曝光工艺,可实现更好的图案的曝光对准(exposure alignment)及更精确的图案叠加(pattern overlay)(尤其是RDL对通孔的叠加)。在一些实施例中,使用同一掩模来执行所述两个接连的曝光工艺,仅需要进行一次掩模对准且不需要额外的对准并且会得到更好的图案叠加。
在图4中,在一些实施例中,进行第一显影工艺以移除第一介电材料层110的第一曝光部分110A及第二曝光部分110B,并形成第一介电图案111,从而实作对掩模MK1、MK2的图案转移。在一些实施例中,第一显影工艺包括施加显影剂溶液以至少溶解或移除第一曝光工艺E1及第二曝光工艺E2期间形成的暴露区(即,第一曝光部分110A及第二曝光部分110B),从而暴露出位于之下的接点104。举例来说,显影剂溶液包括四甲基氢氧化铵(tetramethyl ammonium hydroxide,TMAH)的溶液。在一些实施例中,接着在200摄氏度到250摄氏度下将经显影的第一介电图案111固化。在一些实施例中,可通过同一显影工艺同时移除第一曝光部分110A与第二曝光部分110B。在一些实施例中,在移除至少第一曝光部分110A及第二曝光部分110B之后,形成具有深度d4的沟槽开口TS1及具有深度d3的通孔开口VS1且形成具有厚度T2的第一介电图案111。在一些实施例中,在第一显影工艺期间可能出现膜损耗(film loss)且第一介电图案111的厚度T2小于第一介电材料层110的厚度T1。在一些实施例中,沟槽开口TS1及与沟槽开口TS1对应地在空间上连通的通孔开口VS1构成双重镶嵌开口(dual damascene opening)或镶嵌开口DS1。在一些实施例中,仅沟槽开口TS1中的一些连接通孔开口VS1中的一些,从而形成镶嵌开口DS1。在一些实施例中,沟槽开口TS1中的一些不连接通孔开口VS1中的一些。
在一些实施例中,除移除第一曝光部分110A及第二曝光部分110B以外,第一显影工艺可包括通过过量地移除第一曝光部分110A及第二曝光部分110B周围的第一介电材料层110对第一介电材料层110进行过度显影(over-developing)以形成如图4中所示的通孔开口VS1及沟槽开口TS1以及镶嵌开口DS1。在一些实施例中,与各向同性刻蚀工艺(isotropic etching process)相似,对第一介电材料层110进行过度显影会进一步加宽开口。另外,可包括固化工艺(curing process)以将第一介电材料层110固化,且对第一介电材料层110进行固化会使开口的侧壁倾斜。在一些实施例中,过度显影及固化使得通孔开口VS1被形成为具有深度d3及在水平方向x(垂直于厚度方向z)上的底部大小S3且沟槽开口TS1被形成为具有深度d4及在水平方向x上的底部大小S4。在一些实施例中,沟槽开口TS1、通孔开口VS1、及镶嵌开口DS1因歪斜的侧壁而锥形化(tapering)。在一些实施例中,通孔开口VS1的底部大小S3大于第一曝光部分110A的底部大小S1。在一些实施例中,沟槽开口TS1的底部大小S4大于第二曝光部分110B的底部大小S2。在一些实施例中,深度d3小于深度d1,而深度d4小于深度d2。在一些实施例中,深度的比率d4/d3可为约0.4~0.6。在一些实施例中,底部大小的比率S3/S1等于1.5或大于1.5。在一些实施例中,底部大小的比率S4/S2等于1.5或大于1.5。在一些实施例中,通孔开口VS1为圆形形状开口且通孔开口VS1的底部大小S3是通孔开口VS1的最大尺寸或直径。在一些实施例中,沟槽开口TS1是条状沟槽(striptrench)且沟槽开口TS1的底部大小S4是在长度方向(在图4中标记为方向x)上的最大尺寸或长度。
参照图5,在一些实施例中,在具有镶嵌开口DS1的第一介电图案111之上且在接点104上形成第一晶种金属层120。在一些实施例中,将第一晶种金属层120形成为与具有镶嵌开口DS1的第一介电图案111的轮廓共形,均匀地覆盖镶嵌开口DS1的侧壁及底表面以及第一介电图案111的顶表面。在一些实施例中,通过化学气相沉积(CVD)、物理气相沉积(physical vapor deposition,PVD)、原子层沉积(atomic layer deposition,ALD)、高密度等离子体化学气相沉积(high densityplasma CVD,HDPCVD)或其组合形成第一晶种金属层120。在一些实施例中,通过依序地沉积或溅镀与第一介电图案111及镶嵌开口DS1共形的钛层及铜层(图中未示出)形成第一晶种金属层120。在一个实施例中,第一晶种金属层120覆盖且接触接点104的经暴露表面(即,通孔开口VS1的底表面)。在一些实施例中,对于不连接通孔开口VS1的沟槽开口TS1,将第一晶种金属层120形成为共形地覆盖沟槽开口TS1的侧壁及底表面。沟槽开口TS1、通孔开口VS1、或镶嵌开口DS1的歪斜或倾斜的侧壁使得可实现更好且更均匀的台阶覆盖性(step coverage),尤其是对通过溅镀而形成的第一晶种金属层120的台阶覆盖性。因此,重布线层/结构的可靠性及电性能进一步得到提高。
参照图6,形成第一金属层130,第一金属层130填充满镶嵌开口DS1且位于第一介电图案111之上的第一晶种金属层120上。在一些实施例中,形成第一金属层130包括通过电镀(electroplating)形成铜层或铜合金层(图中未示出),所述铜层或铜合金层填充满镶嵌开口DS1且位于第一介电图案111之上的第一晶种金属层120上。然而,应知,本发明的范围并非仅限于以上所公开的材料及说明。在一些实施例中,对于不连接通孔开口VS1的沟槽开口TS1,将第一金属层130形成为填充满沟槽开口TS1。
在一些实施例中,由于在将金属层填充到开口中之前形成共形的晶种层,因此会确保随后形成的金属层得到更好的粘合。此外,共形的晶种层可帮助降低重布线层的电阻及改善所述重布线层的电性质。
参照图7,执行平坦化工艺(planarization process)以局部地移除位于第一介电图案111的顶表面111a上方的第一金属层130及第一晶种金属层120。在一些实施例中,移除位于第一介电图案111的顶表面111a上方的第一金属层130以及第一晶种金属层120,直到暴露出第一介电图案111的顶表面111a,并形成填充在镶嵌开口DS1内的第一晶种金属图案121及双重镶嵌重布线图案131。在一些实施例中,平坦化工艺可包括化学机械抛光(chemical-mechanical polishing,CMP)工艺、机械研磨工艺(mechanical grindingprocess)、飞切工艺(fly cutting process)、或回蚀工艺(etching back process)。在一些实施例中,平坦化工艺可包括化学机械抛光(CMP)工艺或飞切工艺。在一些实施例中,在平坦化之后,封装结构100内的第一重布线层RDL1的形成过程完成。在一些实施例中,在平坦化之后,保留在镶嵌开口DS1内的第一晶种金属层120及第一金属层130成为第一晶种金属图案121及双重镶嵌重布线图案131。在一些实施例中,第一晶种金属图案121位于镶嵌开口DS1内、夹置在双重镶嵌重布线图案131与镶嵌开口DS1之间、且共形地覆盖镶嵌开口DS1的侧壁及底表面。在一些实施例中,位于镶嵌开口DS1内的第一晶种金属图案121是作为整体形成,原因是第一晶种金属图案121是由同一层(第一晶种金属层120)形成。
在一些实施例中,第一重布线层RDL1包括至少第一介电图案111、第一晶种金属图案121、及双重镶嵌重布线图案131。第一重布线层RDL1电连接衬底102的接点104。在替代性实施例中,第一重布线层RDL1可包括多于一个介电图案以及包括迹线(traces)或连接线的各种类型的重布线图案。在示例性实施例中,第一重布线层RDL1的重布线图案的布局可形成集成扇出型(integrated fan-out,InFO)封装结构的扇出型布线(fan-out routing)。
在一些实施例中,位于镶嵌开口DS1内的双重镶嵌重布线图案131包括通孔部分132(位于通孔开口VS1内)及布线部分133(位于沟槽开口TS1内)。在一些实施例中,第一介电图案111的顶表面111a与双重镶嵌重布线图案131的顶表面131a共面且与双重镶嵌重布线图案131的顶表面131a齐平。在一些实施例中,对于不连接通孔开口VS1的沟槽开口TS1,在将填充满沟槽开口TS1的第一金属层平坦化之后,会获得保留在沟槽开口TS1中的迹线图案(图中未示出)。
在一些实施例中,在以上工艺步骤之后,不使用光刻工艺及刻蚀工艺便能完成第一重布线层,因而避免了光刻胶剥落或膨胀的问题。在一些实施例中,使用上述双重曝光工艺会提供更好的图案叠加及更好的图案对准且会形成包括通孔开口及沟槽开口的镶嵌开口。在一些实施例中,通过形成镶嵌开口,将金属层填充到镶嵌开口中的填充能力提高,且所述镶嵌开口与双重镶嵌重布线图案之间通过形成在其间的第一晶种金属图案121而具有更好的粘合。
图8至图14示意性地说明根据一些实施例的制作半导体封装的方法形成另一重布线层的各工艺的各种阶段。
参照图8,在一些实施例中,可在第一重布线层RDL1上形成第二介电材料层140。可遵循如图1至图7中所述的一些工艺或所有工艺来形成第一重布线层RDL1。在一些实施例中,可通过例如旋转涂布工艺等涂布工艺或者包括CVD工艺的沉积工艺来形成第二介电材料层140。在一些实施例中,第二介电材料层140可为正型感光性材料层。在一些实施例中,第二介电材料层140的材料可为正性感光性材料,包括聚酰亚胺、BCB、PBO、或任何其他适合的感光性聚合物材料或其他光刻胶材料。在一些实施例中,第二介电材料层140的材料可为正性光刻胶材料。在一些实施例中,第二介电材料层140的材料与第一介电材料层110的材料相同。在一些实施例中,第二介电材料层140的材料与第一介电材料层110的材料不同。
参照图9,对第二介电材料层140执行第三曝光工艺E3以形成第三曝光部分140A。在一些实施例中,使用具有第三图案PT3的掩模MK3执行第三曝光工艺E3。在一些实施例中,在第二介电材料层140的暴露于穿过开口PTO2的光的暴露区(示出为斑点区)中形成第三曝光部分140A。可在与在第一曝光工艺E1中阐述的条件相似或相同的条件下执行第三曝光工艺E3,且本文中不再对其予以赘述。在一些实施例中,以第三能量剂量执行第三曝光工艺E3,且将第三曝光部分140A形成为具有深度d5及在水平方向x(垂直于第二介电材料层140的厚度方向z)上的底部大小S5。在一些实施例中,第三曝光部分140A的深度d5实质上等于第二介电材料层140的厚度T3。在一些实施例中,第三曝光部分140A的潜在图案包括通孔开口图案。根据实施例,第三曝光部分140A的图案不同于第一曝光部分110A的图案。所述实施例旨在用于说明目的,而不旨在限制本发明的范围。
参照图10,对第二介电材料层140执行第四曝光工艺E4以形成第四曝光部分140B。在一些实施例中,使用具有第四图案PT4的掩模MK4执行第四曝光工艺E4。在一些实施例中,掩模MK3、MK4可指代同一掩模的不同部分或两个掩模。可在与在第二曝光工艺E2中阐述的条件相似或相同的条件下执行第四曝光工艺E4,且本文中不再对其予以赘述。在图10中,通过第四曝光工艺E4将第二介电材料层140局部地曝光,且在第二介电材料层140的暴露于穿过第四图案PT4的开口PTT2的光的暴露区(示出为斑点区)中形成第四曝光部分140B。在一些实施例中,以第四能量剂量执行第四曝光工艺E4,且将第四曝光部分140B形成为具有深度d6及在水平方向x(垂直于的厚度方向z)上的底部大小S6。在一些实施例中,第四曝光部分140B的深度d6小于第二介电材料层140的厚度T3。在一些实施例中,第四曝光部分140B的深度d6小于第三曝光部分140A的深度d5。在一个实施例中,第四能量剂量低于第三能量剂量。在一些实施例中,深度的比率d6/d5可为约0.4~0.6。在一些实施例中,第三曝光部分140A的位置与第四曝光部分140B的部份的位置交叠。在一些实施例中,第四曝光部分140B的潜在图案包括沟槽开口图案。
在一些实施例中,可将第三曝光工艺E3及第四曝光工艺E4视作另一双重曝光工艺。
在图11中,在一些实施例中,进行第二显影工艺以移除第二介电材料层140的至少第三曝光部分140A及第四曝光部分140B,并形成第二介电图案141。可使用与在第一显影工艺中阐述的条件或材料相似或相同的条件或材料执行第二显影工艺,且本文中不再对其予以赘述。在一些实施例中,可通过同一显影工艺同时移除第三曝光部分140A与第四曝光部分140B。在一些实施例中,在移除至少第三曝光部分140A及第四曝光部分140B之后,形成具有深度d8的沟槽开口TS2及具有深度d7的通孔开口VS2且形成具有厚度T4的第二介电图案141。在一些实施例中,在第二显影工艺期间可能出现膜损耗且第二介电图案141的厚度T4小于第二介电材料层140的厚度T3。在一些实施例中,沟槽开口TS2及与沟槽开口TS2对应地在空间上连通的通孔开口VS2构成双重镶嵌开口或镶嵌开口DS2。在一些实施例中,沟槽开口TS2中的一些连接通孔开口VS2中的一些。在一些实施例中,沟槽开口TS2中的一些不连接通孔开口VS2中的一些。
在一些实施例中,除移除第三曝光部分140A及第四曝光部分140B以外,第二显影工艺可包括通过过量地移除第三曝光部分140A及第四曝光部分140B周围的第二介电材料层140对第二介电材料层140进行过度显影以形成通孔开口VS2及沟槽开口TS2以及镶嵌开口DS2。在一些实施例中,对第二介电材料层140进行过度显影会进一步加宽开口。另外,可包括固化工艺,且对第二介电材料层140进行固化会使开口的侧壁倾斜。在一些实施例中,过度显影的加宽效应使得通孔开口VS2被形成为具有比第三曝光部分140A的底部大小S5宽的底部大小S7(在水平方向x上),且沟槽开口TS2被形成为具有比第四曝光部分140B的底部大小S6宽的底部大小S8(在水平方向x上在深度d8处测量)。在一些实施例中,在固化工艺之后,沟槽开口TS2、通孔开口VS2、及镶嵌开口DS2因歪斜的侧壁而锥形化。在一些实施例中,深度d7小于深度d5,而深度d8小于深度d6。在一些实施例中,深度的比率d8/d7可为约0.4~0.6。在一些实施例中,底部大小的比率S7/S5介于从1.1到2范围内。在一些实施例中,底部大小的比率S8/S6介于从1.1到2范围内。在一些实施例中,通孔开口VS2暴露出位于之下的双重镶嵌重布线图案131。在一些实施例中,通孔开口VS2为圆形形状开口且通孔开口VS2的底部大小S7是通孔开口VS2的最大尺寸或直径。在一些实施例中,沟槽开口TS2是条状沟槽且沟槽开口TS2的底部大小S8是在长度方向(在图11中标记为方向x)上的最大尺寸或长度。
参照图12,在一些实施例中,在具有镶嵌开口DS2的第二介电图案141之上形成第二晶种金属层150。在一些实施例中,将第二晶种金属层150形成为与具有镶嵌开口DS2的第二介电图案141的轮廓共形,均匀地覆盖镶嵌开口DS2的侧壁及底表面以及第二介电图案141的顶表面。在一些实施例中,通过依序地沉积或溅镀与第二介电图案141及镶嵌开口DS2共形的钛层及铜层(图中未示出)形成第二晶种金属层150。在一个实施例中,第二晶种金属层150覆盖且接触双重镶嵌重布线图案131的经暴露表面(即,通孔开口VS2的底表面)。沟槽开口TS2、通孔开口VS2、或镶嵌开口DS2的歪斜或倾斜的侧壁使得可实现对第二晶种金属层150的更好且更均匀的台阶覆盖性。因此,重布线层/结构的可靠性及电性能进一步得到提高。
参照图13,形成第二金属层160,第二金属层160填充满镶嵌开口DS2且位于第二介电图案141之上的第二晶种金属层150上。在一些实施例中,第二金属层160的材料包括铜或铜合金。在一些实施例中,第二金属层160的材料与第一金属层130的材料相同或不同。
参照图14,执行平坦化工艺以局部地移除位于第二介电图案141的顶表面141a上方的第二金属层160及第二晶种金属层150,且形成填充在镶嵌开口DS2内的第二晶种金属图案151及双重镶嵌重布线图案161。在一些实施例中,在平坦化之后,封装结构100中的第二重布线层RDL2的形成过程完成。在一些实施例中,第二晶种金属图案151位于镶嵌开口DS2内、夹置在双重镶嵌重布线图案161与镶嵌开口DS2之间、且共形地覆盖镶嵌开口DS2的侧壁及底表面。在一些实施例中,第二晶种金属图案151作为整体形成于镶嵌开口DS2内。在第一重布线层RDL1上设置第二重布线层RDL2且第二重布线层RDL2电连接第一重布线层RDL1。
在图14中,位于镶嵌开口DS2内的双重镶嵌重布线图案161包括通孔部分162(位于通孔开口VS2内)及布线部分163(位于沟槽开口TS2内)。
图15说明根据一些实施例的半导体封装中的重布线层的示意性布局俯视图。在图15中,示出多于一个双重镶嵌重布线图案161。在一些实施例中,一些双重镶嵌重布线图案161包括两个通孔部分162,所述两个通孔部分162通过位于其间的布线部分163来连接。然而,双重镶嵌重布线图案的图案或重布线层的布局不受本文所述实施例限制。
图16示意性地说明根据一些实施例的具有一个或多个重布线层的半导体封装。在一些实施例中,在形成第二重布线层RDL2之后,封装结构100可经历切割工艺(dicingprocess)且封装结构100被切成多个封装10。参照图16,封装10包括具有模塑化合物1560以及模塑在模塑化合物1560中的至少一个管芯1510及层间通孔(through inter-layervia,TIV)1520的封装子单元(package subunit)1500。在一些实施例中,第一重布线层RDL1设置在模塑化合物1560上以及管芯1510及层间通孔1520上。在一些实施例中,第一重布线层RDL1电连接管芯1510的接点接垫1512以及层间通孔1520。第二重布线层RDL2设置在第一重布线层RDL1上且电连接第一重布线层RDL1。除以经模塑的封装子单元1500取代衬底102以外,图16中所示结构可遵循图1至图14中所述工艺来形成。在一些实施例中,提供不具有层间通孔1520的经模的塑封装子单元1500。
图17至图20示意性地说明根据一些实施例的制作半导体封装的方法的各种阶段。参照图17,提供具有至少第一重布线层RDL1、第二重布线层RDL2、及第三重布线层RDL3的封装结构200。第三重布线层RDL3的形成过程与第一重布线层RDL1及第二重布线层RDL2的形成过程相似。在一些实施例中,可通过形成第三介电图案211、形成第三晶种金属图案220、及接着形成双重镶嵌重布线图案231来形成第三重布线层RDL3。
参照图18,在第三重布线层RDL3之上形成具有开口S的保护层240,以局部地暴露出双重镶嵌重布线图案231。
参照图19,在保护层240的开口S内的双重镶嵌重布线图案231的经暴露表面上形成导电元件250。
在一些实施例中,在第三重布线层RDL3上形成导电元件250之后,在图20中,封装结构200可经历切割工艺且封装结构200被切成多个封装20(仅示出一个)。
参照图21,封装20A包括至少第一重布线层RDL1、第二重布线层RDL2、及第三重布线层RDL3,且可遵循如图1至图14中所述工艺形成第一重布线层RDL1、第二重布线层RDL2、及第三重布线层RDL3。在一些实施例中,执行平坦化工艺以移除额外的第一金属层、第二金属层、或第三金属层包括刻蚀工艺。由于在第一重布线层RDL1、第二重布线层RDL2、及第三重布线层RDL3的形成期间执行回蚀工艺,因此双重镶嵌重布线图案131、161、231的顶表面131a、161a、231a低于第一介电图案111、第二介电图案141、第三介电图案211的顶表面111a、141a、211a。
根据本发明的一些实施例,一种半导体封装具有位于衬底上的至少重布线层。重布线层电连接衬底的接点。重布线层包括具有双重镶嵌开口的介电图案及设置在所述双重镶嵌开口内的重布线图案。重布线层包括晶种金属图案,所述晶种金属图案夹置在双重镶嵌开口与重布线图案之间。
根据本发明的替代性实施例,一种制作半导体封装的方法包括至少以下步骤。提供具有至少一个接点的衬底以及在所述衬底上形成重布线层。形成重布线层包括:在衬底之上形成介电材料层以及对所述介电材料层执行双重曝光工艺。接着执行显影工艺并在介电材料层中形成双重镶嵌开口。在双重镶嵌开口之上及介电材料层之上形成晶种金属层。在晶种金属层之上形成金属层。形成重布线图案,所述重布线图案位于双重镶嵌开口中且电连接所述至少一个接点。
根据本发明的替代性实施例,对所述介电材料层执行双重曝光工艺包括:执行第一曝光工艺以在所述介电材料层中形成具有第一深度的第一曝光部分,并执行第二曝光工艺以在所述介电材料层中形成具有第二深度的第二曝光部分,且所述第一深度大于所述第二深度。
根据本发明的替代性实施例,所述第一曝光部分的位置与所述第二曝光部分的位置交叠。
根据本发明的替代性实施例,执行显影工艺包括移除所述第一曝光部分及所述第二曝光部分并对所述介电材料层进行过度显影以形成所述双重镶嵌开口。
根据本发明的替代性实施例,对所述介电材料层执行双重曝光工艺包括:对所述介电材料层以第一能量剂量执行第一曝光工艺并以第二能量剂量执行第二曝光工艺,且所述第一能量剂量大于所述第二能量剂量。
根据本发明的替代性实施例,所述晶种金属层被形成为共形地覆盖所述双重镶嵌开口及覆盖所述介电材料层。
根据本发明的替代性实施例,形成位于所述双重镶嵌开口中的重布线图案包括:执行平坦化工艺以移除位于所述双重镶嵌开口外的所述金属层及所述晶种金属层。
根据本发明的替代性实施例,一种制作半导体封装的方法包括至少以下步骤。提供具有接点的衬底。在衬底之上形成第一介电材料层。对第一介电材料层执行第一双重曝光工艺。执行第一显影工艺并在第一介电材料层中形成暴露出接点的第一双重镶嵌开口。在第一双重镶嵌开口之上及第一介电材料层之上形成第一晶种金属层。在第一晶种金属层上形成第一金属层。在第一双重镶嵌开口中形成具有第一重布线图案的第一重布线层。在第一重布线层之上形成第二介电材料层。对第二介电材料层执行第二双重曝光工艺。执行第二显影工艺并在第二介电材料层中形成第二双重镶嵌开口。在第二双重镶嵌开口之上及第二介电材料层之上形成第二晶种金属层。在第二晶种金属层上形成第二金属层。在第二双重镶嵌开口中形成具有第二重布线图案的第二重布线层。
根据本发明的替代性实施例,对所述第一介电材料层执行第一双重曝光工艺包括:对所述第一介电材料层以第一能量剂量执行第一曝光工艺并以第二能量剂量执行第二曝光工艺,且所述第一能量剂量大于所述第二能量剂量。
根据本发明的替代性实施例,在所述第一双重镶嵌开口中形成具有第一重布线图案的第一重布线层包括:执行平坦化工艺以移除位于所述第一双重镶嵌开口外的所述第一金属层及所述第一晶种金属层,从而形成覆盖所述第一双重镶嵌开口的第一晶种金属图案及填充满所述第一双重镶嵌开口的所述第一重布线图案。
根据本发明的替代性实施例,对所述第二介电材料层执行第二双重曝光工艺包括对所述第二介电材料层以第三能量剂量执行第三曝光工艺并以第四能量剂量执行第四曝光工艺,且所述第三能量剂量大于所述第四能量剂量。
根据本发明的替代性实施例,在所述第二双重镶嵌开口中形成具有第二重布线图案的第二重布线层包括:执行平坦化工艺以移除位于所述第二双重镶嵌开口外的所述第二金属层及所述第二晶种金属层,以形成覆盖所述第二双重镶嵌开口的第二晶种金属图案及填充满所述第二双重镶嵌开口的所述第二重布线图案。
根据本发明的替代性实施例,一种制作重布线层的方法包括至少以下步骤。提供具有接点的衬底。在衬底上形成介电材料层。以第一能量剂量执行第一曝光工艺,以在介电材料层中形成具有第一深度的第一曝光部分。以第二能量剂量执行第二曝光工艺,以在介电材料层中形成具有第二深度的第二曝光部分。第一深度大于第二深度且第一能量剂量大于第二能量剂量。同时移除介电材料层的第一曝光部分与第二曝光部分,以分别形成通孔开口及沟槽开口。在介电材料层之上形成晶种金属层,所述晶种金属层覆盖通孔开口及沟槽开口。在晶种金属层之上形成金属层,所述金属层填充通孔开口及沟槽开口。
根据本发明的替代性实施例,所述制作重布线层的方法进一步包括:执行平坦化工艺,以移除位于所述通孔开口及所述沟槽开口外的所述金属层及所述晶种金属层。
根据本发明的替代性实施例,所述第一曝光部分的位置与所述第二曝光部分的位置交叠。
根据本发明的替代性实施例,同时移除所述介电材料层的所述第一曝光部分与所述第二曝光部分包括:执行显影工艺以移除所述第一曝光部分及所述第二曝光部分,并对所述第一曝光部分及所述第二曝光部分周围的所述介电材料层进行过度显影以形成所述通孔开口及所述沟槽开口。
根据本发明的替代性实施例,执行所述显影工艺进一步包括固化工艺。
根据本发明的替代性实施例,所述晶种金属层被形成为共形地覆盖所述通孔开口及所述沟槽开口。
根据本发明的替代性实施例,通过溅镀形成包含钛及铜的所述晶种金属层并通过电镀形成包含铜的所述金属层。
根据本发明的替代性实施例,所述晶种金属层被形成为覆盖被所述通孔开口暴露出的所述接点。
以上概述了若干实施例的特征,以使所属领域中的技术人员可更好地理解本发明的各个方面。所属领域中的技术人员应知,其可容易地使用本发明作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的及/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到,这些等效构造并不背离本发明的精神及范围,而且他们可在不背离本发明的精神及范围的条件下对其作出各种改变、代替、及变更。
Claims (33)
1.一种制作半导体封装的方法,其特征在于,包括:
提供具有至少一个接点的衬底;以及
在所述衬底上形成重布线层,其中形成所述重布线层包括:
在所述衬底之上形成介电材料层;
对所述介电材料层执行双重曝光工艺,其中执行所述双重曝光工艺包括执行第一曝光工艺以在所述介电材料层中形成第一曝光部分,并执行第二曝光工艺以在所述介电材料层中形成第二曝光部分;
执行显影工艺并在所述介电材料层中形成双重镶嵌开口,其中执行所述显影工艺并在所述介电材料层中形成所述双重镶嵌开口包括藉由施加显影剂溶液以对所述介电材料层进行过度显影以形成比所述第一曝光部分宽的通孔开口及比所述第二曝光部分宽的沟槽开口;
在所述双重镶嵌开口之上及所述介电材料层之上形成晶种金属层;
在所述晶种金属层之上形成金属层;以及
形成重布线图案,所述重布线图案位于所述双重镶嵌开口中且电连接所述至少一个接点。
2.根据权利要求1所述的制作半导体封装的方法,其中所述第一曝光部分形成为在所述介电材料层中具有第一深度,所述第二曝光部分形成为在所述介电材料层中具有第二深度,且所述第一深度大于所述第二深度。
3.根据权利要求1所述的制作半导体封装的方法,其中所述第一曝光部分的位置与所述第二曝光部分的位置交叠。
4.根据权利要求1所述的制作半导体封装的方法,其中对所述介电材料层执行所述双重曝光工艺包括:对所述介电材料层以第一能量剂量执行第一曝光工艺并以第二能量剂量执行第二曝光工艺,且所述第一能量剂量大于所述第二能量剂量。
5.根据权利要求1所述的制作半导体封装的方法,其中所述晶种金属层被形成为共形地覆盖所述双重镶嵌开口及覆盖所述介电材料层。
6.根据权利要求1所述的制作半导体封装的方法,其中形成位于所述双重镶嵌开口中的所述重布线图案包括:执行平坦化工艺以移除位于所述双重镶嵌开口外的所述金属层及所述晶种金属层。
7.一种制作半导体封装的方法,其特征在于,包括:
提供具有接点的衬底;以及
在所述衬底之上形成第一介电材料层;
对所述第一介电材料层执行第一双重曝光工艺以在所述第一介电材料层中形成第一曝光部分及第二曝光部分;
执行第一显影工艺并在所述第一介电材料层中形成暴露出所述接点的第一双重镶嵌开口,其中执行所述第一显影工艺并在所述第一介电材料层中形成所述第一双重镶嵌开口包括藉由施加显影剂溶液以对所述第一介电材料层进行过度显影以形成比所述第一曝光部分宽的通孔开口及比所述第二曝光部分宽的沟槽开口;
在所述第一双重镶嵌开口之上及所述第一介电材料层之上形成第一晶种金属层;
在所述第一晶种金属层上形成第一金属层;
在所述第一双重镶嵌开口中形成具有第一重布线图案的第一重布线层;
在所述第一重布线层之上形成第二介电材料层;
对所述第二介电材料层执行第二双重曝光工艺;
执行第二显影工艺并在所述第二介电材料层中形成第二双重镶嵌开口;
在所述第二双重镶嵌开口之上及所述第二介电材料层之上形成第二晶种金属层;
在所述第二晶种金属层上形成第二金属层;以及
在所述第二双重镶嵌开口中形成具有第二重布线图案的第二重布线层。
8.根据权利要求7所述的制作半导体封装的方法,其中对所述第一介电材料层执行所述第一双重曝光工艺包括:对所述第一介电材料层以第一能量剂量执行第一曝光工艺并以第二能量剂量执行第二曝光工艺,且所述第一能量剂量大于所述第二能量剂量。
9.根据权利要求7所述的制作半导体封装的方法,其中在所述第一双重镶嵌开口中形成具有所述第一重布线图案的所述第一重布线层包括:执行平坦化工艺以移除位于所述第一双重镶嵌开口外的所述第一金属层及所述第一晶种金属层,以形成覆盖所述第一双重镶嵌开口的第一晶种金属图案及填充满所述第一双重镶嵌开口的所述第一重布线图案。
10.根据权利要求7所述的制作半导体封装的方法,其中对所述第二介电材料层执行所述第二双重曝光工艺包括对所述第二介电材料层以第三能量剂量执行第三曝光工艺并以第四能量剂量执行第四曝光工艺,且所述第三能量剂量大于所述第四能量剂量。
11.根据权利要求7所述的制作半导体封装的方法,其中在所述第二双重镶嵌开口中形成具有所述第二重布线图案的所述第二重布线层包括:执行平坦化工艺以移除位于所述第二双重镶嵌开口外的所述第二金属层及所述第二晶种金属层,以形成覆盖所述第二双重镶嵌开口的第二晶种金属图案及填充满所述第二双重镶嵌开口的所述第二重布线图案。
12.一种制作重布线层的方法,其特征在于,包括:
提供具有接点的衬底;
在所述衬底上形成介电材料层;
以第一能量剂量执行第一曝光工艺,以在所述介电材料层中形成具有第一深度的第一曝光部分;
以第二能量剂量执行第二曝光工艺,以在所述介电材料层中形成具有第二深度的第二曝光部分,其中所述第一深度大于所述第二深度且所述第一能量剂量大于所述第二能量剂量;
同时移除所述介电材料层的所述第一曝光部分与所述第二曝光部分,以分别形成通孔开口及沟槽开口,其中同时移除所述介电材料层的所述第一曝光部分与所述第二曝光部分包括执行显影工艺以移除所述第一曝光部分与所述第二曝光部分,并藉由施加显影剂溶液以对所述第一曝光部分及所述第二曝光部分周围的所述介电材料层进行过度显影以形成比所述第一曝光部分大的所述通孔开口及比所述第二曝光部分大的所述沟槽开口;
在所述介电材料层之上形成晶种金属层,所述晶种金属层覆盖所述通孔开口及所述沟槽开口;以及
在所述晶种金属层之上形成金属层,所述金属层填充所述通孔开口及所述沟槽开口。
13.根据权利要求12所述的制作重布线层的方法,还包括执行平坦化工艺,以移除位于所述通孔开口及所述沟槽开口外的所述金属层及所述晶种金属层。
14.根据权利要求12所述的制作重布线层的方法,其中所述第一曝光部分的位置与所述第二曝光部分的位置交叠。
15.根据权利要求12所述的制作重布线层的方法,其中执行所述显影工艺还包括固化工艺。
16.根据权利要求12所述的制作重布线层的方法,其中所述晶种金属层被形成为共形地覆盖所述通孔开口及所述沟槽开口。
17.根据权利要求12所述的制作重布线层的方法,其中通过溅镀形成包含钛及铜的所述晶种金属层并通过电镀形成包含铜的所述金属层。
18.根据权利要求12所述的制作重布线层的方法,其中所述晶种金属层被形成为覆盖被所述通孔开口暴露出的所述接点。
19.一种制作半导体封装的方法,其特征在于,包括:
提供其中具有至少一个接点且其上具有介电材料层的衬底;
对所述介电材料层执行双重曝光工艺,包括依序执行第一曝光工艺以在所述介电材料层中形成第一曝光部分,并执行第二曝光工艺以在所述介电材料层中形成第二曝光部分;
执行显影工艺以溶解所述第一曝光部分及所述第二曝光部分,并对所述介电材料层进行过度显影以形成双重镶嵌开口,所述双重镶嵌开口具有比所述第一曝光部分宽的通孔开口及比所述第二曝光部分宽的沟槽开口;
在所述双重镶嵌开口之上及所述介电材料层之上形成晶种金属层;以及
形成填充在所述双重镶嵌开口中且电连接所述至少一个接点的金属图案。
20.根据权利要求19所述的制作半导体封装的方法,其中所述第一曝光部分形成为在所述介电材料层中具有第一深度,所述第二曝光部分形成为在所述介电材料层中具有第二深度,且所述第一深度大于所述第二深度。
21.根据权利要求19所述的制作半导体封装的方法,其中所述第一曝光部分的位置与所述第二曝光部分的位置交叠。
22.根据权利要求19所述的制作半导体封装的方法,其中以第一能量剂量执行所述第一曝光工艺并以第二能量剂量执行所述第二曝光工艺,且所述第一能量剂量大于所述第二能量剂量。
23.根据权利要求19所述的制作半导体封装的方法,其中所述通孔开口暴露出所述至少一个接点,且所述沟槽开口连接所述通孔开口。
24.根据权利要求23所述的制作半导体封装的方法,其中在所述双重镶嵌开口中形成所述金属图案包括形成位于所述通孔开口内的通孔部分以及形成位于所述沟槽开口内的布线部分。
25.根据权利要求19所述的制作半导体封装的方法,其中形成所述金属图案包括形成填充所述双重镶嵌开口的金属层,且执行平坦化工艺,以移除位于所述双重镶嵌开口外的所述金属层及所述晶种金属层。
26.一种制作内连结构的方法,其特征在于,包括:
提供具有接点及覆盖所述接点的介电材料层的衬底;
以第一能量剂量执行第一曝光工艺以在所述介电材料层中形成第一曝光部分;
以第二能量剂量执行第二曝光工艺以在所述介电材料层中形成第二曝光部分,其中所述第一能量剂量大于所述第二能量剂量;
执行显影工艺以溶解所述介电材料层的所述第一曝光部分及所述第二曝光部分,并在同一显影工艺中对所述介电材料层进行过度显影以形成比所述第一曝光部分宽的通孔开口及比所述第二曝光部分宽的沟槽开口;
形成在所述介电材料层之上且覆盖所述通孔开口及所述沟槽开口的晶种金属层;以及
形成在所述晶种金属层上且填充在所述通孔开口及所述沟槽开口内的金属图案。
27.根据权利要求26所述的制作内连结构的方法,其中执行所述显影工艺还包括固化工艺。
28.根据权利要求26所述的制作内连结构的方法,其中所述晶种金属层被形成为共形地覆盖所述通孔开口及所述沟槽开口。
29.根据权利要求28所述的制作内连结构的方法,其中通过溅镀形成包含钛及铜的所述晶种金属层。
30.根据权利要求28所述的制作内连结构的方法,其中所述晶种金属层被形成为覆盖被所述通孔开口暴露出的所述接点。
31.根据权利要求26所述的制作内连结构的方法,其中形成所述金属图案包括形成填充所述通孔开口及所述沟槽开口的金属层,且执行平坦化工艺,以移除位于所述通孔开口外的所述金属层及所述晶种金属层。
32.根据权利要求31所述的制作内连结构的方法,其中通过电镀形成包含铜的所述金属层。
33.根据权利要求26所述的制作内连结构的方法,其中所述第一曝光部分被形成在与所述第二曝光部分的位置交叠的位置。
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