CN109427714A - 半导体封装及其制造方法 - Google Patents

半导体封装及其制造方法 Download PDF

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Publication number
CN109427714A
CN109427714A CN201810554623.1A CN201810554623A CN109427714A CN 109427714 A CN109427714 A CN 109427714A CN 201810554623 A CN201810554623 A CN 201810554623A CN 109427714 A CN109427714 A CN 109427714A
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layer
conductive layer
patterned conductive
semiconductor packages
encapsulated
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CN109427714B (zh
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颜尤龙
陈光雄
梁心丞
徐沛妤
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

本发明揭示一种半导体封装，其包含裸片及电连接到所述裸片的经图案化导电层。所述经图案化导电层包含连接垫及迹线。所述半导体封装进一步包含囊封所述裸片及所述经图案化导电层的囊封层。所述半导体封装，其进一步包含安置在所述连接垫上的电连接元件及包含围绕所述电连接元件的侧壁部分的保护层。

Description

半导体封装及其制造方法
技术领域
本发明大体来说涉及半导体封装及其制造方法。
背景技术
在半导体装置封装中，在衬底与模塑料之间可存在接口。在热处理期间，衬底与模塑料之间的相应热膨胀系数(CTE)的失配可导致半导体装置封装件翘曲，且因此在热处理期间衬底可能与模塑料分离。
在半导体装置封装中，可在安装焊料球之前在衬底上设置保护层。可将保护层的部分移除以暴露衬底的连接垫，使得其可接纳用于外部连接的焊料球。此方法还可能涉及用于去除保护层的额外工艺，此会增加用于制造半导体装置封装的成本或处理时间。
发明内容
在一些实施例中，根据一个方面，半导体封装包含裸片及电连接到裸片的经图案化导电层，经图案化导电层包含连接垫及迹线。半导体封装进一步包含囊封裸片及经图案化导电层的囊封层，以及安置在连接垫上的电连接元件。半导体封装进一步包含保护层，其包含围绕电连接元件的侧壁部分。
在一些实施例中，根据另一方面，制造半导体封装的方法包含在载体上形成包含连接垫的经图案化导电层，及将裸片电连接到经图案化导电层。所述方法进一步包含形成囊封裸片及经图案化导电层的囊封层，以及去除载体以暴露经图案化导电层的连接垫。所述方法进一步包含在连接垫上形成涂覆层，在涂覆层上形成电连接元件，及加热涂覆层以在电连接元件上形成保护层。保护层包含围绕电连接元件的侧壁部分。
附图说明
当与附图一起阅读时可自以下详述描述最佳理解本发明的方面。应注意，各种特征可能未按比例绘制，且各种特征的尺寸可出于论述的清楚起见而任意增大或减小。
图1A为说明根据本发明的一些实施例的半导体裸片封装的横截面图的示意图。
图1B为说明根据本发明的一些实施例的半导体裸片封装的横截面图的示意图。
图1C为说明根据本发明的一些实施例的半导体裸片封装的横截面图的示意图。
图1D为说明根据本发明的一些实施例的半导体裸片封装的横截面图的示意图。
图1E为说明根据本发明的一些实施例的半导体裸片封装的横截面图的示意图。
图1F为说明根据本发明的一些实施例的半导体裸片封装的横截面图的示意图。
图2A为说明根据本发明的一些实施例的半导体裸片封装的横截面图的示意图。
图2B为说明根据本发明的一些实施例的半导体裸片封装的横截面图的示意图。
图3A、图3B、图3C、图3D、图3E、图3F、图3G、图3H、图3I及图3J说明根据本发明的一些实施例的制造半导体封装的方法。
图4A及图4B说明根据本发明的一些实施例制造半导体封装的方法的一些阶段。
图5A、图5B及图5C说明根据本发明的一些实施例的制造半导体封装的方法。
图5D说明根据本发明的一些实施例的制造半导体封装的方法的阶段。
图6为说明半导体封装的一些实施例的示意图。
图7为说明半导体封装的比较实例的示意图。
具体实施方式
下面详细论述本发明的实施例及其用途。然而，应了解，实施例阐明可在各种各样的具体环境中体现的许多适用概念。应理解，以下公开内容提供实实施各种实施例的不同特征的许多不同实施例或实例。出于论述目的下文描述组件及配置之特定实例。当然，这些仅为实例且并不意欲为限制性。
除非另有规定，例如“在…上面”、“在…下面”、“上”、“左”、“右”、“下”、“顶部”、“底部”、“垂直”、“水平”、“侧面”、“较高”、“下部”、“上部”、“在…上方”、“在…下方”等等术语的空间描述在本文中是相对于对应图中所展示的定向使用。应理解，本文中所使用的空间描述是仅出于说明的目的，且本文中所描述的结构的实际实施方案可以任一定向或方式进行空间布置，只要此布置不背离本发明的实施例的优点。
下面使用特定语言揭示附图中说明的实施例或实例。然而，应理解，实施例及实例并不意欲为限制性的。如所属领域的技术人员通常会想到的，所揭示的实施例的任何变更及修改以及在此文件中揭示的原理的任何进一步应用都在本发明的范围内。
另外，本发明可在各种实例中重复参考编号及/或字母。此重复是出于简约及清楚的目的且自身并不指示本文中所论述的各种实施例及/或配置之间的关系。
本发明提供了一种封装方法及封装结构。在本文中所描述的方法及结构中，可省略电介质材料在衬底上的层压，且因此可降低用于制造封装结构的成本。在本发明中揭示的方法的实施例可增加衬底合格率且还可提供封装的减小的总厚度。另外，可增强使用本发明中揭示的方法制造的封装的可靠性。
图1A为说明根据本发明的一些实施例的半导体裸片封装的横截面图的示意图。如图1A所展示，半导体裸片封装100包括经图案化导电层4、焊接材料5、导电柱6、裸片7、囊封层8、保护层10及电连接元件11。
囊封层8囊封经图案化导电层4、焊接材料5、导电柱6、裸片7、保护层10的至少部分以及电连接元件11的至少部分。裸片7的有源表面电连接到导电柱6。尽管未说明，但在一些实施例中，一或多个导电垫(图1未展示)可安置在裸片7的有源表面上，用于连接到导电柱6。
焊接材料5安置在导电柱6上。焊接材料5安置在经图案化导电层4与导电柱6之间。经图案化导电层4安置在焊接材料5上。经图案化导电层4可包含一或多个连接垫及/或一或多个迹线。
电连接元件11安置在经图案化导电层4上以供外部连接。电连接元件11可包含例如与焊接材料5中所包含的材料相似或相同的材料。电连接元件11的部分被囊封层8囊封。电连接元件11的部分嵌入在囊封层8中。电连接元件11可包含安置在囊封层8中的第一部分及通过囊封层8(例如从其突出)暴露的圆形、弯曲、球面或球形的第二部分。
保护层10覆盖囊封层8的表面。保护层10包含部分101、部分102及侧壁部分103。部分101覆盖囊封层8的上表面。保护层10的部分101具有在约5微米(“μm”)到约15μm范围内的厚度，或在约2μm到约15μm范围内的厚度。
侧壁部分103覆盖囊封层8的表面。侧壁部分103可包含部分102的侧表面。侧壁部分103可为与电连接元件11接触的保护层10的部分。侧壁部分103可具有弯曲或弧形(例如，与电连接元件11的第二部分互补的弯曲形状)。在其它实施例中，侧壁部分103可为与电连接元件11互补的任何形状。侧壁部分103围绕电连接元件11的第二部分。侧壁部分103围绕电连接元件11。保护层10的侧壁部分103安置于在囊封层8内的电连接元件11的第一部分上面且在由囊封层8暴露的电连接元件11的第二部分的至少部分下面。
保护层10的部分102的至少部分被囊封层8围绕。保护层10的部分102的至少部分嵌入在囊封层8中。部分102可安置在部分101与侧壁部分103之间。部分102的上表面可为具有部分101的上表面的基本共面。
图1B为说明根据本发明的一些实施例的半导体裸片封装的横截面图的示意图。图1B中所展示的半导体裸片封装120与图1A中所展示的半导体裸片封装100类似，除了实施保护层10a而不是保护层10之外。保护层10a类似于保护层10但省略了保护层10的部分101(例如，囊封层8的上表面的至少部分从保护层10a暴露)。在一或多个实施例中，部分102的上表面与囊封层8的上表面基本上共面。
图1C为说明根据本发明的一些实施例的半导体裸片封装的横截面图的示意图。在图1C所展示的半导体裸片封装140类似于图1A中所展示的半导体裸片封装100，除了抗氧化导电层14安置在经图案化导电层4上除外。抗氧化导电层14安置在经图案化导电层4与电连接元件11之间。抗氧化导电层14安置在经图案化导电层4与保护层10之间。抗氧化导电层14包含从包含在电连接元件11中的材料不同的材料(例如，包含无电镀镍浸金(ENIG)或其它合适的材料)。
图1D为说明根据本发明的一些实施例的半导体裸片封装的横截面图的示意图。图1D中所展示的半导体裸片封装160与图1C中所展示的半导体裸片封装140相似，除了省略了安置在经图案化导电层4与电连接元件11之间的抗氧化导电层14的部分(例如，电连接元件11与经图案化导电层4直接接触)之外。抗氧化导电层14包含与包含在电连接元件11中的材料相似，或相同的材料(例如，包含例如锡(Sn)、另一金属或其它合适材料的焊接材料)。
图1E为说明根据本发明的一些实施例的半导体裸片封装的横截面图的示意图。在图1E中所展示的半导体裸片封装180类似于图1A中所展示的半导体裸片封装100，除了保护层10的部分102的上表面与保护层10的部分101的上表面基本上不共面。另外，保护层10的部分102的上表面安置在囊封层8的上表面下面(例如，自其凹陷)。保护层10的部分101及102具有在约5μm到约15μm范围内的厚度，或在约2μm到约15μm的范围内的厚度。
图1F为说明根据本发明的一些实施例的半导体裸片封装的横截面图的示意图。图1F中所展示的半导体裸片封装190类似于图1B所展示的半导体裸片封装120，除了保护层10的部分102与囊封层8的上表面基本上不共面，且凹入在囊封层8的上表面的下面。保护层10的部分102具有在约5μm到约15μm范围内的厚度的，或在约2μm到约15μm的范围内的厚度。
图2A为说明根据本发明的一些实施例的半导体裸片封装的横截面图的示意图。图2A说明图1A中所展示的虚线框A中的结构的放大图。如图2A中所展示，电连接元件11包含可分别对应于上面所描述第一部分与第二部分的部分11a及部分11b。部分11a嵌入在囊封层8中且保护层10(例如，保护层10的侧壁部分103)经安置抵靠部分11b且围绕部分11b的部分(例如，下部部分)。在图2A中所展示的实施例中，部分11b为弯曲的，且经成形为球的至少部分(例如，为基本上球形状)。经图案化导电层4包括在其上的电连接元件11设置连接垫41。
如图2A中所展示，部分11b与经图案化导电层4之间(例如，部分11b的顶部部分与经图案化导电层4的顶部表面之间)的最大距离被称作为距离X，且侧壁部分103与经图案化导电层4之间(例如，在侧壁部分103的顶部部分与经图案化导电层4的顶部表面之间)的最大距离被称作为距离Y。在一些实施例中，距离Y小于或等于距离X的一半，例如小于或等于约三分之一、或小于或等于约四分之一。如将在下文参考图3J所论述，可在通过电连接元件11推开连接垫41上的涂覆层之后可形成侧壁部分103。距离Y可取决于在制造期间安置在囊封层8上的涂覆层材料的量。
如果侧壁部分103覆盖太多电连接元件11的外表面，那么电连接元件11与外部组件之间的电连接可能会失败，或可为次优的。在一些实施例中，在制造期间安置在囊封层8上的涂覆材料的量经选择，使得距离Y小于或等于约距离X的一半。
图2B为说明根据本发明的一些实施例的半导体裸片封装的横截面图的示意图。图2B提供根据本发明的一些实施例的图1A中所展示的矩形A中的结构的放大图。在图2B中所展示的实施例中，部分11b为弯曲的，且经成形为球的至少部分(例如，基本为半球形状)。部分11b与经图案化导电层4之间(例如，部分11b的顶部部分与经图案化导电层4的顶部表面之间)的最大距离被称作为距离X且侧壁部分103与经图案化导电层4之间(例如，侧壁部分103的顶部部分与经图案化导电层4的顶部表面之间)的最大距离被称作为距离Y。在一些实施例中，距离Y小于或等于距离X的一半。在一些实施例中，如下面所论述，在制造期间安置在囊封层8上的涂覆层材料的量经选择使得距离Y小于或等于距离X的约一半。
图3A到图3J说明根据本发明的一些实施例的制造半导体封装的方法。如图3A中所展示，提供载体1，且导电层2安置在载体1的上表面上。导电层2可包含例如铜(Cu)的导电材料、其它金属或其它合适的材料。如图3B中所展示，在导电层2上提供(例如形成)经图案化光致抗蚀剂层3。经图案化光致抗蚀剂层3可包含使用层压工艺及曝光工艺形成的干膜光致抗蚀剂。
如图3C中所展示，导电材料被电镀在未被经图案化光致抗蚀剂层3覆盖的导电层2的部分上，以便产生经图案化导电层4'。电镀在导电层2上的导电材料可包含与导电层2中所包含的材料相似或相同的材料。在所述状况下，导电层2与经图案化导电层4'之间可基本上不存在接口。
如图3D中所展示，去除经图案化光致抗蚀剂层3。如图3E中所展示，在经图案化导电层4'上提供焊接材料5，且在焊接材料5上提供导电柱6。通过焊接材料5及导电柱6将裸片7附接在经图案化导电层4'上。如在图3E中所展示，经图案化导电层4'包含连接垫41及迹线42。如在图3F中所展示，裸片7、经图案化导电层4'、焊接材料5及导电柱6由囊封层8囊封。在形成囊封层8之后，封装结构非常适合于承受人或机器的处理，即使没有载体1。如图3G中所展示，载体1被移除。
如图3H中所展示，通过蚀刻工艺去除导电层2。蚀刻工艺去除导电层2及经图案化导电层4'的部分。如此刻蚀的经图案化导电层4'在下文中将被称作为经图案化导电层4。经图案化导电层4的上表面从囊封层8的上表面凹陷，且因此经图案化导电层4及囊封层8界定凹部9。即，经图案化导电层4的上表面经安置成低于囊封层8的上表面。如下面将要论述，电连接元件11可安置在凹部9中。电连接元件11因此可被凹部9约束，且这可有助于防止电连接元件11在回流过程中不期望地渗出或流动(例如，溢流)。电连接元件11的渗出或溢流可能导致半导体装置封装中的不期望的短路。
如图3I中所展示，将涂覆材料安置在图案化的导电层4上，且因此形成涂覆层10'。在图3I中所展示的实施例中，涂覆层10'覆盖连接垫41及迹线42两者，且覆盖囊封层8的表面。涂覆层10'可包含硬化剂，助焊剂及/或溶剂。在一些实施例中，涂覆层10'可包含硬化剂，例如环氧树脂或双酚环氧树脂。在一些实施例中，涂覆层10'可包含助焊剂，例如羧酸及/或松香焊剂。在一些实施方案中，涂覆层10'可包含溶剂，例如聚乙二醇或1-甲基-2-吡咯烷酮(NMP)。
如图3J中所展示，电连接元件11形成或安置在涂覆层10'上。在一些实施例中，电连接元件11可包含焊接材料，例如锡，另一金属或其它合适的材料。在回流操作或加热操作之后，涂覆层10'的助焊剂及溶剂经蒸发或以其它方式基本上被消除。在回流操作或加热操作中，电连接元件11推开连接垫41上的涂覆层10'的涂覆材料并接合到连接垫41，且因此包含被推开的涂覆材料的至少一些的侧壁部分103经形成以围绕电连接元件11。在回流操作或加热操作之后，电连接元件11连接到连接垫41。在回流操作或加热操作之后，涂覆层10'的剩余部分可构成包含侧壁部分103的保护层10，所述侧壁部分可包含涂覆层10'的硬化剂。可对图3J中所展示的结构执行单个化操作以形成半导体裸片封装，所述半导体裸片封装与参考图1A所说明及所描述的半导体裸片封装100相似或相同。
在回流操作或加热操作中，在涂覆层10'的助焊剂和溶剂中的至少一些挥发之后，涂覆层10'被硬化以形成保护层10。因此，保护层10可选择性地包含例如环氧树脂或双酚环氧树脂的硬化剂，且可省略助焊剂及溶剂的至少一些。保护层10具有在覆盖层10'(例如，紧在回流操作或加热操作之前的覆盖层10')的厚度的约70％到约90％的范围内的厚度。在一些实施例中，安置在囊封层8上的保护层10具有在约5μm到约15μm的范围内的厚度，或在约2μm到约15μm的范围内的厚度。围绕电连接元件11形成的侧壁部分103可增强电连接元件11与连接垫41之间的附接。因此，可减小电连接元件11无意中从连接垫41脱落的概率。
图4A及图4B说明根据本发明的一些实施例制造半导体封装的方法的一些阶段。。在图4A中及在图4B中所说明的制造阶段可在图3A、图3B、图3C、图3D、图3E、图3F、图3G及图3H中所展示的制造阶段之后实施。
参考图4A，在经图案化导电层4上(例如，在由经图案化导电层4与囊封层8界定的凹部中)形成涂覆层13。如在图3I中所展示，涂覆层13类似于涂覆层10'，除了涂覆层13经形成以选择性地覆盖经图案化导电层4，其包含连接垫41及迹线42。囊封层8由涂覆层13暴露。涂覆层13不覆盖囊封层8。
参照图4B，电连接元件11形成或安置在涂覆层13上。在一些实施例中，电连接元件11可包含焊接材料，例如锡，另一种金属或其它合适的材料。在涂覆层13上形成电连接元件11之后，执行回流操作或加热操作。在回流操作或加热操作之后，涂覆层13的助焊剂及溶剂蒸发或以其它方式基本上消除。在回流操作或加热操作中，电连接元件11推开连接垫41上的涂覆材料且接合到连接垫41，且因此侧壁部分103经形成以围绕电连接元件11。类似于上面参照图3J所描述的过程，在回流操作或加热操作之后，电连接元件11连接到连接垫41，且形成包含涂覆层13的硬化剂的保护层。可对图4B中所展示的结构执行单个化操作以形成与如参考图1B所说明及所描述的半导体裸片封装120相似或相同的半导体裸片封装。
图5A、图5B及图5C说明根据本发明的一些实施例的制造半导体封装的方法。图5A中所展示的制造阶段为可在图3H中所展示的制造阶段之后执行的阶段。在图5A中所展示的制造阶段中，抗氧化导电层14形成在经图案化导电层4上(例如，在经图案化导电层4的连接垫41上)。在一些实施方案中，抗氧化导电层14包含焊接材料(其可包含锡)、无电镀镍浸金或其它合适的材料。如图5B中所展示，涂覆层10'形成在抗氧化导电层14上。在图5B中所展示的实施例中，覆盖层10'覆盖抗氧化导电层14及囊封层8的表面两者。尽管在附图中未描绘，但在一些实施例中，涂覆层10'可选择性地安置在抗氧化导电层14上且可使囊封层8的至少部分暴露。
如图5C中所展示，电连接元件11形成或安置在抗氧化导电层14上。在回流操作或加热操作中，电连接元件11推开抗氧化导电层14上面的涂覆层材料并接合到抗氧化导电层14，所述抗氧化导电层可包含无电镀镍浸金或其它合适的材料，且因此侧壁部分103经形成以围绕电连接元件11。在回流操作或加热操作之后，电连接元件11连接到连接垫41，且形成包含涂覆层10'的硬化剂的保护层10。可对如图5C中所展示的结构执行单个化操作以形成与参考图1C所说明及所描述的半导体裸片封装140相似或相同的半导体裸片封装。
图5D说明根据本发明的一些实施例的制造半导体封装的方法的阶段。图5D中所说明的制造阶段可例如在图5A及图5B中所说明的制造阶段之后实施。图5D中所说明的阶段可例如实施为图5C中所说明的制造阶段的替代方案。
如图5D中所展示，电连接元件11经形成或安置在经图案化导电层4上。在回流操作或加热操作中，电连接元件11推开经图案化导电层4上面的涂覆层材料并接合到经图案化导电层4，且因此侧壁部分103经形成以围绕电连接元件11。在回流操作或加热操作之后，电连接元件11连接到连接垫41，且形成包含涂覆层10'的硬化剂的保护层10。可在如图5D中所展示的结构上执行单个化操作以形成与如参考图1D所说明及所描述的半导体裸片封装160相似或相同的半导体裸片封装。
图6为说明半导体封装600的一些实施例的示意图。图6中所展示的半导体封装600包含囊封层601、半导体裸片602、经图案化导电层603、衬底604、一或多个导电柱605及一或多个电连接件606。
衬底604包含与囊封层601中所包含的材料相似或相同的材料。在一些实施例中，衬底604包含与包含在囊封层601中的材料不同的材料。衬底604包含具有填充物的环氧树脂。衬底604包含相对较硬材料，其可为厚材料，且其厚度被设置为大于大约110μm以减少或避免破裂或其它可靠性问题。一或多个导电柱605形成在衬底604中用于半导体裸片602与一或多个电连接606之间的电连接。相应地，一或多个导电柱605的高度可为至少约100μm，或更高，以帮助提供一或多个电组件606与经图案化金属层603之间的电连接。载体可从半导体装置600的制造过程至少一些阶段省略。
图7为说明比较半导体封装700的示意图。图7中所展示的半导体封装包含囊封层701、半导体裸片702、经图案化导电层703、电介质层704及一或多个电连接件705。电介质层704具有等于或大于大约40μm的厚度。电介质层704包含不同于囊封层701中所包含的材料的材料。电介质层704包含电介质材料，例如(但不限于)聚酰亚胺(PI)、预浸料或预浸渍复合纤维(pp)、味之素(Ajinomoto)增层膜(ABF)、FR-4等级材料、焊料掩模及/或其它合适的材料。介电层704可用作经图案化导电层703的保护层。介电层704可为吸湿性。介电层704可能倾向于吸收湿气，这可能导致可靠性问题。一或多个电连接件705安置在电介质层704上且电连接到经图案化导电层703。
由于囊封层701与介电层704之间的CTE不匹配，在热循环期间可能容易发生翘曲。此外，在囊封层701与介电层704之间的边界或接口上可能发生分层，其包含不同的材料。本文中描述的实施例可改进这些缺陷。
如本文中所使用，除非上下文另有明确指示，否则单数术语“一(a)”、“一(an)”及“所述”可包含复数对象。在一些实施例的描述中，提供在另一组件“上”、“上面”或“上方”的组件可囊括其中后一组件直接在前一组件上(例如，物理接触)的状况，以及其中一或多个介入组件可位于前一组件与后一组件之间的状况。
如本文中所使用，术语“基本上”、“大约”及“约”用于描述及考虑小变化。在结合事件或情形使用时，所述术语可是指其中事件或情形明确发生的情况以及其中事件或情形接近于发生的情况。举例来说，当结合数值使用时，所述术语可指小于或等于所述数值±10％的变化范围，例如小于或等于±5％，小于或等于±4％，小于或等于±3％，小于或等于±2％，小于或等于±1％，小于或等于±0.5％，小于或等于±0.1％或小于或等于±0.05％。例如，关于两个值的术语“约”或“基本上”相等可是指这两个值的比率在0.9与1.1之间(包含0.9与1.1)的范围内。
另外，数量、比率及其它数值有时在本文中以范围格式呈现。应理解，此范围格式是出于便利及简洁起见而使用且应灵活地理解为包含明确规定为范围的限制的数值，而且还包含所述范围内囊括的所有个别数值或子范围，犹如每一数值及子范围是明确规定。
如果两个表面之间的位移不大于5μm，不大于2μm，不大于1μm或不大于0.5μm，那么两个表面可被认为共面或基本上共面。
虽然已参考本发明的特定实施例描述并说明本发明，但这些描述及说明并不限制本发明。所属领域的技术人员应理解，在不背离如随附权利要求书所界定的本发明的真实精神及范围的情况下，可做出各种改变且可替代等效物。说明可不必按比例绘制。由于制造过程及容限，因此本发明中的精巧呈现与实际设备之间可存在差异。可存在本发明的未具体说明的其它实施例。说明书及图式应视为说明性而非限制性。可进行修改以使特定情况、材料、物质组合物、方法或过程适应本发明的目的、精神及范围。所有此些修改意欲属于随附的权利要求书的范围内。虽然已参考以特定次序执行的特定操作来描述本文中所揭示的方法，但应理解，可在不背离本发明的教示的情况下将这些操作组合，细分或重新排序以形成等效方法。因此，除非本文中特别指明，否则操作的次序及分组并非本发明的限制。

Claims (23)

1.一种半导体封装，其包括：
裸片；
电连接到所述裸片的经图案化导电层，所述经图案化导电层包括连接垫及迹线；
囊封层，其囊封所述裸片及所述经图案化导电层；
电连接元件，其安置在所述连接垫上；及
保护层，其包括围绕所述电连接元件的至少部分的侧壁部分。
2.根据权利要求1所述的半导体封装，其中所述电连接元件包括第一部分及第二部分，且其中所述第一部分嵌入在所述囊封层且所述第二部分被所述保护层围绕。
3.根据权利要求2所述的半导体封装，其中所述第二部分具有半球形状。
4.根据权利要求2所述的半导体封装，其中：
所述第二部分与所述经图案化导电层之间的第一最大距离为距离X；
所述侧壁部分与所述经图案化导电层之间的第二最大距离为距离Y；及
所述距离Y小于或等于所述距离X的一半。
5.根据权利要求1所述的半导体封装，其中所述保护层经安置抵靠所述电连接元件。
6.根据权利要求1所述的半导体封装，其中所述保护层安置在所述经图案化导电层上。
7.根据权利要求1所述的半导体封装，其中所述迹线被所述保护层覆盖且所述囊封层的至少部分从所述保护层暴露。
8.根据权利要求1所述的半导体封装，其中所述迹线及所述囊封层被所述保护层覆盖。
9.根据权利要求8所述的半导体封装，其中安置在所述囊封层上面的所述保护层具有在约2微米(μm)至约15μm范围内的厚度。
10.根据权利要求1所述的半导体封装，其中
所述经图案化导电层具有第一上表面且所述囊封层具有第二上表面，及
所述第二上表面不与所述第一上表面共面。
11.根据权利要求1所述的半导体封装，其中所述保护层包括环氧树脂或双酚环氧树脂。
12.根据权利要求1所述的半导体封装，其进一步包括设置在所述连接垫与所述电连接元件之间的抗氧化导电层。
13.根据权利要求1所述的半导体封装，其进一步包括安置在所述迹线上的抗氧化导电层。
14.根据权利要求13所述的半导体封装，其中所述抗氧化导电层包含锡(Sn)或无电镀镍浸金(ENIG)。
15.一种制造半导体装置的方法，其包括：
在载体上形成包括连接垫的经图案化导电层；
将裸片电连接到所述经图案化导电层；
形成囊封所述裸片及所述经图案化导电层的囊封层；
移除所述载体以暴露所述经图案化导电层的所述连接垫；
在所述连接垫上形成涂覆层；
在所述涂覆层上形成电连接元件；及
加热所述涂覆层以形成保护层，所述保护层包括围绕所述电连接元件的侧壁部分。
16.根据权利要求15所述的方法，其中所述涂覆层包括助焊剂及溶剂。
17.根据权利要求16所述的方法，其中所述助焊剂包括羧酸或松香焊剂中的至少一个。
18.根据权利要求16所述的方法，其中所述溶剂包括聚乙二醇或1-甲基-2-吡咯烷酮(NMP)中的至少一个。
19.根据权利要求16所述的方法，其中加热所述涂覆层包括使所述助焊剂及所述溶剂蒸发以硬化所述涂覆层以形成所述保护层。
20.根据权利要求19所述的方法，其中所述保护层的厚度在所述涂覆层的厚度的约70％到约90％的范围内。
21.根据权利要求15所述的方法，其进一步包括：
在所述连接垫与所述电连接元件之间形成抗氧化导电层。
22.根据权利要求15所述的方法，其中所述经图案化导电层包括迹线，且所述方法进一步包括：
在所述经图案化导电层的所述迹线上形成所述涂覆层。
23.根据权利要求15所述的方法，其中所述涂覆层包括环氧树脂或双酚环氧树脂中的至少一个。
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