CN205944071U - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN205944071U
CN205944071U CN201620733042.0U CN201620733042U CN205944071U CN 205944071 U CN205944071 U CN 205944071U CN 201620733042 U CN201620733042 U CN 201620733042U CN 205944071 U CN205944071 U CN 205944071U
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liner
conductive
conductive projection
semiconductor device
trace
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李琼延
李泰勇
新闵哲
欧瑟门
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Anrely Technology Singapore Holdings Pte Ltd
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Imark Technology Co
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Abstract

半导体装置。作为非限制性实例，本实用新型的各种方面提供一种半导体装置，所述半导体装置包括：衬底，其包含介电层；至少一个导电迹线和导电凸块衬垫，其形成于所述介电层的一个表面上；和保护层，其覆盖所述至少一个导电迹线和导电凸块衬垫，所述至少一个导电凸块衬垫具有通过所述保护层暴露的一端；和半导体裸片，其电连接到所述衬底的所述导电凸块衬垫。

Description

半导体装置
技术领域
本实用新型涉及半导体装置。
背景技术
目前半导体装置和用于制造半导体装置的方法是不适当的，例如，导致过低的敏感度、过多的成本、降低的可靠性或过大的封装大小。通过比较常规和传统方法与如在本申请的其余部分中参看图式阐述的本实用新型，此类方法的另外的限制和劣势将对所属领域的技术人员变得显而易见。
实用新型内容
本实用新型的各种方面提供一种半导体装置和一种制造半导体装置的方法。作为非限制性实例，本实用新型的各种方面提供一种半导体装置及一种其制造方法，所述半导体装置包括：衬底，其包含介电层；至少一个导电迹线和导电凸块衬垫，其形成于所述介电层的一个表面上；和保护层，其覆盖所述至少一个导电迹线和导电凸块衬垫，所述至少一个导电凸块衬垫具有通过所述保护层暴露的一端；和半导体裸片，其电连接到所述衬底的所述导电凸块衬垫。
附图说明
图1为根据本实用新型的各种实施例的半导体装置的横截面图。
图2A和2B为根据本实用新型的各种实施例的半导体装置中的衬底的一些区域的平面图。
图3A和3B为根据本实用新型的各种实施例的半导体装置中的衬底的横截面图。
图4A到4H为根据本实用新型的各种实施例的半导体装置的制造方法的横截面图。
具体实施方式
以下论述通过提供其实例来呈现本实用新型的各种方面。此类实例是非限制性的，并且由此本实用新型的各种方面的范围应不必受所提供的实例的任何特定特性限制。在以下论述中，短语“举例来说”、“例如”和“示范性”是非限制性的且通常与“借助于实例而非限制”、“例如且非限制”和类似者同义。
如本文中所使用，“和/或”意味着由“和/或”联结的列表中的项目中的任何一个或多个。作为实例，“x和/或y”意味着三元素集合{(x),(y),(x,y)}中的任何元素。换句话说，“x和/或y”意味着“x和y中的一个或两个”。作为另一实例，“x、y和/或z”意味着七元素集合{(x),(y),(z),(x,y),(x,z),(y,z),(x,y,z)}中的任何元素。换句话说，“x、y和/或z”意味着“x、y和z中的一或多个”。
本文中所使用的术语仅出于描述特定实例的目的，且并不希望限制本实用新型。如本文中所使用，除非上下文另外明确指示，否则单数形式也希望包含复数形式。将进一步理解，术语“包括”、“包含”、“具有”和类似者当在本说明书中使用时，指定所陈述特征、整体、步骤、操作、元件和/或组件的存在，但是不排除一或多个其它特征、整体、步骤、操作、元件、组件和/或其群组的存在或添加。
将理解，虽然术语“第一”、“第二”等可在本文中用以描述各种元件，但这些元件不应受这些术语限制。这些术语仅用以将一个元件与另一元件区分开来。因此，例如，在不脱离本实用新型的教示的情况下，下文论述的第一元件、第一组件或第一区段可被称为第二元件、第二组件或第二区段。类似地，例如「上部」、「上方」、「下部」、「下方」、「侧」、「侧向」、「水平」、「垂直」和类似者的各种空间术语可用于以相对方式将一个元件与另一元件区分开来。然而，应理解，组件可以不同方式定向，例如，在不脱离本实用新型的教示的情况下，半导体装置可以侧向转动使得其“顶”表面水平地朝向且其“侧”表面垂直地朝向。
还应理解，术语“耦合”、“连接”、“附着”和类似者包含直接和间接(例如，用插入元件)耦合、连接、附着等，除非另有明确指示。举例来说，如果元件A耦合到元件B，那么元件A可通过中间信号分配结构间接耦合到元件B，元件A可直接耦合到元件B(例如，直接黏附到、直接焊接到、通过直接金属到金属结合而附着)等。
在图式中，为了清晰起见，可放大结构、层、区域等的尺寸(例如，绝对和/或相对尺寸)。虽然此类尺寸大体指示实例实施方案，但其不受限制。举例来说，如果将结构A说明为大于区域B，那么此大体指示实例实施方案，但通常不需要结构A大于结构B，除非另有指示。另外，在图式中，相似参考数字可以在整个论述中指相似元件。
本实用新型的各种实施例涉及一种半导体装置及一种其制造方法。
一般而言，用于半导体的衬底用以电连接半导体裸片与外部装置(例如，主板、母板等)。不同于一般组件(例如，电容器、电阻器或类似者)，按非常高的集成等级安装的半导体组件可能不能够直接安装在外部装置中。因此，为了将半导体组件的电信号发射到外部装置，可利用用于在半导体中使用的衬底。
根据本实用新型的一方面，提供一种半导体装置，所述半导体装置包含：衬底，其包含介电层；至少一个导电迹线和导电凸块衬垫，其形成于所述介电层的一个表面上；和保护层，其覆盖所述至少一个导电迹线和导电凸块衬垫，所述至少一个导电凸块衬垫具有通过所述保护层暴露的一端；和半导体裸片，其电连接到所述衬底的所述导电凸块衬垫。
根据本实用新型的另一方面，提供一种半导体装置，所述半导体装置包括：衬底，其包含至少一个导电迹线和导电凸块衬垫和覆盖所述至少一个导电迹线和导电凸块衬垫的保护层，所述至少一个导电凸块衬垫具有通过所述保护层暴露的一端；半导体裸片，其电连接到所述衬底的所述导电凸块衬垫；和囊封物，其插入于所述衬底与所述半导体裸片之间。
根据本实用新型的另一方面，提供一种半导体装置的制造方法，所述制造方法包含：在介电层上涂布光刻胶树脂且接着执行光微影和显影工艺以在所述光刻胶树脂中形成至少一个迹线开口和凸块衬垫；对所述迹线开口和所述凸块衬垫开口执行电镀工艺以分别在所述迹线开口和所述凸块衬垫开口上形成导电迹线和导电凸块衬垫；用光刻胶树脂填充所述迹线开口且对所述凸块衬垫开口执行额外电镀工艺以形成具有比所述导电迹线大的厚度的导电凸块衬垫；和去除所述光刻胶树脂且用保护层覆盖所述导电迹线和所述导电凸块衬垫，所述导电凸块衬垫具有通过所述保护层暴露的一端。
如上所述，根据本实用新型的各种实施例，由于未暴露的导电迹线形成于经暴露和/或突出的导电凸块衬垫之间，所以即使导电凸块衬垫与导电迹线之间的空间减小了，也不会出现导电凸块衬垫与导电迹线之间的电短路。
此外，根据本实用新型的各种实施例，由于可调整导电凸块衬垫的高度(厚度)，因此可调整半导体裸片与衬底之间的间隙或空间。
此外，根据本实用新型的各种实施例，由于将导电迹线中的至少一个线插入于正常导电凸块衬垫的空间之间，所以与背景技术相比，可达成改善的设计灵活性。
现将关于用于主要使用电镀工艺形成导电迹线和导电凸块衬垫的工艺来描述本实用新型的各种方面，但本实用新型的各方面并不限于此。然而，本实用新型中揭示的导电迹线和/或导电凸块衬垫可通过多种工艺(例如，旋涂、印刷、喷涂、烧结、热氧化、物理气相沉积(PVD)、溅镀、化学气相沉积(CVD)、原子层沉积(ALD)或类似者)中的任一者形成。
此外，主要关于导电迹线和导电凸块衬垫由铜制成的情况来描述本实用新型的各种方面。然而，本实用新型中揭示的导电迹线和/或导电凸块衬垫可通过多种材料(例如，金、银、镍、钯、铝或类似者)中的任一者形成。
参看图1，说明根据本实用新型的各种实施例的半导体装置(100)的横截面图。
如图1中所说明，根据本实用新型的各种实施例的半导体装置100可包括衬底110、半导体裸片120和囊封构件130。此外，根据本实用新型的各种实施例的半导体装置100可进一步包含连接到衬底110的导电凸块140。
衬底110包括介电层(例如，绝缘层)111、至少一个导电迹线112、至少一个导电凸块衬垫113和至少一个保护层114。
介电层111具有实质上平坦第一表面111a和与第一表面111a相对的实质上平坦第二表面111b。介电层111可包括(例如)热固性树脂、热塑性树脂、硅、玻璃、陶瓷和其等效物中的一者，但本实用新型的各方面并不限于此。此外，介电层111可为刚性或柔性，但本实用新型的各方面并不限于此。
至少一个导电迹线112形成于介电层111的第一表面111a上。导电迹线112可变为用于电信号(例如，穿过半导体裸片120与外部装置之间的电信号、接地信号和/或电力信号等等)的路径。
导电迹线112可形成于介电层111内以及介电层111的第一表面111a上。此处，导电迹线112也可形成于介电层111的第二表面111b上。为了方便解释的原因，可将形成于介电层111内和介电层111的第二表面111b上的导电迹线定义为第二导电迹线116。此外，由于形成穿过介电层111的导电通孔117，因此形成于介电层111上、介电层111内和介电层111下的导电迹线112和116可相互电连接。在本实用新型中，描述将通常聚焦于形成于介电层111的第一表面111a上的导电迹线112。
同时，导电迹线112可包括(例如)铜、金、银、镍、钯、铝、其合金和其等效物中的一或多者，但本实用新型的各方面并不限于此。
至少一个导电凸块衬垫113形成于介电层111的第一表面111a上。也就是说，导电凸块衬垫113经形成以与导电迹线112间隔开一段预定距离。半导体裸片120电连接到导电凸块衬垫113。导电凸块衬垫113可包括(例如)铜、金、银、镍、钯、铝、其合金和其等效物中的一或多者，但本实用新型的各方面并不限于此。为了有助于制造工艺的目的，可使用相同材料(或相同材料的至少一个层)形成导电凸块衬垫113与导电迹线112，但这并非必要。
同时，导电凸块衬垫113可经形成以具有比导电迹线112大的宽度(或直径)。此外，导电凸块衬垫113也可经形成以具有比导电迹线112大的厚度(或高度)。此外，导电凸块衬垫113与导电迹线112之间(或在其中心线之间)的空间(或间距)可在大致1μm到大致15μm的范围中，优选地在大致5μm到大致10μm的范围中。也就是说，在本实用新型中，甚至在导电凸块衬垫113与导电迹线112之间的空间处于大致1μm到大致15μm的范围中或大致5μm到大致10μm的范围中时，导电凸块衬垫113与导电迹线112之间的电短路可不会出现。
保护层114(或介电层)形成于介电层111的第一表面111a上且覆盖导电迹线112和导电凸块衬垫113。举例来说，保护层114允许导电凸块衬垫113的顶表面被暴露或突出，同时全部覆盖导电迹线112。
此外，保护层114包括暴露导电凸块衬垫113的开口114a，且开口114a与导电凸块衬垫113可具有实质上相同宽度(或直径)。此外，保护层114可经形成以具有大致平坦顶表面。保护层114可由任何多种材料形成，例如，无机材料(例如，氮化物(Si3N4)、氧化物(SiO2)或氮氧化物(SiON))和/或有机材料(例如，聚酰亚胺(PI)、苯并环丁烷(BCB)、聚苯并恶唑(PBO)、双马来酰亚胺(BT)、酚醛树脂、环氧树脂或类似者)，但本实用新型的各方面并不限于此。
如上所述，在本实用新型中，导电迹线112全部由保护层114覆盖且导电凸块衬垫113的顶表面通过保护层114向外暴露和/或突出。因此，即使导电迹线112与导电凸块衬垫113之间的空间或距离相对小，导电迹线112与导电凸块衬垫113之间的电短路仍不大可能出现。
因此，在本实用新型中，衬底110或半导体装置100可具有进一步减小的大小。为了避免导电迹线112与导电凸块衬垫113之间的电短路，先前通常将导电迹线112与导电凸块衬垫113之间的空间设定到大致15μm或更大。然而，根据本实用新型，即使导电迹线112与导电凸块衬垫113之间的空间小于此间距，导电迹线112和导电凸块衬垫113(或至少其侧部分)全部由保护层114覆盖，仍可有效率地防止导电迹线112与导电凸块衬垫113之间的电短路。举例来说，保护层114将导电凸块衬垫113与导电迹线112电隔离。
此外，如果衬底110或半导体装置100的大小未由本实用新型的特征减小，那么在(例如)两个导电凸块衬垫113之间形成比背景技术中多的导电迹线112，由此改善迹线的集成度。还举例来说，可同时达成大小减小和增大的迹线集成度。
半导体裸片120通过导电凸块122电连接到衬底110。半导体裸片120可包括(例如)结合衬垫121和连接到结合衬垫121的导电凸块122。此处，结合衬垫121的概念可涵盖连接到再分布层的导电衬垫。
实际上，导电凸块122电连接到衬底110的导电凸块衬垫113。此处，导电凸块122可包含连接到结合衬垫121的导电柱123(或导电支柱)，和形成于导电柱123的底端处的焊料124。实际上，焊料124可连接到衬底110的导电凸块衬垫113。举例来说，焊料124可覆盖导电凸块衬垫113的顶表面和/或侧表面。此外，可使焊料124与保护层114直接接触。导电柱123可包括(例如)铜，但本实用新型的各方面并不限于此。此外，在一些情况下，导电柱123可直接电连接到导电凸块衬垫113。也就是说，导电柱123和导电凸块衬垫113可直接建立直接金属到金属结合(例如，无焊料、环氧树脂等)。
在本实用新型中，由于通过处理控制来充分地调整导电凸块122的厚度(或高度)，因此易于控制衬底110与半导体裸片120之间的间隙。也就是说，当衬底110与半导体裸片120之间的间隙应相对大时，导电凸块122经形成以具有相对大的厚度(或高度)。相反地，当衬底110与半导体裸片120之间的间隙应相对小时，导电凸块122经形成以具有相对小的厚度(或高度)。
任选地，可在半导体裸片120的结合衬垫121与导电柱123之间形成下凸块金属125(例如，金、银、镍、钯、铝或其合金等)。在必要时，另一下凸块金属126可进一步形成于导电柱123与焊料124之间。
半导体裸片120可包括电路，例如，中央处理单元(CPU)、数字信号处理器(DSP)、网络处理器、电力管理单元、音频处理器、RF电路、无线基带芯片上系统(SoC)处理器、传感器和专用集成电路。
囊封构件130覆盖安置于衬底110上的半导体裸片120。当囊封构件130(例如，其填充物)具有比衬底110与半导体裸片120之间的间隙足够小的大小时，其可填充衬底110与半导体裸片120之间的间隙。在一些情况下，囊封构件130可全部覆盖半导体裸片120的顶表面和侧表面。
此外，囊封构件130的顶表面可与半导体裸片120的顶表面共平面。也就是说，半导体裸片120的顶表面可通过囊封构件130的顶表面向外暴露。此外，囊封构件130的侧表面可与衬底110的侧表面共平面。还举例来说，囊封构件130的侧表面可不与衬底110的侧表面共平面。在一些情况下，囊封构件130可覆盖衬底110的侧表面。
此外，衬底110与半导体裸片120之间的间隙可在囊封之前用底填充料填充，接着用囊封构件130囊封半导体裸片120。囊封构件130可包含(例如)环氧模制化合物、环氧树脂模制化合物和其等效物，但本实用新型的各方面并不限于此。
导电凸块140可电连接到衬底110的底表面。举例来说，导电凸块140可连接到第二导电迹线116，且导电凸块140可又安装到外部装置。导电凸块140可包含(例如)共晶焊料(Sn37Pb)、高铅焊料(Sn95Pb)和无铅焊料(SnAg、SnAu、SnCu、SnZn、SnZnBi、SnAgCu、SnAgBi等)和其等效物中的一者，但本实用新型的各方面并不限于此。
导电凸块140可呈平地或球的形式，如图1中所说明。
如上所述，在根据本实用新型的各种实施例的半导体装置100中，由于未暴露的导电迹线112形成于暴露的和/或突出的导电凸块衬垫113之间，所以即使导电凸块衬垫113与导电迹线112之间的空间减小了，导电凸块衬垫113与导电迹线112之间的电短路可仍不出现。
此外，在根据本实用新型的各种实施例的半导体装置100中，由于易于调整导电凸块衬垫113的高度(厚度)，因此可易于调整半导体裸片120与衬底110之间的间隙或空间。此外，在根据本实用新型的各种实施例的半导体装置100中，由于将导电迹线112中的至少一个线插入于正常导电凸块衬垫113的空间之间，所以可达成改善的设计灵活性。
参看图2A和2B，说明在根据本实用新型的各种实施例的半导体装置(100)中的衬底(110)的一些区域的平面图。
如图2A中所说明，导电凸块衬垫113可形状为实质上圆形平面(例如，圆柱形)，但本实用新型的各方面并不限于此。也就是说，导电凸块衬垫113可采用各种平面(或平坦横截面)形状，包含(例如)椭圆形形状、正方形形状、矩形形状、五边形形状、梯形形状等等。此处，在保护层114中形成的开口114a的宽度(直径或大小)可等于导电凸块衬垫113的宽度(直径或大小)。
如图2B中所说明，导电凸块衬垫213可形状为实质上圆形平面，且多个三边形(或三角形)突出213a可进一步沿着导电凸块衬垫213的周边形成，但本实用新型的各方面并不限于此。也就是说，突出213a可采用各种平面(或平坦横截面)形状，包含(例如)矩形形状、凸形状、凹形状等等。图2B中说明的导电凸块衬垫213的特征也可应用于图3A和3B中说明的导电凸块衬垫或本文中揭示的任何导电凸块衬垫。
具有各种平面形状的导电凸块衬垫213的设计可进一步改善半导体裸片120与导电凸块衬垫213的耦合力。也就是说，由于形成于半导体裸片120中的导电凸块122(即，焊料124)不仅包围导电凸块衬垫213的顶表面，而且包围导电凸块衬垫213的侧表面且导电凸块衬垫213经形成以具有不平的侧表面，因此导电凸块122与导电凸块衬垫213之间的接触面积可增大。
参看图3A和3B，说明在根据本实用新型的各种实施例的半导体装置(100)中的衬底(310、410)的横截面图。
如图3A中所说明，导电凸块衬垫313可具有实质上凹顶部部分。也就是说，导电凸块衬垫313可形状为凹透镜，其在其顶表面的中心具有最大深度和远离中心逐渐减小的深度。通过此配置，在本实用新型中，半导体裸片120的导电柱123可直接电连接到导电凸块衬垫313，而不借助于焊料124，此可不表明本实用新型阻止使用焊料124。半导体裸片120与衬底110之间的金属到金属结合可通过(例如)热压缩实现。如果导电凸块衬垫313具有实质上凹顶部部分，那么导电凸块122或导电柱123优选地具有实质上凸底部部分。
具有凹顶表面的导电凸块衬垫313可通过(例如)在电镀期间变化电镀溶液的浓度来形成。举例来说，导电凸块衬垫313的凹顶表面可通过从导电凸块衬垫313的高度变为导电凸块衬垫313的总高度的大致80％到大致90％之时逐渐减小电镀溶液的浓度来达到。
相反地，如图3B中所说明，导电凸块衬垫413可具有实质上凸顶部部分。也就是说，导电凸块衬垫413可形状为凸透镜，其在其顶表面的中心具有最大高度和远离中心逐渐减小的高度。通过此配置，在本实用新型中，半导体裸片120的导电凸块122与衬底110的导电凸块衬垫413之间的接触面积可增大。
如果导电凸块衬垫413具有实质上凸顶部部分，那么导电凸块122或导电柱123优选地具有实质上凹底部部分。
具有凹底表面的导电凸块衬垫413可通过(例如)在电镀期间变化电镀溶液的浓度来形成。举例来说，导电凸块衬垫413的凸底表面可通过从导电凸块衬垫413的高度变为导电凸块衬垫413的总高度的大致80％到大致90％之时逐渐减小电镀溶液的浓度来达到。
参看图4A到4H，说明根据本实用新型的各种实施例的半导体装置(100)的制造方法的横截面图。假定完成衬底110的基本配置，且以下描述将聚焦于根据本实用新型形成导电迹线112和导电凸块衬垫113的工艺。
如图4A中所说明，由钨、钛钨和/或铜(或多种材料中的任一种)制成的种子层111c形成于第一表面111上，且将光刻胶树脂150(或其他遮蔽材料)涂布于种子层111c上，接着在光刻胶树脂150中形成迹线开口150a和凸块衬垫开口150b，例如，通过光刻和显影工艺。此处，迹线开口150a可形状为(例如)线，但本实用新型的各方面并不限于此。此外，凸块衬垫开口150b可形状为(例如)圆、矩形或线，但本实用新型的各方面并不限于此。如上所述，种子层111c可通过迹线开口150a和凸块衬垫开口150b向外暴露。凸块衬垫开口150b可(例如)对应于本文中论述的凸块衬垫形状中的任一者。
此处，光刻胶树脂150可呈(例如)液体或干燥薄膜的形式，但本实用新型的各方面并不限于此。
如图4B中所说明，可通过第一电镀工艺使导电迹线112和导电凸块衬垫113'形成于迹线开口150a和凸块衬垫开口150b上。此处，导电迹线112与导电凸块衬垫113'可在电镀时具有相同厚度，和电镀溶液的相同浓度。由于凸块衬垫开口150b具有比迹线开口150a大的宽度，因此导电凸块衬垫113'的宽度可大于导电迹线112的宽度。
此外，导电迹线112和导电凸块衬垫113'的厚度(或高度)可小于迹线开口150a和凸块衬垫开口150b的厚度(或高度)。
如图4C中所说明，迹线开口150a可受到光刻胶树脂150阻挡。因此，导电迹线112与外部完全隔离。然而，导电凸块衬垫113'不与外部隔离。也就是说，导电凸块衬垫113'仍通过凸块衬垫开口150b向外暴露。
如图4D中所说明，通过第二电镀工艺形成导电凸块衬垫113。也就是说，作为第二电镀工艺的结果，只增加导电凸块衬垫113的厚度。换句话说，由于导电迹线112接收电流且不能够接近电镀溶液，而导电凸块衬垫113'接收电流且能够接近电镀溶液，因此最终只增加导电凸块衬垫113的厚度(或高度)。也就是说，导电迹线112具有比导电凸块衬垫113小的最终厚度。由于在实例实施方案中，导电凸块衬垫113按两个阶段形成(例如，电镀等)于同一开口150b中，因此导电凸块衬垫113的侧表面可为连续的(例如，在第一形成部分与第二形成部分之间无显著的不连续)。
此处，如本文所论述，可通过变化在第二电镀工艺的末期阶段的电镀溶液的浓度来凹或凸地形成导电凸块衬垫113的顶表面。
如图4E中所说明，光刻胶树脂150被完全去除，由此将具有不同厚度和/或宽度的导电迹线112和导电凸块衬垫113向外暴露。光刻胶树脂150的此去除将种子层111c的各种部分(例如，种子层111c的不在导电迹线112或导电凸块衬垫113下的部分)向外暴露。接着执行软蚀刻，由此去除定位于导电迹线112和导电凸块衬垫113的外部侧处的种子层111c。因此，介电层111的定位于导电迹线112和导电凸块衬垫113的外部侧处的第一表面111a直接向外暴露。
如图4F中所说明，由于保护层114形成于介电层111的第一表面111a上，因此导电迹线112和导电凸块衬垫113由保护层114覆盖，同时使导电凸块衬垫113的顶表面向外暴露和/或突出。也就是说，虽然保护层114具有比导电迹线112大的厚度，但其经控制以具有比导电凸块衬垫113小的厚度，由此使导电凸块衬垫113的顶表面和侧表面(或其上部部分)向外暴露和/或突出。因此，导电迹线112由保护层114完全覆盖，且使导电凸块衬垫113的顶表面和侧表面(或其上部部分)从保护层114向外暴露和/或突出。此处，导电凸块衬垫113的顶表面完全向外暴露，而导电凸块衬垫113的侧表面的一些部分(或其上部部分)向外暴露。
可通过多种工艺中的任一者(例如，旋涂、印刷、喷涂、烧结、热氧化、物理气相沉积(PVD)、溅镀、化学气相沉积(CVD)、原子层沉积(ALD)或类似者)来形成保护层114，但本实用新型的各方面并不限于此。
如图4G中所说明，半导体裸片120电连接到提供于衬底110中的导电凸块衬垫113。包含(例如)导电柱123和焊料124的导电凸块122可形成于半导体裸片120上。导电凸块122可电连接到导电凸块衬垫113。导电凸块122可通过(例如)大规模回流焊、热压缩或激光辅助结合而电连接到导电凸块衬垫113，但本实用新型的范围不限于此。在一些情况下，可将非导电膏(NCP)涂布于导电凸块衬垫113上和导电凸块衬垫113周围，且半导体裸片120的导电凸块122可电连接到衬底110的导电凸块衬垫113，同时穿过NCP。如上所述，半导体裸片120的导电柱123可直接金属到金属结合到衬底110的导电凸块衬垫113，而不借助于焊料。
如图4H中所说明，半导体裸片120由(例如)囊封物囊封，由此形成囊封构件130。此处，囊封构件130还可填充衬底110与半导体裸片120之间的间隙。替代地，在将底填充料填充到半导体裸片120与衬底110之间的间隙内后，囊封构件130可形成于半导体裸片120和衬底110的外部侧。可通过(例如)压缩模制(即，使用液体、粉末和/或薄膜)或真空模制来形成囊封构件130。此外，囊封构件130可通过(例如)传递模塑来形成，但本实用新型的范围不限于此。
此处，囊封构件130可原先经形成以覆盖半导体裸片120的顶表面，且可研磨囊封构件130和半导体裸片120的顶表面，由此使囊封构件130的顶表面与半导体裸片120的顶表面共平面。在一些情况下，可不执行研磨，使得囊封构件130可覆盖半导体裸片120的顶表面。
此外，在一些情况下，在通过薄膜辅助模制执行模制后，半导体裸片120的顶表面可与囊封构件130的顶表面共平面。也就是说，柔性薄膜定位于覆盖半导体裸片120的模套的底表面上，且对柔性薄膜执行模制，所述柔性薄膜处于使柔性薄膜与半导体裸片120的顶表面紧密接触的状态中。在模制后，半导体裸片120的顶表面可与囊封构件130的顶表面共平面。
其后，导电凸块140可形成于提供于衬底110的底表面上的第二导电迹线116中。也就是说，导电凸块140可形成于第二导电迹线116的由焊球或焊膏向下暴露的区域中。此处，第二导电迹线116的区域的外部(在此处将形成导电凸块140)也可由保护层118覆盖。
同时，由于可按条带或矩阵的形式执行制造工艺，因此可通过使用激光束或钢锯条的锯切工艺或单切工艺来实施离散半导体装置100。最终，由于将囊封构件130和衬底110在一起切割，因此囊封构件130的侧表面可与衬底110的侧表面共平面。
如上所述，在本实用新型中，虽然在第一电镀工艺期间同时形成导电迹线112与导电凸块衬垫113，但只在第二电镀工艺期间对导电凸块衬垫113执行电镀，由此允许导电凸块衬垫113具有导电迹线112的较大厚度(或高度)。因此，在本实用新型中，易于控制(或维持)衬底110与半导体裸片120之间的间隙。此外，在本实用新型的制造工艺中，保护层114经控制以具有比导电迹线112大的厚度和比导电凸块衬垫113小在厚度，由此通过保护层114使导电凸块122向外暴露和/或突出，同时由保护层114覆盖导电迹线112。因此，可防止导电迹线112与导电凸块122之间的电短路出现在后续工艺中。举例来说，导电凸块衬垫113与导电迹线112之间的电短路不会因半导体裸片120的导电凸块122而出现。
本文中的论述包含展示电子装置组合件的各种部分及其制造方法的众多说明性图。为了说明清晰性，这些图并未展示每一实例组合件的所有方面。本文中提供的任何实例组合件和/或方法可与本文中提供的任何或全部其它组合件和/或方法共享任何或全部特征。
总之，本实用新型的各种方面提供一种半导体装置和一种制造半导体装置的方法。作为非限制性实例，本实用新型的各种方面提供一种半导体装置及一种其制造方法，所述半导体装置包括：衬底，其包含介电层；至少一个导电迹线和导电凸块衬垫，其形成于所述介电层的一个表面上；和保护层，其覆盖所述至少一个导电迹线和导电凸块衬垫，所述至少一个导电凸块衬垫具有通过所述保护层暴露的一端；和半导体裸片，其电连接到所述衬底的所述导电凸块衬垫。虽然已经参考某些方面和实例描述了以上内容，但是所属领域的技术人员应理解，在不脱离本实用新型的范围的情况下，可进行各种改变并可用等效物取代。此外，在不脱离本实用新型的范围的情况下，可进行许多修改以使特定情况或材料适应本实用新型的教示。因此，希望本实用新型不限于所揭示的特定实例，而是本实用新型将包含属于所附权利要求书的范围的所有实例。

Claims (11)

1.一种半导体装置，其特征在于，包括：
衬底，其具有顶部衬底侧和底部衬底侧；
导电迹线，其具有顶部迹线侧、在所述顶部衬底侧上的底部迹线侧和在所述顶部迹线侧与所述底部迹线侧之间的侧向迹线侧；
导电凸块衬垫，其具有顶部衬垫侧、在所述顶部衬底侧上的底部衬垫侧和在所述顶部衬垫侧与所述底部衬垫侧之间的侧向衬垫侧；以及
介电层，其至少覆盖所述顶部迹线侧、所述侧向迹线侧和所述侧向衬垫侧的下部部分；
其中所述顶部衬垫侧从所述介电层暴露，且所述导电凸块衬垫在垂直上比所述导电迹线厚。
2.根据权利要求1所述的半导体装置，其特征在于，所述顶部衬垫侧和所述侧向衬垫侧的上部部分从所述介电层突出。
3.根据权利要求1所述的半导体装置，其特征在于，所述导电迹线与所述导电凸块衬垫之间的侧向距离小于10μm。
4.根据权利要求1所述的半导体装置，其特征在于，所述介电层包括开口，所述导电凸块衬垫通过所述开口被暴露，且所述开口的宽度等于所述导电凸块衬垫的宽度。
5.根据权利要求1所述的半导体装置，其特征在于，所述侧向衬垫侧包括从其延伸的多个突出。
6.根据权利要求1所述的半导体装置，其特征在于，其包括附着到所述导电凸块衬垫的半导体裸片，且其中所述半导体裸片包括用覆盖所述侧向衬垫侧的至少一部分的焊料连接到所述导电凸块衬垫的导电凸块。
7.根据权利要求6所述的半导体装置，其特征在于，所述焊料接触所述介电层。
8.根据权利要求1所述的半导体装置，其特征在于，其包括附着到所述导电凸块衬垫的半导体裸片，且其中：
所述顶部衬垫侧为凹的或凸的；且
所述半导体裸片包括通过直接金属到金属结合连接到所述顶部衬垫侧的导电凸块。
9.根据权利要求1所述的半导体装置，其特征在于，其包括第一电镀传导层，所述第一电镀传导层包括所述导电迹线和所述导电凸块衬垫的下部部分。
10.根据权利要求9所述的半导体装置，其特征在于，其包括第二电镀传导层，所述第二电镀传导层包括所述导电凸块衬垫的上部部分。
11.根据权利要求10所述的半导体装置，其特征在于，在所述导电凸块衬垫的所述下部部分与所述上部部分之间的所述侧向衬垫侧上不存在不连续。
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