CN109427701A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN109427701A
CN109427701A CN201711230904.3A CN201711230904A CN109427701A CN 109427701 A CN109427701 A CN 109427701A CN 201711230904 A CN201711230904 A CN 201711230904A CN 109427701 A CN109427701 A CN 109427701A
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Prior art keywords
conductor
substrate
width
semiconductor device
exposure
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CN109427701B (zh
Inventor
黄冠育
蓝子凯
殷寿志
许书嘉
李百渊
黄松辉
李祥帆
韩英信
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明实施例涉及半导体装置及其制造方法。该半导体装置包含衬底、封装、第一导体及第二导体。所述衬底包含第一表面及与所述第一表面相对的第二表面。所述封装放置于所述衬底上方。所述第一导体放置于所述衬底上方。所述第二导体放置于所述衬底上方，其中所述第一导体及所述第二导体基本上处于同一层级，且所述第二导体的宽度大于所述第一导体的宽度。

Description

半导体装置及其制造方法
技术领域
本揭露关于半导体装置和其制造方法。
背景技术
在集成电路的封装中，半导体裸片可通过接合来堆叠，且可接合到例如中介层及封装衬底的其它封装组件。所得封装被称作三维集成电路(3DIC)。然而，冷结问题及桥接问题是3DIC中的挑战。
发明内容
本发明的一个实施例是关于一种半导体装置，所述半导体装置包括：衬底，其包含第一表面及与所述第一表面相对的第二表面；封装，其在所述衬底上方；多个第一导体，其在所述衬底上方；及多个第二导体，其在所述衬底上方，其中所述多个第一导体及所述多个所述第二导体基本上处于同一层级，且所述第二导体的宽度大于所述第一导体的宽度。
本发明的另一实施例是关于一种半导体装置，所述半导体装置包括：衬底，其包含第一表面及与所述第一表面相对的第二表面；封装，其在所述衬底上方；多个第一导体，其在所述衬底上方；及多个第二导体，其在所述衬底上方，其中所述多个第一导体及所述多个所述第二导体基本上处于同一层级，且所述第二导体的体积大于所述第一导体的体积。
本发明的另一实施例是关于一种用于制造半导体装置的方法，其包括：接收衬底；在所述衬底上方形成第一导体及第二导体，其中所述第二导体的高度大于所述第一导体的高度；及通过所述第一导体及所述第二导体将所述衬底接合到电子组件。
附图说明
本揭露的实施例的方面依据在借助附图阅读时进行的以下详细说明得到最佳地理解。应注意，根据工业中的标准实践，各种结构未按比例绘制。实际上，为论述清晰起见，可任意地增加或减小各种结构的尺寸。
图1是图解说明根据本揭露的一或多个实施例的各个方面的制造半导体装置的方法的流程图。
图2A、图2B、图2C及图2D是在根据本揭露的一或多个实施例的制造半导体装置的各种操作中的一个时的示意图。
图3A、图3B及图3C是在根据本揭露的一或多个实施例的制造半导体装置的各种操作中的一个时的示意图。
图4A、图4B、图4C、图4D及图4E是在根据本揭露的一或多个实施例的制造半导体装置的各种操作中的一个时的示意图。
图5A及图5B是根据本揭露的一些实施例的半导体装置的示意图。
图6A及图6B是根据本揭露的一些实施例的半导体装置的示意图。
图7A及图7B是根据本揭露的一些实施例的半导体装置的示意图。
图8是根据本揭露的一些实施例的半导体装置的示意图。
图9A、图9B、图9C及图9D是在根据本揭露的一或多个实施例的制造半导体装置的各种操作中的一个时的示意图。
图10是根据本揭露的一些实施例的半导体装置的示意图。
具体实施方式
以下揭示内容提供用于实施所提供标的物的不同特征的许多不同实施例或实例。下文描述元件及布置的具体实例以简化本揭露。当然，这些具体实例仅为实例且不打算为限制性的。举例来说，在以下说明中第一特征形成于第二特征上方或上可包含其中第一特征及第二特征直接接触地形成的实施例，且也可包含其中额外特征可形成于第一特征与第二特征之间使得第一特征及第二特征可不直接接触的实施例。另外，本揭露可在各种实例中重复元件符号及/或字母。此重复是出于简单及清晰目的且本身不指示所论述的各种实施例及/或配置之间的关系。
进一步地，可为便于说明而在本文中使用空间相对术语(例如，“下方”、“下面”、“下部”、“上面”、“上部”、“上”及类似者)来描述一个元件或特征与另一(些)元件或特征的关系，如各图中所图解说明。所述空间相关术语打算囊括除各图中所描绘的定向之外的在使用或操作中的装置的不同定向。设备可以其它方式定向(旋转90度或处于其它定向)且因此可同样地解释本文中所使用的空间相对叙词。
如本文中所使用，例如“第一”、“第二”及“第三”的术语描述各种元件、组件、区域、层及/或区段，这些元件、组件、区域、层及/或区段不应受这些术语限制。这些术语可仅用于将一个元件、组件、区域、层或区段与另一元件、组件、区域、层或区段区分开。例如“第一”、“第二”及“第三”的术语在用于本文中时不暗示顺序或次序，除非上下文明确指示。
如本文中所使用，术语“大致”、“基本上(substantially)”、“基本上(substantial)”及“大约”用于描述且解释小变化。当结合事件或情况使用时，所述术语可指代其中事件或情况精确地发生的实例以及其中事件或情况近似地发生的实例。举例来说，当结合数值使用时，术语可指代所述数值的小于或等于±10％(例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％或小于或等于±0.05％)的变化范围。举例来说，如果两个数值之间的差小于或等于所述值的平均数的±10％，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％或小于或等于±0.05％，那么所述值可被视为“基本上”相同或相等。举例来说，“基本上”平行可指代相对于0°的角度变化范围，所述角度变化范围小于或等于±10°，例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°或小于或等于±0.05°。举例来说，“基本上”垂直可指代相对于90°的角度变化范围，所述角度变化范围小于或等于±10°，例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°或小于或等于±0.05°。
也可包含其它特征及过程。举例来说，可包含测试结构以辅助3D封装或3DIC装置的验证测试。所述测试结构可包含(举例来说)形成于重布层中或衬底上的测试垫，此允许测试3D封装或3DIC、使用探针及/或探针卡及类似者。可对中间结构以及最终结构执行验证测试。另外，本文中所揭示的结构及方法可结合并入有已知良好裸片的中间验证的测试方法使用以增加合格率且降低成本。
在本揭露的一些实施例中，半导体装置包含放置于同一层级处的两个或多于两个类型的导体，所述导体具有不同体积及/或宽度、形成于衬底的不同区域处以分别缓解冷结问题及桥接问题。
图1是图解说明根据本揭露的一或多个实施例的各个方面的制造半导体装置的方法的流程图。方法100以操作110开始，其中接收衬底。方法以操作120继续，其中在衬底上方形成第一导体及第二导体。第二导体的高度大于第一导体的高度。方法以操作130继续，其中衬底通过第一导体及第二导体接合到电子组件。
方法100仅仅为实例，且不打算限制本揭露超出权利要求书中明确陈述的内容。可在方法100之前、期间及之后提供额外操作，且可针对方法的额外实施例替换、消除或移动所描述的一些操作。
图2A、图2B、图2C及图2D是在根据本揭露的一或多个实施例的制造半导体装置的各种操作中的一个时的示意图。如图2A中所描绘，接收衬底10。在一些实施例中，衬底10可包含晶片、半导体衬底、中介层、封装衬底或类似者。衬底10包含第一表面10A及与第一表面10A相对的第二表面10B。在一些实施例中，第一接合垫121及第二接合垫122形成于衬底10上且从第一表面10A暴露。第一接合垫121及第二接合垫122可经配置以接收且电连接到将形成的导体。在一些替代实施例中，第一接合垫121及第二接合垫122可从第二表面10B暴露。在一些实施例中，衬底10可进一步包含电连接到第一接合垫121及第二接合垫122的一或多个电路层14，例如重布层(RDL)、导电通孔或类似者。
如图2B中所描绘，钝化层16形成于衬底10上方。在一些实施例中，钝化层16形成于衬底10的第一表面10A上方。在一些实施例中，钝化层16可包含焊料掩模、绝缘层或类似者。钝化层16包含分别暴露第一接合垫121及第二接合垫122的第一凹部161及第二凹部162。在一些实施例中，第一凹部161的宽度WA1大于第二凹部162的宽度WA2。在一些实施例中，第二凹部162暴露第二接合垫122的一部分，且第二接合垫122的另一部分被钝化层16覆盖。另一方面，第一凹部161可完全地暴露第一接合垫121，且第一接合垫121可与钝化层16分开一间隙。
如图2C中所描绘，导电材料形成于第一接合垫121及第二接合垫122上方以通过第一凹部161形成第一导体18且通过第二凹部162形成第二导体20。在一些实施例中，可在形成导电材料之后执行回流操作。在一些实施例中，第一导体18及第二导体20可包含导电凸块、导电球或类似者。在一些实施例中，第一导体18及第二导体20的材料可包含但不限于银(Ag)、铜(Cu)、锡(Sn)、其组合或其它适合导电材料。在一些实施例中，第一导体18可为非焊料掩模界定的(NSMD)导体，而第二导体20可为焊料掩模界定的(SMD)导体。通过实例的方式，覆盖第二接合垫122的一部分的钝化层16可帮助界定第二导体20的宽度W2，而第一导体18的宽度W1可由第一接合垫121的宽度界定。在一些实施例中，第一导体18与相应第一凹部161的边缘161E分开，且第二导体20与相应第二凹部162的边缘162E接触。在一些实施例中，第一导体18的体积及第二导体20的体积基本上相同，第一导体18的高度H1由第一接合垫121的宽度界定，且第二导体20的高度H2由第二凹部162的宽度WA2界定。由于第二凹部162的宽度WA2小于第一接合垫121的宽度，因此第二导体20的宽度W2小于第一导体18的宽度W1，且第二导体20的高度H2大于第一导体18的高度H1。在一些实施例中，第二导体20的高度H2可比第一导体18的高度H1大大约5％到大约20％，例如大约10％，但不限于此。在一些实施例中，第一导体18及第二导体20基本上放置于同一层级处。
如图2D中所描绘，衬底10可通过第一导体18及第二导体20接合到电子组件30以形成半导体装置1。在一些实施例中，电子组件30可包含晶片、半导体衬底、中介层、封装衬底、印刷电路板(PCB)或类似者。在一些实施例中，电子组件30可进一步包含经配置以接收第一导体18及第二导体20的接合垫(未展示)。在一些实施例中，可执行回流操作。在接合衬底10及电子组件30之后，第二导体20的高度H2'及第一导体18的高度H1'可基本上相同，且第二导体20的宽度W2'可大于第一导体18的宽度W1'。在一些实施例中，具有较大高度的第二导体20可帮助避免由于扭曲或其它原因而出现冷结。在一些实施例中，具有较小高度的第一导体18可帮助避免由于扭曲或其它原因而出现桥接(即，邻近导体之间的短路)。在一些实施例中，第二导体20可经配置以形成于其中趋向于发生冷结的冷结热区中，而第一导体18可经配置以形成于其中趋向于发生桥接的桥接热区中。在一些实施例中，半导体装置1可为包含彼此堆叠的两个或多于两个电子组件或衬底的三维封装结构，且第一导体18及第二导体20可形成于邻近电子组件或衬底中的任何两个中。
本揭露的半导体装置及其制造方法不限于上文所提及的实施例，且可具有其它不同实施例。为简化说明且为了便于在本揭露的实施例中的每一个之间进行比较，用等同编号标记以下实施例中的每一个中的等同组件。为了使将实施例之间的差异进行比较更容易，以下说明将详述不同实施例之间的相异点且将不冗余地描述等同特征。
图3A、图3B及图3C是在根据本揭露的一或多个实施例的制造半导体装置的各种操作中的一个时的示意图。如图3A中所描绘，接收衬底10。在一些实施例中，衬底10可进一步包含从第一表面10A暴露且经配置以接收将形成的导体的第一接合垫121及第二接合垫122。在一些替代实施例中，第一接合垫121及第二接合垫122可从第二表面10B暴露。在一些实施例中，衬底10可进一步包含电连接到第一接合垫121及第二接合垫122的一或多个电路层14，例如重布层(RDL)、导电通孔或类似者。在一些实施例中，钝化层16形成于衬底10上方。在一些实施例中，钝化层16形成于衬底10的第一表面10A上方。在一些实施例中，钝化层16可包含焊料掩模或类似者。钝化层16包含分别暴露第一接合垫121及第二接合垫122的第一凹部161及第二凹部162。在一些实施例中，第一凹部161的宽度WA1大于第二凹部162的宽度WA2。在一些实施例中，钝化层16覆盖第一接合垫121的一部分及第二接合垫122的一部分。
如图3B中所描绘，导电材料形成于第一接合垫121及第二接合垫122上方以通过第一凹部161形成第一导体18且通过第二凹部162形成第二导体20。在一些实施例中，可在形成导电材料之后执行回流操作。在一些实施例中，覆盖第一接合垫121的一部分的钝化层16可帮助界定第一导体18的宽度W1，且覆盖第二接合垫122的一部分的钝化层16可帮助界定第二导体20的宽度W2。在一些实施例中，第一导体18的体积及第二导体20的体积基本上相同，第一导体18的高度H1由第一凹部161的宽度WA1界定，且第二导体20的高度H2由第二凹部162的宽度WA2界定。由于第二凹部162的宽度WA2小于第一凹部161的宽度WA1，因此第二导体20的宽度W2小于第一导体18的宽度W1，且第二导体20的高度H2大于第一导体18的高度H1。在一些实施例中，第二导体20的高度H2可比第一导体18的高度H1大大约5％到大约20％，例如大约10％，但不限于此。
如图3C中所描绘，衬底10可通过第一导体18及第二导体20接合到且电连接到电子组件30以形成半导体装置2。在一些实施例中，可执行回流操作。在接合衬底10及电子组件30之后，第二导体20的高度H2'及第一导体18的高度H1'可基本上相同，且第二导体20的宽度W2'可大于第一导体18的宽度W1'。
图4A、图4B、图4C、图4D及图4E是在根据本揭露的一或多个实施例的制造半导体装置的各种操作中的一个时的示意图。如图4A中所描绘，接收衬底10。在一些实施例中，衬底10可进一步包含从第一表面10A暴露的第一接合垫121及第二接合垫122，以及电连接到第一接合垫121及第二接合垫122的一或多个电路层14。第一导电材料形成于第一接合垫121及第二接合垫122上方以形成具有相同高度的导体17。在一些实施例中，可对第一导电材料执行回流操作以形成导体17。
如图4B中所描绘，经图案化掩模层22形成于衬底10上方。经图案化掩模层22可包含暴露导体17中的一个的凹部221。如图4C中所描绘，第二导电材料24形成于凹部221中。在一些实施例中，第二导电材料24及第一导电材料可包含但不限于不同材料。在一些实施例中，第二导电材料24的熔点可低于第一导电材料的熔点。通过实例的方式，第一导电材料可包含银(Ag)、铜(Cu)、锡(Sn)、其组合或类似者，且第二导电材料24可包含铅(Pb)、铋(Bi)、其组合或类似者。
如图4D中所描绘，可对第一导电材料及第二导电材料24执行回流操作以形成具有高度H1的第一导体18及具有高度H2的第二导体20。第一导体18由第一导电材料形成，而第二导体20由第一导电材料及第二导电材料24形成。因此，第二导体20的高度H2大于第一导体18的高度H1。在一些实施例中，第二导体20的熔点低于第一导体18的熔点。在一些实施例中，第二导体20的高度H2可比第一导体18的高度H1大大约5％到大约20％，例如大约10％，但不限于此。在一些实施例中，第一导体18的宽度W1及第二导体20的宽度W2基本上相同。
如图4E中所描绘，衬底10可通过第一导体18及第二导体20接合到且电连接到电子组件30以形成半导体装置3。在一些实施例中，可执行回流操作。在接合衬底10与电子组件30之后，第二导体20的高度H2'及第一导体18的高度H1'可基本上相同，且第二导体20的宽度W2'可大于第一导体18的宽度W1'。
图5A及图5B是根据本揭露的一些实施例的半导体装置的示意图，其中图5A是根据本揭露的一些实施例的半导体装置的俯视图，且图5B是沿着图5A的半导体装置的线A-A的横截面视图。如图5A及图5B中所描绘，半导体装置4包含衬底10、封装50、第一导体18及第二导体20。封装50放置于衬底10上方。第一导体18及第二导体20放置于衬底10上方且电连接到封装50。在一些实施例中，封装50、第一导体18及第二导体20放置于衬底10的第一表面10A上方，且第一导体18及第二导体20放置于封装50与衬底10的第一表面10A之间。在一些实施例中，第二导体20的宽度W2'大于第一导体18的宽度W1'。第二导体20的体积可基本上等于或大于第一导体18的体积。在一些实施例中，第一导体18及第二导体20可通过(例如)前述实施例中所描述的方法来形成，但不限于此。
在一些实施例中，封装50可包含但不限于晶片上芯片(CoW)结构。在一些实施例中，封装50可包含中介层52、至少一个第一半导体裸片60、至少一个第二半导体裸片70、第一模制层62及第二模制层72。第一半导体裸片60放置于中介层52上方且电连接到中介层52。在一些实施例中，第一半导体裸片60通过导电结构64(例如导电凸块、导电球、导电膏或类似者)电连接到中介层52。第二半导体裸片70放置于中介层52上方且电连接到中介层52，且第二半导体裸片70邻近于至少一个第一半导体裸片60放置。在一些实施例中，第二半导体裸片70通过导电结构74(例如导电凸块、导电球、导电膏或类似者)电连接到中介层52。在一些实施例中，第一半导体裸片60及第二半导体裸片70包含具有不同特性的不同类型的裸片。通过实例的方式，第一半导体裸片60可包含(若干)存储器裸片，且第二半导体裸片70可包含(若干)芯片上系统(SOC)裸片。在一些实施例中，第一半导体裸片60在放置于中介层52上方之前用环绕第一半导体裸片60的侧壁60E的第一模制层62封装，而第二半导体裸片70在放置于中介层52上方之后经封装。第二模制层72放置于中介层52上方且环绕第二半导体裸片70的侧壁70E及第一模制层62的侧壁62E。在一些实施例中，第一模制层62及第二模制层72的特性是不同的。通过实例的方式，第一模制层62及第二模制层72可包含具有不同热膨胀系数(CTE)的不同材料。
在一些实施例中，第二导体20形成于其中趋向于发生冷结的冷结热区52R中。举例来说，第二导体20基本上对准到至少一个第一半导体裸片60与至少一个第二半导体裸片70之间的边界52C，且基本上对准到至少一个第二半导体裸片70与中介层52的边缘52E之间的边界52D。在一些实施例中，第一导体18形成于其中趋向于发生桥接的桥接热区52T中。举例来说，第一导体18可对准到中介层52的角落。
图6A及图6B是根据本揭露的一些实施例的半导体装置的示意图，其中图6A是根据本揭露的一些实施例的半导体装置的俯视图，且图6B是沿着图6A的半导体装置的线B-B的横截面视图。如图6A及图6B中所描绘，半导体装置5的第一半导体裸片60及第二半导体裸片70布置成不同配置。第二导体20可布置于不同于图5A及图5B中的冷结热区52R的冷结热区52R中以避免冷结。第一导体18可布置于不同于图5A及图5B中的桥接热区52T的桥接热区52T中以避免桥接。
图7A及图7B是根据本揭露的一些实施例的半导体装置的示意图，其中图7A是根据本揭露的一些实施例的半导体装置的俯视图，且图7B是沿着图7A的半导体装置的线C-C的横截面视图。如图7A及图7B中所描绘，半导体装置6的第一半导体裸片60及第二半导体裸片70布置成不同配置。第二导体20可布置于不同于图5A及图5B中的冷结热区52R或图6A及图6B中的冷结热区52R的冷结热区52R中以避免冷结。第一导体18可布置于不同于图5A及图5B中的桥接热区52T或图6A及图6B中的桥接热区52T的桥接热区52T中以避免桥接。
图8是根据本揭露的一些实施例的半导体装置的示意图。如图8中所描绘，半导体装置7可进一步包含放置于第一导体18与第二导体20之间的一或多个第三导体19，且第三导体19的宽度W3'介于第一导体18的宽度W1'与第二导体20的宽度W2'之间。在一些实施例中，第一导体18、第二导体20及第三导体19基本上放置于同一层级处，即同一水平处。在一些实施例中，半导体装置7可包含具有不同宽度的三个或多于三个类型的导体。通过实例的方式，导体的宽度可从冷结热区到桥接热区逐渐减小。
图9A、图9B、图9C及图9D是在根据本揭露的一或多个实施例的制造半导体装置的各种操作中的一个时的示意图。如图9A及图9B中所描绘，接收包含第一表面10A及与第一表面10A相对的第二表面10B的衬底10。封装80形成于衬底10的第一表面10A上方。在一些实施例中，封装80包含中介层82、在中介层82上方且通过导电结构85电连接到中介层82的一或多个半导体裸片84及覆盖(若干)半导体裸片84的模制层86。封装80可进一步包含在中介层82与衬底10之间且电连接到中介层82及衬底10的导电结构88。在一些实施例中，封装80放置于衬底10的第一表面10A上方。第一导体18及第二导体20形成于衬底10上方且电连接到封装80。在一些实施例中，第一导体18及第二导体20形成于衬底10的第二表面10B上方。在一些实施例中，第二导体20的体积大于第一导体18的体积。在一些实施例中，第二导体20的宽度W2基本上等于第一导体18的宽度W1。在一些实施例中，第二导体20的高度H2大于第一导体18的高度H1。在一些实施例中，第一导体18及第二导体20可通过(例如)前述实施例中所描述的方法来形成，但不限于此。在一些实施例中，第二导体20在封装80下方，且第一导体18在衬底的边缘10E的近端。
如图9C及图9D中所描述，衬底10通过第一导体18及第二导体20接合到且电连接到电子组件30以形成半导体装置8。在一些实施例中，电子组件30可包含印刷电路板(PCB)或类似者，且半导体装置8可包含衬底上晶片上芯片(CoWoS)结构。在接合衬底10及电子组件30之后，第二导体20的高度H2'及第一导体18的高度H1'可基本上相同，且第二导体20的宽度W2'可大于第一导体18的宽度W1'。在一些实施例中，具有较大高度的第二导体20可帮助避免由于扭曲或其它原因而出现冷结。在一些实施例中，具有较小高度的第一导体18可帮助避免由于扭曲或其它原因而出现桥接(即，邻近导体之间的短路)。在一些实施例中，第二导体20可经配置以形成于其中趋向于发生冷结的冷结热区中，而第一导体18可经配置以形成于其中趋向于发生桥接的桥接热区中。在一些实施例中，半导体装置8可为包含彼此堆叠的两个或多于两个电子组件或衬底的三维封装结构，且第一导体18及第二导体20可形成于邻近电子组件或衬底中的任何两个中。
图10是根据本揭露的一些实施例的半导体装置的示意图。如图10中所描绘，半导体装置9可进一步包含放置于第一导体18与第二导体20之间的一或多个第三导体19，且第三导体19的宽度W3'介于第一导体18的宽度W1'与第二导体20的宽度W2'之间。在一些实施例中，第二导体20的高度H2'、第一导体18的高度H1'及第三导体19的高度H3'可基本上相同。在一些实施例中，半导体装置9可包含具有不同宽度的三个或多于三个类型的导体。通过实例的方式，导体的宽度可从衬底10的中心到衬底10的边缘逐渐减小。
在本揭露的一些实施例中，具有不同体积及/或高度的两个或多于两个类型的导体形成于衬底的不同区域处以分别缓解由于扭曲或其它原因而出现冷结问题及桥接问题。两个或多于两个类型的导体在衬底接合到电子组件之后可具有基本上相同高度，但其可在半导体装置的制造期间缓解冷结问题及桥接问题。导体的不同宽度可通过修改相应导体的体积或组合物、使用具有不同宽度的凹部的焊料掩模、修改相应接合垫的宽度或类似者来控制。
在一个示范性方面中，一种半导体装置包含衬底、封装、第一导体及第二导体。所述衬底包含第一表面及与所述第一表面相对的第二表面。所述封装放置于所述衬底上方。所述第一导体放置于所述衬底上方。所述第二导体放置于所述衬底上方，其中所述第一导体及所述第二导体基本上处于同一层级，且所述第二导体的宽度大于所述第一导体的宽度。
在另一方面中，一种半导体装置包含衬底、封装、第一导体及第二导体。所述衬底包含第一表面及与所述第一表面相对的第二表面。所述封装放置于所述衬底上方。所述第一导体放置于所述衬底上方。所述第二导体放置于所述衬底上方，其中所述第一导体及所述第二导体基本上处于同一层级，且所述第二导体的体积大于所述第一导体的体积。
在又一方面中，一种用于制造半导体装置的方法包含：接收衬底；在所述衬底上方形成第一导体及第二导体，其中所述第二导体的高度大于所述第一导体的高度；且通过所述第一导体及所述第二导体将所述衬底接合到电子组件。
前文概述数个实施例的结构使得所属领域的技术人员可更好地理解本揭露的方面。所属领域的技术人员应了解，其可容易地使用本揭露作为设计或修改用于实施相同目的及/或实现本文中介绍的实施例的相同优点的其它过程及结构的基础。所属领域的技术人员还应认识到，此类等效构造不背离本揭露的精神及范围，且其可在不背离本揭露的精神及范围的情况下在本文中做出各种改变、替代及变更。

Claims (1)

1.一种半导体装置，其包括：
衬底，其包含第一表面及与所述第一表面相对的第二表面；
封装，其在所述衬底上方；
多个第一导体，其在所述衬底上方；及
多个第二导体，其在所述衬底上方，其中所述多个第一导体及所述多个所述第二导体基本上处于同一层级，且所述第二导体的宽度大于所述第一导体的宽度。
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