CN109411574A - 均匀半导体纳米线和纳米片发光二极管 - Google Patents

均匀半导体纳米线和纳米片发光二极管 Download PDF

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CN109411574A
CN109411574A CN201711452325.3A CN201711452325A CN109411574A CN 109411574 A CN109411574 A CN 109411574A CN 201711452325 A CN201711452325 A CN 201711452325A CN 109411574 A CN109411574 A CN 109411574A
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D·K·纳亚克
S·R·班纳
A·P·雅各布
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Abstract

本发明涉及均匀半导体纳米线和纳米片发光二极管。本公开涉及半导体结构，并且更具体地涉及均匀半导体纳米线和纳米片发光二极管及其制造方法。该结构包括缓冲层；在所述缓冲层上的至少一个电介质层，所述至少一个电介质层具有暴露所述缓冲层的多个开口；以及形成在所述开口中并且在所述至少一个电介质层上方延伸的多个尺寸和形状均匀的纳米线或纳米片。

Description

均匀半导体纳米线和纳米片发光二极管
技术领域
本公开涉及半导体结构，更特别地，涉及均匀半导体纳米线和纳米片发光二极管及其制造方法。
背景技术
发光二极管(LED)需要光学透明且高度导电的电极。在LED中，除了诸如作为电化学活性的感应的电解质的介质之外，材料还与电荷收集器接触。当适当的电压施加到LED器件的引线上时，电子能够与LED器件内的电子空穴复合，以光子的形式释放能量。
二维(2D)LED是平面器件，该平面器件发射来自它们的平坦表面处或附近的薄层材料的光。另一方面，在三维(3D)LED中，光能够从器件的所有侧面发射。3D LED的制造带来许多问题，包括纳米线和纳米片的微加载以及由于不均匀直径的纳米线或纳米片LED引线导致的光谱扩展和产量损失。
发明内容
在本公开的一个方面中，一种结构包括：缓冲层；位于所述缓冲层上的至少一个电介质层，所述至少一个电介质层具有暴露所述缓冲层的多个开口；以及形成在所述开口中并在所述至少一个电介质层上方延伸的多个尺寸和形状均匀的纳米线或纳米片。
在本公开的一个方面中，一种方法包括：在缓冲层上形成第一电介质材料；在所述第一电介质上形成第二电介质；蚀刻通过所述结构的所述第一电介质和所述第二电介质的多个开口，所述蚀刻在所述缓冲层上停止；用种子材料填充所述多个开口；以及去除所述结构的所述第二电介质以暴露与所述多个开口的形状一致的多个纳米线或纳米片种子。
在本公开的一个方面中，一种方法包括：直接在缓冲层上形成第一电介质材料；直接在所述第一电介质材料上形成第二电介质材料；蚀刻穿过所述第一电介质材料和所述第二电介质材料的多个开口，暴露所述缓冲层；在所述多个开口中从所述暴露的缓冲层生长纳米线或纳米片种子；去除所述第二电介质材料以部分地暴露与所述多个开口的形状一致的多个形状均匀的纳米线或纳米片；在所述形状均匀的纳米线或纳米片的侧壁上形成多个量子阱；以及在所述多个量子阱中的每一个的侧壁上形成至少一种材料。
附图说明
通过本公开的示例性实施例的非限制性实例并参考所述多个附图，在以下详细描述中描述本公开。
图1示出了根据本发明的方面的引入结构以及相应的制造工艺。
图2示出了根据本公开的方面的除了其他特征之外的电介质材料的开口中的纳米线/纳米片以及相应的制造工艺。
图3示出了根据本公开的方面的除了其他特征之外的均匀纳米线/纳米片以及相应的制造工艺。
图4示出了根据本公开的方面的除了其他特征之外的纳米线/纳米片发光二极管(LED)以及相应的制造工艺。
具体实施方式
本公开涉及半导体结构，更特别地，涉及均匀半导体纳米线和纳米片发光二极管及其制造方法。更具体地，本公开涉及具有均匀纳米线或纳米片的3D LED。有利地，与二维(2D)LED相比，本公开减少了制造成本。具体而言，本公开可以将制造成本降低为大约2DLED的三分之一。此外，本公开提供了相同尺寸的纳米线或纳米片和相同的带隙，其导致更紧凑的光谱分布和制造产量。
在本公开中，纳米线或纳米片可以以均匀的形状生长，例如相同的圆形或矩形形状。这是通过在电介质材料中形成均匀形状的开口中生长纳米线或纳米片来实现的。在实施例中，通过例如CMOS工艺的常规图案化和蚀刻工艺来制造开口，其导致从像素到像素以及从晶片到晶片的纳米线或纳米片种子直径的精确控制。由此，在本公开中，制造工艺获得均匀尺寸的纳米线或纳米片LED。
本公开的纳米线或纳米片LED结构可以使用多种不同的工具以多种方式制造。一般而言，方法和工具被用于形成具有微米和纳米尺寸的结构。已从集成电路(IC)技术中采用了用于制造本公开的半导体结构的方法，即，技术。例如，纳米线或纳米片LED结构被建立在晶片上，并且以通过在晶片的顶部上进行光刻工艺图案化的材料膜来实现。特别地，纳米线或纳米片LED结构的制造使用三个基本构建块：(i)材料的沉积，(ii)通过光刻成像施加图案化的掩模，以及(iii)选择性地将材料蚀刻到掩模。
图1示出根据本公开的方面的引入结构以及相应的制造工艺。更具体地，图1的结构10包括半导体或绝缘材料20。在实施例中，半导体或绝缘材料20可以由例如Si、蓝宝石、SiC或玻璃组成。在材料20上形成缓冲层30。缓冲层30可以是例如具有晶体结构的GaN或金属氮化物或者例如AlN、WN等的其它金属缓冲层。在实施例中，缓冲层30将在随后的蚀刻工艺期间充当蚀刻停止层。在实施例中，GaN层可以通过金属有机化学气相沉积(MOCVD)工艺来沉积，其厚度为大约500nm至5微米。可选地，可以通过等离子体增强化学气相沉积(PECVD)工艺或其他化学气相沉积(CVD)工艺来沉积金属氮化物，其厚度大约为50nm至150nm。
仍然参考图1，在缓冲层30上形成电介质材料40。电介质材料40可以是例如SiN或氧化物。在实施例中，缓冲层30可以是钝化层，以抑制或增强GaN材料的后续生长。在电介质40上形成电介质材料50。电介质材料50可以是SiN或氧化物。然而，应理解，电介质材料40和电介质材料50应当优选地具有不同的材料以在随后的处理步骤中实现蚀刻选择性。
在图1中，通过电介质材料40和电介质材料50形成开口55，暴露下面的缓冲层30。在实施例中，开口55可以使用常规的光刻和反应离子蚀刻(RIE)工艺形成。例如，将形成在电介质材料50之上的抗蚀剂暴露于能量(光)以形成图案(开口)。将例如反应离子蚀刻(RIE)的具有选择性化学的蚀刻工艺用于通过抗蚀剂的开口在电介质材料40和电介质材料50中形成一个或多个开口。蚀刻工艺将在蚀刻停止层30上停止。然后可以通过传统的氧灰化工艺或其他已知的剥离剂(stripant)来去除抗蚀剂。
在实施例中，开口55是均匀的，例如具有相同的尺寸。在实施例中，开口55可被改变到不同的尺寸以控制和调整LED的颜色。例如，开口55的尺寸可以在约50nm至1微米的范围内，其中70nm是一个优选实施例。在另外的实施例中，开口55可以是大约150nm至500nm，并且优选地在150nm至大约200nm之间等，以在LED中发射不同的颜色。在实施例中，开口55可以是圆形、矩形或其他形状，其全部具有相同的均匀形状以包含例如用于纳米线的种子材料等的LED材料的生长。
图2示出了根据本公开的方面的除了其他特征之外的电介质材料中的纳米线/纳米片以及相应的制造工艺。更具体地，在实施例中，在开口55内形成例如GaN材料的种子材料以形成纳米线/纳米片60。在实施例中，种子材料可以从暴露的缓冲层30开始在开口55中外延生长以形成多个纳米线/纳米片60。如本领域技术人员应理解的，种子材料将与开口55的形状一致，从而基于开口55的均匀尺寸(例如，尺寸和形状)形成各自具有相同尺寸和形状的纳米线/纳米片60。
在图3中，去除电介质材料50，部分暴露均匀纳米线/纳米片60。更具体地，通过使用选择性蚀刻化学，可以去除电介质材料50而不去除电介质材料40。以这种方式，均匀的纳米线/纳米片60将保留，在电介质材料40上方延伸。
图4示出了根据本公开的方面的除了其他特征之外的纳米线/纳米片发光二极管(LED)以及相应的制造工艺。具体而言，图4示出了形成在每个纳米线/纳米片60上的多个量子阱70。量子阱70可以是在纳米线/纳米片60的侧面上生长的例如GaN和InGaN。应理解，电介质材料40将阻止量子阱70在电介质材料40上的生长。在量子阱70之上形成材料80。更具体地，材料80是例如p型GaN。纳米线/纳米片60、量子阱70和材料80的组合将形成均匀的纳米线/纳米片LED 90。在形成均匀的纳米线/纳米片LED 90之后，可以使用常规的CMOS工艺制造接触和后端制程结构。
如上所述的方法用在集成电路芯片的制造中。所得到的集成电路芯片可以由制造商以作为裸芯片的原始晶片形式(即，作为具有多个未封装芯片的单个晶片)或者以封装形式分发。在后一种情况下，芯片被安装在单芯片封装(诸如塑料载体中，其引线固定到母板或其他更高级别的载体)或多芯片封装(诸如陶瓷载体中，其具有表面互连和/或掩埋互连中的一者或两者)中。在任何情况下，芯片然后与其他芯片、分立电路元件和/或其他信号处理设备集成，作为(a)中间产品(诸如母板)或者(b)最终产品的一部分。最终产品可以是包括集成电路芯片的任何产品，从玩具和其他低端应用，到具有显示器、键盘或其他输入设备以及中央处理器的高级计算机产品。
本公开的各种实施例的描述已为了示例的目的而给出，但并非旨在是穷举性的或限于所公开的实施例。在不脱离所描述的实施例的范围和精神的情况下，许多修改和变化对于本领域普通技术人员将是显而易见的。本文中所用术语的被选择以旨在最好地解释实施例的原理、实际应用或对市场中发现的技术的技术改进，或者使本技术领域的其他普通技术人员能理解本文公开的实施例。

Claims (20)

1.一种结构，包括：
缓冲层；
位于所述缓冲层上的至少一个电介质层，所述至少一个电介质层具有暴露所述缓冲层的多个开口；以及
形成在所述开口中并在所述至少一个电介质层上方延伸的多个尺寸和形状均匀的纳米线或纳米片。
2.根据权利要求1所述的结构，其中所述多个尺寸和形状均匀的纳米线或纳米片中的每一个具有相同的直径。
3.根据权利要求1所述的结构，进一步包括围绕所述尺寸或形状均匀的纳米线或纳米片的侧壁的多个量子阱。
4.根据权利要求3所述的结构，其中所述量子阱中的每一个包括GaN和InGaN。
5.根据权利要求3所述的结构，进一步包括位于所述量子阱的侧壁上的至少一种材料。
6.根据权利要求5所述的结构，其中所述至少一种材料包括p型GaN。
7.根据权利要求1所述的结构，其中所述缓冲层为GaN。
8.根据权利要求1所述的结构，其中所述缓冲层为金属材料。
9.根据权利要求1所述的结构，其中所述至少一个电介质层包括SiN。
10.根据权利要求1所述的结构，其中所述至少一个电介质层包括氧化物。
11.一种方法，包括：
在缓冲层上形成第一电介质材料；
在所述第一电介质上形成第二电介质；
蚀刻通过所述结构的所述第一电介质和所述第二电介质的多个开口，所述蚀刻在所述缓冲层上停止；
用种子材料填充所述多个开口；以及
去除所述结构的所述第二电介质以暴露与所述多个开口的形状一致的多个纳米线或纳米片种子。
12.根据权利要求11所述的方法，进一步包括在所述纳米线或纳米片种子的侧壁上形成多个量子阱并且在所述多个量子阱的侧壁上形成至少一种材料。
13.根据权利要求12所述的方法，其中，所述量子阱中的每一个由GaN和InGaN构成。
14.根据权利要求12所述的方法，其中所述纳米线或纳米片种子由通过所述多个开口在所述缓冲层的暴露部分上生长的GaN或InGaN构成。
15.根据权利要求12所述的方法，其中所述至少一种材料包括p型GaN。
16.根据权利要求11所述的方法，其中所述缓冲层由GaN构成。
17.根据权利要求11所述的方法，其中所述第一电介质和所述第二电介质材料是不同的材料。
18.一种方法，包括：
直接在缓冲层上形成第一电介质材料；
直接在所述第一电介质材料上形成第二电介质材料；
蚀刻穿过所述第一电介质材料和所述第二电介质材料的多个开口，暴露所述缓冲层；
在所述多个开口中从所述暴露的缓冲层生长纳米线或纳米片种子；
去除所述第二电介质材料以部分地暴露与所述多个开口的形状一致的多个形状均匀的纳米线或纳米片；
在所述形状均匀的纳米线或纳米片的侧壁上形成多个量子阱；以及
在所述多个量子阱中的每一个的侧壁上形成至少一种材料。
19.根据权利要求18所述的方法，其中所述纳米线或纳米片种子是在所述缓冲层上外延生长的GaN材料。
20.根据权利要求18所述的方法，其中所述缓冲层为GaN材料。
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