TWI679775B - 均勻半導體奈米線與奈米片發光二極體 - Google Patents
均勻半導體奈米線與奈米片發光二極體 Download PDFInfo
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Abstract
本發明所揭示內容係關於半導體結構，尤其係關於均勻半導體奈米線與奈米片發光二極體及製造方法。該結構包括一緩衝層；至少一個介電層，其在該緩衝層上，該至少一個介電層具有暴露該緩衝層的複數開口；以及複數大小均勻且成形的奈米線或奈米片，其形成在該等開口中且延伸於該至少一個介電層上方。
Description
本發明所揭示內容係關於半導體結構，尤其係關於均勻半導體奈米線與奈米片發光二極體及製造方法。
發光二極體(Light emitting diode，LED)需要光學透明且高度導電的電極。在LED中，除了感應電化學活性的電解質等介質之外，材料還會與電荷收集器接觸。當適合的電壓施加於該LED裝置的引線時，電子能夠與該LED裝置內的電洞再結合，從而釋放出光子形式的能量。
二維(two-dimensional，2D)LED係從其平坦表面或附近的材料薄層發出光的平面裝置。另一方面，在三維(three-dimensional，3D)LED中，光能夠從裝置的所有側面皆發出。3D LED的製造帶來許多問題，其中包括奈米線與奈米片的微負載效應(micro-loading)，以及由於奈米線或奈米片LED引線的直徑不均勻所導致的光譜分散(spectral spread)和良率損失。
在所揭示內容的態樣中，一種結構包含：一緩衝層；至少一個介電層，其在該緩衝層上，該至少一個介電層具有暴露該緩衝層的複數開口；以及複數大小均勻且成形的奈米線或奈米片，其形成在該等開口中 且延伸於該至少一個介電層上方。
在所揭示內容的態樣中，一種方法包含：在一緩衝層上形成一第一介電體材料；在該第一介電體上形成一第二介電體；蝕刻複數開口穿越該結構的第一介電體和第二介電體而停止於該緩衝層上；採用晶種材料填充該等複數開口；以及去除該結構的第二介電體，以暴露與該等複數開口的一形狀一致的複數奈米線或奈米片晶種。
在所揭示內容的態樣中，一種方法包含：直接在一緩衝層上形成一第一介電體材料；直接在該第一介電體材料上形成一第二介電體材料；蝕刻複數開口穿越該第一介電體材料和該第二介電體材料，從而暴露該緩衝層；從該所暴露的緩衝層，在該等複數開口中成長奈米線或奈米片晶種；去除該第二介電體材料，以部分地暴露與該等複數開口的一形狀一致的複數均勻地成形的奈米線或奈米片；在該等均勻地成形的奈米線或奈米片的側壁上形成複數量子井；以及在每個該等複數量子井的側壁上皆形成至少一種材料。
10‧‧‧結構
20‧‧‧半導體或絕緣材料；材料
30‧‧‧緩衝層；蝕刻停止層
40‧‧‧介電體材料；介電體
50‧‧‧介電體材料
55‧‧‧開口
60‧‧‧奈米線/奈米片
70‧‧‧量子井
80‧‧‧材料
90‧‧‧均勻奈米線/奈米片發光二極體(LED)
在接下來的實施方式中，將藉由本發明所揭示內容的示例性具體實施例的非限制性範例，參照所提及的複數圖式說明本發明所揭示內容。
圖1顯示依據本發明所揭示內容的各態樣的引入結構和各自製程。
圖2除了其他特徵之外，顯示介電體材料的開口中的奈米線/奈米片，以及依據本發明所揭示內容的各態樣的各自製程。
圖3除了其他特徵之外，顯示均勻奈米線/奈米片，以及依據本發明所揭示內容的各態樣的各自製程。
圖4除了其他特徵之外，顯示奈米線/奈米片發光二極體 (LED)，以及依據本發明所揭示內容的各態樣的各自製程。
本發明所揭示內容係關於半導體結構，尤其係關於均勻半導體奈米線與奈米片發光二極體及製造方法。更具體而言，本發明所揭示內容係針對具有均勻(uniform)奈米線或奈米片的3D LED。具優勢地，相較於二維(2D)LED，本發明所揭示內容可降低製造成本。特別是，本發明所揭示內容可將該製造成本降低為2D LED的大約三分之一。又，本發明所揭示內容提供用於相同大小奈米線或奈米片和相同頻帶間隙，其導致更嚴格的光譜分佈和製造良率。
在本發明所揭示內容中，奈米線或奈米片可以均勻形狀成長，例如相同的圓形(例如具有相同直徑)或矩形形狀。這是透過在介電體材料中均勻地成形的開口中成長奈米線或奈米片達成。在具體實施例中，該等開口係透過慣用佈局圖樣和蝕刻製程(如互補金氧半導體(CMOS)製程)製成，其導致從像素到像素以及從晶圓到晶圓精確控制該奈米線或奈米片晶種直徑。因此，在本發明所揭示內容中，該製程得到大小均勻的該等奈米線或奈米片LED。
本發明所揭示內容的該等奈米線或奈米片LED結構，可使用多種不同的工具以多種方式製造。不過一般來說，該等方法和工具係用於形成具有微米和奈米尺度的結構。用於製造本發明所揭示內容的半導體結構的該等方法(即技術)已從積體電路(Integrated circuit，IC)技術導入。舉例來說，該等奈米線或奈米片LED結構係構建在晶圓上，並係在晶圓頂部上透過光微影製程佈局圖樣的材料膜中實現。特別是，該等奈米線或奈米片LED結構的製造使用三個基本構建區塊：(i)在基板上沉積材料薄膜、(ii)透過光微影成像在該等膜上方施加佈局圖樣的圖罩，以及(iii)對該圖罩選擇性地蝕刻該等膜。
圖1顯示依據本發明所揭示內容的各態樣的引入結構和各自製程。更具體而言，圖1的結構10包括一半導體或絕緣材料20。在具體實施例中，半導體或絕緣材料20可由矽(Si)、藍寶石、碳化矽(SiC)或玻璃等組成。緩衝層30係形成在材料20上。緩衝層30可為具有例如氮化鋁(AlN)、氮化鎢(WN)等晶體結構或其他金屬緩衝層的氮化鎵(GaN)或金屬氮化物等。在該等具體實施例中，緩衝層30將在後續蝕刻製程期間用作蝕刻停止層。在具體實施例中，GaN層可透過厚度約為500nm至5μm的金屬有機化學氣相沉積(Metal organic chemical vapor deposition，MOCVD)製程進行沉積。或者，金屬氮化物可透過電漿輔助化學氣相沉積(Plasma-enhanced chemical vapor deposition，PECVD)製程或其他化學氣相沉積(CVD)製程沉積為約50nm至150nm的厚度。
仍參照圖1，介電體材料40係形成在緩衝層30上。介電體材料40可為例如氮化矽(SiN)或氧化物等。在具體實施例中，緩衝層30可為鈍化(passivated)層，以抑制或增進後續GaN材料的成長。介電體材料50係形成在介電體40上。介電體材料50可為SiN或氧化物。然而，應可理解介電體材料40和介電體材料50較佳應為不同材料，以在後續處理步驟中實行蝕刻選擇性。
在圖1中，開口55係穿越介電體材料40和介電體材料50形成，從而暴露底層的緩衝層30。在具體實施例中，該等開口55可使用慣用微影和活性離子蝕刻(Reactive ion etching，RIE)製程形成。舉例來說，形成在介電體材料50上方的光阻係暴露於能量(光)，以形成佈局圖樣(開口)。例如活性離子蝕刻(RIE)等具有選擇性化學反應的蝕刻製程，將用於穿越該光阻的該等開口在介電體材料40和介電體材料50中形成一個或多個開口。該蝕刻製程將停止於蝕刻停止層30上。該光阻隨後可透過慣用氧氣灰化(ashing)製程或其他已知剝離劑去除。
在具體實施例中，該等開口55為均勻一致，例如具有相同 大小。在具體實施例中，該等開口55可變更為不同尺寸，以控制和調整該等LED的顏色。舉例來說，該等開口55的該等尺寸可在約50nm至1μm的範圍內，其中70nm為一個較佳具體實施例。在進一步具體實施例中，該等開口55可為大約150nm至500nm，且較佳為在150nm至約200nm之間等，以在該等LED中發出不同顏色。在具體實施例中，該等開口55可為圓形、矩形或其他形狀，全部皆為相同的均勻形狀以容納LED材料的成長，例如用於該奈米線的晶種材料等。
圖2除了其他特徵之外，顯示介電體材料中的奈米線/奈米片，以及依據本發明所揭示內容的各態樣的各自製程。更具體而言，在具體實施例中，例如GaN材料等晶種材料係形成在該等開口55內，以形成該等奈米線/奈米片60。在具體實施例中，該晶種材料可在該等開口55中以磊晶方式從所暴露的緩衝層30開始成長，以形成複數奈米線/奈米片60。如熟習此領域技術者應可理解，該晶種材料將符合該等開口55的該等形狀，由此形成每個皆具有基於該等開口55的該等均勻尺寸(如大小和形狀)的相同大小和形狀的奈米線/奈米片60。
在圖3中，介電體材料50係去除，從而部分地暴露該等均勻奈米線/奈米片60。更具體而言，透過使用選擇性蝕刻化學反應，可能去除介電體材料50而無需去除介電體材料40。如此，該等均勻奈米線/奈米片60將維持延伸於介電體材料40上方。
圖4除了其他特徵之外，顯示奈米線/奈米片發光二極體(LED)，以及依據本發明所揭示內容的各態樣的各自製程。特別是，圖4顯示形成在每個該等奈米線/奈米片60上的複數量子井70。該等量子井70可為例如成長在該等奈米線/奈米片60的該等側面上的GaN和氮化銦鎵(InGaN)等。應可理解介電體材料40將防止該等量子井70在介電體材料40上成長。材料80係形成在該等量子井70上方。更具體而言，材料80係例如p型GaN等。該等奈米線/奈米片60、量子井70和材料80的組合，將 形成均勻奈米線/奈米片LED 90。在形成該等均勻奈米線/奈米片LED 90後，該等線結構的接點和其他後端可使用慣用CMOS製程製造。
如以上所說明的該(等)方法係用於製造積體電路晶片。該等所得到的積體電路晶片可由該製造商以原始晶圓形式(即作為具有多個未封裝晶片的單一晶圓)、作為裸晶粒或以封裝形式分銷。在該後者情況下，該晶片係安裝在單晶片封裝(例如塑料載體，具有貼附於主機板或其他更高層級載體的引線)或多晶片封裝(例如陶瓷載體，擇一具有表面內連線或嵌埋內連線或兩者)中。在任何情況下，該晶片隨後皆擇一作為(a)中間產品(例如主機板)或(b)最終產品的一部分與其他晶片、個別電路元件及/或其他信號處理裝置積體化。該最終產品可為包括積體電路晶片的任何產品，範圍從玩具和其他低階應用到具有顯示器、鍵盤或其他輸入裝置和中央處理器的高階電腦產品皆包括。
為了例示目的已描述本發明所揭示內容的該等各種具體實施例的該等說明，但不欲為全面性或限於所揭示的該等具體實施例。對此領域一般技術者而言，將顯而易見許多修飾例和變化例，而不悖離該等所說明的具體實施例的範疇與精神。文中所使用的術語經過選擇，以最好地解說該等具體實施例的該等原理、該整個市場上所找到的技術的實際應用或技術改進，或讓此領域一般技術者能理解文中所揭示的該等具體實施例。
Claims (21)
- 一種半導體結構，包含：一緩衝層；至少一個介電層，其在該緩衝層上，該至少一個介電層具有暴露該緩衝層的複數均勻成形開口；以及複數大小均勻且成形的奈米線或奈米片，其形成在該等均勻成形開口中且延伸於該至少一個介電層上方。
- 如申請專利範圍第1項之半導體結構，其中每個該等複數大小均勻且成形的奈米線或奈米片皆具有一相同直徑。
- 如申請專利範圍第1項之半導體結構，更包含複數量子井，其圍繞該等大小均勻且成形的奈米線或奈米片的側壁。
- 如申請專利範圍第3項之半導體結構，其中每個該等量子井皆包含氮化鎵(GaN)和氮化銦鎵(InGaN)。
- 如申請專利範圍第3項之半導體結構，更包含至少一材料，其在該等量子井的側壁上。
- 如申請專利範圍第5項之半導體結構，其中該至少一材料包含一p型GaN。
- 如申請專利範圍第1項之半導體結構，其中該緩衝層係GaN。
- 如申請專利範圍第1項之半導體結構，其中該緩衝層係一金屬材料。
- 如申請專利範圍第1項之半導體結構，其中該至少一個介電層包含氮化矽(SiN)。
- 如申請專利範圍第1項之半導體結構，其中該至少一個介電層包含氧化物。
- 一種製造一半導體結構的方法，包含：在一緩衝層上形成一第一介電體材料；在該第一介電體上形成一第二介電體；蝕刻複數均勻成形開口穿越該結構的第一介電體和第二介電體，停止於該緩衝層上；採用晶種材料填充該等複數均勻成形開口；以及去除該結構的第二介電體，以暴露與該等複數均勻成形開口的一形狀一致的複數奈米線或奈米片晶種。
- 如申請專利範圍第11項之方法，更包含在該等奈米線或奈米片晶種的側壁上形成複數量子井；以及在該等複數量子井的側壁上形成至少一材料。
- 如申請專利範圍第12項之方法，其中每個該等量子井皆係由GaN和InGaN組成。
- 如申請專利範圍第12項之方法，其中該等奈米線或奈米片晶種係由穿越該等複數開口而成長在該緩衝層的暴露部分上的GaN或InGaN組成。
- 如申請專利範圍第12項之方法，其中該至少一材料包含一p型GaN。
- 如申請專利範圍第11項之方法，其中該緩衝層係由GaN組成。
- 如申請專利範圍第11項之方法，其中該第一介電體和該第二介電體材料係不同材料。
- 一種製造一半導體結構的方法，包含：直接在一緩衝層上形成一第一介電體材料；直接在該第一介電體材料上形成一第二介電體材料；蝕刻複數均勻成形開口穿越該第一介電體材料和該第二介電體材料，從而暴露該緩衝層；從該所暴露的緩衝層，在該等複數均勻成形開口中成長奈米線或奈米片晶種；去除該第二介電體材料，以部分地暴露與該等複數均勻成形開口的一形狀一致的複數均勻地成形的奈米線或奈米片；在該等均勻地成形的奈米線或奈米片的側壁上形成複數量子井；以及在每個該等複數量子井的側壁上皆形成至少一材料。
- 如申請專利範圍第18項之方法，其中該等奈米線或奈米片晶種係該緩衝層上以磊晶方式成長的GaN材料。
- 如申請專利範圍第18項之方法，其中該緩衝層係GaN材料。
- 一種半導體結構，包含：一緩衝層；至少一個介電層，其在該緩衝層上，該至少一個介電層具有暴露該緩衝層的複數開口；以及複數大小均勻且成形的奈米線或奈米片，其形成在該等開口中且延伸於該至少一個介電層上方；其中該緩衝層係一金屬材料。
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| CN102544279B (zh) * | 2010-12-28 | 2016-11-09 | 鸿富锦精密工业（深圳）有限公司 | 发光二极管及其形成方法 |
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