CN109273455A - 3D memory device and its manufacturing method - Google Patents
3D memory device and its manufacturing method Download PDFInfo
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- CN109273455A CN109273455A CN201811095238.1A CN201811095238A CN109273455A CN 109273455 A CN109273455 A CN 109273455A CN 201811095238 A CN201811095238 A CN 201811095238A CN 109273455 A CN109273455 A CN 109273455A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 230000001020 rhythmical effect Effects 0.000 claims abstract description 78
- 238000002955 isolation Methods 0.000 claims abstract description 54
- 239000004020 conductor Substances 0.000 claims abstract description 47
- 239000004065 semiconductor Substances 0.000 claims abstract description 42
- 239000011229 interlayer Substances 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000000463 material Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 14
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 238000010276 construction Methods 0.000 claims description 6
- 238000000926 separation method Methods 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 238000003860 storage Methods 0.000 abstract description 36
- 239000010410 layer Substances 0.000 description 69
- 238000005530 etching Methods 0.000 description 15
- 230000005641 tunneling Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000000059 patterning Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 102100032401 Charged multivesicular body protein 2a Human genes 0.000 description 1
- 102100024827 Dynamin-1-like protein Human genes 0.000 description 1
- 101000943253 Homo sapiens Charged multivesicular body protein 2a Proteins 0.000 description 1
- 101000909218 Homo sapiens Dynamin-1-like protein Proteins 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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Abstract
This application discloses a kind of 3D memory device and its manufacturing methods.The 3D memory device includes: semiconductor substrate；Rhythmic structure of the fence is located in semiconductor substrate, including the grid conductor and interlayer insulating film being alternately stacked；And channel column, run through rhythmic structure of the fence, 3D memory device further includes the second isolation structure through channel column and rhythmic structure of the fence, wherein the second isolation structure separates channel column and rhythmic structure of the fence in the plane parallel with semiconductor substrate surface.Channel column and rhythmic structure of the fence are separated by the second isolation structure, to increase the storage density of 3D memory device, improve the space utilization rate of 3D memory device.
Description
Technical field
The present invention relates to memory technologies, more particularly, to 3D memory device and its manufacturing method.
Background technique
The raising of the storage density of memory device and the progress of semiconductor fabrication process are closely related.With semiconductors manufacture
The characteristic size of technique is smaller and smaller, and the storage density of memory device is higher and higher.In order to further increase storage density,
Develop the memory device (that is, 3D memory device) of three-dimensional structure.3D memory device includes along the multiple of vertical direction stacking
Storage unit can double up integrated level on the chip of unit area, and can reduce cost.
Existing 3D memory device is mainly used as non-volatile flash memory.Two kinds of main non-volatile flash technology difference
Using NAND and NOR structure.Compared with NOR memory device, the reading speed in nand memory part is slightly slow, but writing speed
Fastly, erasing operation is simple, and smaller storage unit may be implemented, to reach higher storage density.Therefore, it uses
The 3D memory device of NAND structure has been widely used.
In the 3D memory device of NAND structure, mainly include rhythmic structure of the fence, through rhythmic structure of the fence channel column with
And conductive channel, the grid conductor of selection transistor and memory transistor is provided using rhythmic structure of the fence, is provided using channel column
The channel layer of selection transistor and memory transistor and gate medium lamination, and the mutual of memory cell string is realized using conductive channel
Even.However, the number of plies with rhythmic structure of the fence is more and more, in rhythmic structure of the fence, grid conductor is led with for separating grid
The insulating layer of body increases simultaneously, and insulating layer occupies a large amount of space in 3D memory device, not only increases 3D memory device
Size, and reduce the utilization rate in space.
It is expected that the structure and its manufacturing method of 3D memory device are further improved, so that the storage for improving 3D memory device is close
Degree reduces the size of 3D memory device.
Summary of the invention
The object of the present invention is to provide a kind of improved 3D memory device and its manufacturing methods, will by the second isolation structure
Channel column and rhythmic structure of the fence separate, and storage unit is increased one times, so that the storage density of 3D memory device is increased,
Improve the space utilization rate of 3D memory device.
According to an aspect of the present invention, a kind of 3D memory device is provided, comprising: semiconductor substrate；Rhythmic structure of the fence is located at
In the semiconductor substrate, including the grid conductor and interlayer insulating film being alternately stacked；And channel column, run through the gate stack
Structure, the 3D memory device further include the second isolation structure through the channel column and the rhythmic structure of the fence, wherein institute
The second isolation structure is stated in the plane parallel with the semiconductor substrate surface by the channel column and the gate stack knot
Structure separates.
It preferably, further include the first isolation structure with the rhythmic structure of the fence through the channel column, described first
The rhythmic structure of the fence is divided into the first rhythmic structure of the fence and second rhythmic structure of the fence by isolation structure, is partly led with described
On the vertical direction in body substrate surface, the grid of the grid conductor of first rhythmic structure of the fence and second rhythmic structure of the fence
Conductor is arranged in a staggered manner.
Preferably, first isolation structure divides equally the channel column along the first direction, second isolation junction
Structure divides equally the channel column along the second direction.
Preferably, the first direction and the angle of the second direction are 90 degree.
Preferably, the material of first isolation structure includes silicon carbide.
Preferably, the material of the interlayer insulating film of first rhythmic structure of the fence is selected from oxide and one in nitride
Kind, another kind of the material of the interlayer insulating film of second rhythmic structure of the fence in oxide and nitride.
Preferably, first isolation structure divides equally the channel column.
Preferably, the multiple channel column is arranged in array, and the channel column of channel column and adjacent column described in each column is wrong
Position arrangement.
Preferably, channel column described in each column is separated by same first isolation structure.
Preferably, further include grid line gap, run through the rhythmic structure of the fence, the multiple channel column is located at grid line seam
Between gap.
According to another aspect of the present invention, a kind of method for manufacturing 3D memory device is provided, comprising: on a semiconductor substrate
Rhythmic structure of the fence is formed, including the grid conductor and interlayer insulating film being alternately stacked；And it is formed through the rhythmic structure of the fence
Channel column, the method also includes forming the second isolation structure through the channel column and the rhythmic structure of the fence, wherein described
Second isolation structure is in the plane parallel with the semiconductor substrate surface by the channel column and the rhythmic structure of the fence
Separate.
Preferably, further include forming the first isolation structure through the channel column, the rhythmic structure of the fence is separated into the
One rhythmic structure of the fence and the second rhythmic structure of the fence separate, wherein described on the direction vertical with the semiconductor substrate surface
The grid conductor of the grid conductor of first rhythmic structure of the fence and second rhythmic structure of the fence is arranged in a staggered manner.
3D memory device according to an embodiment of the present invention and its manufacturing method, by the second isolation structure by channel column and
Rhythmic structure of the fence separates in the plane parallel with semiconductor substrate, utilizes the channel column and the corresponding part channel column of separation
Grid conductor be respectively formed storage unit, storage unit increases one times, to increase the storage density of 3D memory device,
The space utilization rate of 3D memory device is improved, compared with prior art, the 3D memory device of the embodiment of the present invention and its manufacture
Method only needs that the second isolation structure is arranged through channel column and rhythmic structure of the fence, instead of increasing gate stack in the prior art
The method of structure level number has achieved the purpose that reduce 3D memory device size.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from.
The equivalent circuit diagram and structural schematic diagram of the memory cell string of 3D memory device is shown respectively in Fig. 1 a and 1b.
Fig. 2 a shows the perspective view of 3D memory device according to a first embodiment of the present invention.
Fig. 2 b shows the perspective view of 3D memory device according to a second embodiment of the present invention.
Fig. 3, Fig. 4, Fig. 6, Fig. 7, Fig. 9, Figure 10, Figure 12 show 3D memory according to a second embodiment of the present invention to Figure 14
The sectional view in each stage of part manufacturing method.
Fig. 5, Fig. 8, Figure 11 show each stage of 3D memory device manufacturing method according to a second embodiment of the present invention
Top view.
Figure 15 a to 16c shows the effect analysis schematic diagram of 3D memory device according to an embodiment of the present invention.
Specific embodiment
Hereinafter reference will be made to the drawings, and the present invention will be described in more detail.In various figures, identical element is using similar attached
Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown certain
Well known part.For brevity, the semiconductor structure obtained after several steps can be described in a width figure.
It should be appreciated that being known as being located at another floor, another area when by a floor, a region in the structure of outlines device
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If will use " directly exist ... herein to describe located immediately at another layer, another region above scenario
Above " or " ... abut above and therewith " form of presentation.
Many specific details of the invention, such as structure, material, size, the processing work of device is described hereinafter
Skill and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can not press
The present invention is realized according to these specific details.
The present invention can be presented in a variety of manners, some of them example explained below.
The circuit diagram and structural schematic diagram of the memory cell string of 3D memory device is shown respectively in Fig. 1 a and 1b.In the embodiment
Shown in memory cell string include 4 storage units situation.It is appreciated that the invention is not limited thereto, in memory cell string
Number of memory cells can be to be any number of, for example, 32 or 64.
As shown in Figure 1a, the first end of memory cell string 100 is connected to bit line (Bit-Line, BL), and second end is connected to
Source electrode line (Source Line, SL).Memory cell string 100 includes the multiple crystalline substances being connected in series between the first end and a second end
Body pipe, comprising: first choice transistor Q1, memory transistor M1 to M4 and the second selection transistor Q2.First choice crystal
The grid of pipe Q1 is connected to string selection line (Selection Gate for Drain, SGD), the grid of the second selection transistor Q2
It is connected to source selection line (Selection Gate for Source, SGS).The grid of memory transistor M1 to M4 is separately connected
To the respective word of wordline (Word-Line) WL1 to WL4.
As shown in Figure 1 b, the selection transistor Q1 and Q2 of memory cell string 100 respectively include grid conductor 122 and 123, deposit
Storage transistor M1 to M4 respectively includes grid conductor 121.Crystal in grid conductor 121,122 and 123 and memory cell string 100
The stacking order of pipe is consistent, is separated each other using interlayer insulating film between adjacent grid conductor, to form rhythmic structure of the fence.
Further, memory cell string 100 includes channel column 110.Channel column 110 is adjacent with rhythmic structure of the fence or runs through gate stack knot
Structure.In the middle section of channel column 110, tunneling medium layer 112, charge storage are accompanied between grid conductor 121 and channel layer 111
Layer 113 and gate dielectric layer 114, to form memory transistor M1 to M4.At the both ends of channel column 110,122 He of grid conductor
Gate dielectric layer 114 is accompanied between 123 and channel layer 111, to form selection transistor Q1 and Q2.
In this embodiment, channel layer 111 is for example made of polysilicon, and tunneling medium layer 112 and gate dielectric layer 114 are distinguished
It is made of oxide, such as silica, charge storage layer 113 is made of the insulating layer comprising quantum dot or nanocrystal, example
The silicon nitride of particle such as comprising metal or semiconductor, grid conductor 121,122 and 123 is made of metal, such as tungsten.Channel
Layer 111 is for providing control selection transistor and controlling the channel region of transistor, the doping type and selection transistor of channel layer 111
It is identical with the control type of transistor.For example, the selection transistor and control transistor, channel layer 111 for N-type can be N
The polysilicon of type doping.
In this embodiment, the core of channel column 110 is channel layer 111, tunneling medium layer 112,113 and of charge storage layer
Gate dielectric layer 114 forms the laminated construction for surrounding core wall.In alternate embodiments, the core of channel column 110 is additional
Insulating layer, channel layer 111, tunneling medium layer 112, charge storage layer 113 and gate dielectric layer 114 are formed around semiconductor layer
Laminated construction.
In this embodiment, selection transistor Q1 and Q2, memory transistor M1 to M4 use public channel layer 111 and grid
Dielectric layer 114.In channel column 110, channel layer 111 provides the source-drain area and channel layer of multiple transistors.In the implementation of substitution
Example in, can use step independent of one another, be respectively formed selection transistor Q1 and Q2 semiconductor layer and gate dielectric layer and
The semiconductor layer and gate dielectric layer of memory transistor M1 to M4.In channel column 110, the semiconductor layer of selection transistor Q1 and Q2
It is electrically connected to each other with the semiconductor layer of memory transistor M1 to M4.
In write operation, memory cell string 100 writes data into memory transistor M1 into M4 using FN tunneling effect
Selected memory transistor.By taking memory transistor M2 as an example, while source electrode line SL ground connection, source selection line SGS is biased to greatly
About zero volts, so that the selection transistor Q2 corresponding to source selection line SGS is disconnected, string selection line SGD is biased to high voltage
VDD, so that corresponding to the selection transistor Q1 conducting of string selection line SGD.Further, bit line BL2 is grounded, wordline WL2 biasing
In program voltage VPG, such as 20V or so, remaining wordline is offset to low-voltage VPS1.Due to only selected memory transistor M2's
Word line voltage is higher than tunneling voltage, and therefore, the electronics of the channel region of memory transistor M2 is reached via tunneling medium layer 112
Charge storage layer 113, so that data are transformed into charge storage in the charge storage layer 113 of memory transistor M2.
In read operation, selected memory transistor of the memory cell string 100 according to memory transistor M1 into M4 is led
Logical state judges the quantity of electric charge in charge storage layer, to obtain the data of quantity of electric charge characterization.By taking memory transistor M2 as an example,
Wordline WL2, which is offset to, reads voltage VRD, remaining wordline is offset to high voltage VPS2.The on state of memory transistor M2 and its
Threshold voltage is related, i.e., related to the quantity of electric charge in charge storage layer, thus can be with according to the on state of memory transistor M2
Judge data value.Memory transistor M1, M3 and M4 are in the conductive state always, and therefore, the on state of memory cell string 100 takes
Certainly in the on state of memory transistor M2.Control circuit is according to the electric signal judgement storage detected on bit line BL and source electrode line SL
The on state of transistor M2, to obtain the data stored in memory transistor M2.
Fig. 2 a shows the perspective view of 3D memory device according to a first embodiment of the present invention.For the sake of clarity, in Fig. 2 a
In illustrate only the first isolation structure of part 102, do not show that other in the 3D memory device of first embodiment of the invention
Insulating layer.
As shown in Figure 2 a, 3D memory device shown in the present embodiment includes: semiconductor substrate 101, is located at semiconductor lining
Multiple channel columns 110, the first gate stack knot adjacent above semiconductor substrate 101 and with channel column 110 of 101 top of bottom
Structure 120a and the second rhythmic structure of the fence 120b, the first isolation structure 102 through channel column 110, wherein the first rhythmic structure of the fence
120a includes multiple grid conductor 121a, 122a, the 123a and multiple interlayer insulating films being alternately stacked, the second rhythmic structure of the fence
120b includes multiple grid conductor 121b, 122b, the 123b and multiple interlayer insulating films being alternately stacked.
Multiple channel columns 110 are arranged in array, 110 Heterogeneous Permutation of channel column of each column channel column 110 and adjacent column, identical
The channel column 110 of column is separated and is divided equally by same first isolation structure 102, meanwhile, the first isolation structure 102 also folds the first grid
Layer structure 120a and the second rhythmic structure of the fence 120b separates.
On the direction vertical with 101 surface of semiconductor substrate, the grid conductor 121a of the first rhythmic structure of the fence 120a,
Grid conductor 121b, 122b, 123b of 122a, 123a and the second rhythmic structure of the fence 120b are arranged in a staggered manner, to realize this implementation
3D memory device shown in example includes that 2*n amounts to 2n memory cell string, and wherein n is the number of channel column 110.
Fig. 2 b shows the perspective view of 3D memory device according to a second embodiment of the present invention.For the sake of clarity, in Fig. 2 b
In each insulating layer in 3D memory device is not shown.
As shown in Figure 2 b, 3D memory device shown in the present embodiment includes: semiconductor substrate 101, is located at semiconductor lining
Multiple channel columns 110, the first gate stack knot adjacent above semiconductor substrate 101 and with channel column 110 of 101 top of bottom
Structure 120a and the second rhythmic structure of the fence 120b, through channel column 110 the first isolation structure 102 and run through rhythmic structure of the fence
Grid line gap 103, wherein the first rhythmic structure of the fence 120a includes multiple grid conductor 121a, 122a, the 123a being alternately stacked
With multiple interlayer insulating films, the second rhythmic structure of the fence 120b include multiple grid conductor 121b, 122b, the 123b being alternately stacked and
Multiple interlayer insulating films.
Multiple channel columns 110 are arranged in array, between grid line gap 103, each column channel column 110 and adjacent column
The rhythmic structure of the fence of 110 Heterogeneous Permutation of channel column, 110 two sides of channel column is separated by the first isolation structure through channel column 110,
And the grid conductor of 110 side of channel column is opposite with the interlayer insulating film of the other side, realizes the staggered floor arrangement of grid conductor, this
Outside, the grid conductor of 110 two sides of channel column is divided at least two parts by the second isolation structure respectively, to realize this implementation
3D memory device shown in example includes that 2*2*n amounts to 4n memory cell string, and wherein n is the number of channel column 110.
In the 3D memory device of the present embodiment, each channel column 110 is isolated structure and is divided into 4 parts, storage unit
String respectively includes part and grid conductor corresponding to respective channel column 110.In grid conductor and memory cell string 100
The stacking order of transistor is consistent, is separated each other using interlayer insulating film between adjacent grid conductor, to form gate stack
Structure.
Preferably, for example including cmos circuit in substrate semiconductor substrate 101.Cmos circuit is provided using conductive channel
Being electrically connected between external circuit.
Preferably, 3D memory device shown in the present embodiment further includes false channel column 140, is made for providing mechanical support
With.
Fig. 3, Fig. 4, Fig. 6, Fig. 7, Fig. 9, Figure 10, Figure 12 show 3D memory according to a second embodiment of the present invention to Figure 14
The sectional view in each stage of part manufacturing method, Fig. 5, Fig. 8, Figure 11 show 3D memory device according to a second embodiment of the present invention
The top view in each stage of manufacturing method.It is carried out below in conjunction with manufacturing method of the Fig. 3 to Figure 14 to invention memory construction
Detailed description.
The method of the present embodiment manufacture 3D memory device starts from semiconductor substrate 101, is formed absolutely in semiconductor substrate 101
Edge laminated construction 130, as shown in Figure 3.
In this step, can use depositing operation stacked in semiconductor substrate 101 first interlayer insulating film 131 with
Second interlayer insulating film 132, wherein the material of the first interlayer insulating film 131 be selected from one of oxide and nitride, second
Another kind of the material of interlayer insulating film 132 in oxide and nitride.In the present embodiment, the first interlayer insulating film
131 material is oxide, and the material of the second interlayer insulating film 132 is nitride.
Further, multiple first isolation structures 102 are formed through insulating laminate structure 130, the first isolation structure 102 prolongs
It extends in semiconductor substrate 101, as shown in figure 4,
In this step, etching technics patterning insulating laminate structure 130 and part semiconductor substrate 101 be can use,
A plurality of gap is formed, and is used to form the material of the first isolation structure 102 in gap filling, wherein the first isolation structure 102
Material includes silicon carbide.
Further, multiple channel columns 110 are formed through insulating laminate structure 130, as shown in Figures 5 to 7, wherein Fig. 6
For the sectional view in Fig. 5 along line A-A or the sectional view of line B-B, Fig. 7 Fig. 5 along line C-C.
In this step, it can use etching technics patterning insulating laminate structure 130, form multiple channel holes, then
In channel hole, inner wall sequentially forms gate dielectric layer 114, charge storage layer 113, tunneling medium layer 112 and channel layer 111, most
Forming contact zone 115 afterwards forms channel column 110 for source contact by semiconductor substrate 101.Wherein, the first isolation structure
102 separate the insulating laminate structure 130 of 110 two sides of channel column.
Preferably, the first isolation structure 102 divides equally channel column 110 along first direction.
Preferably, in this step, can also form the false channel column through insulating laminate structure 130, false channel column with
The internal structure of channel column 110 can be identical or different, and leads at least across at least part grid in rhythmic structure of the fence
Body.In final 3D memory device, false channel column is not connected with bit line, is not also used to form selection transistor and deposits
Store up transistor.Therefore, false channel column does not form effective storage unit.
Further, through insulating laminate structure 130 and around multiple channel columns 110 formed grid line gap 103, as Fig. 5,
Shown in Fig. 6, wherein multiple channel columns 110 are between grid line gap 103.
Further, form the second isolation structure 104 through insulating laminate structure 130 and multiple channel columns 110, as Fig. 5,
Shown in Fig. 6.
In this step, it can use etching technics patterning insulating laminate structure 130, form a plurality of gap, and stitching
Gap fills the material for being used to form the second isolation structure 104, and the insulating laminate structure 130 of 110 two sides of channel column is respectively by second
Isolation structure 104 is divided into two parts, wherein the material of the second isolation structure 104 includes oxide.
Preferably, the second isolation structure 104 in a second direction divides equally channel column 110, and first direction is in second direction
90 degree.
Further, using grid line gap 103 as etchant channel, using isotropic etching by the first isolation structure
The second interlayer insulating film 132 removal of 102 sides is to form cavity 105, and as shown in Figure 8, Figure 9, Fig. 9 is in Fig. 8 along line A-A
Sectional view.
In this step, isotropic etching can be using the wet etching or gas phase etching of selectivity.In wet etching
It is middle to use etching solution as etchant, wherein in the etch solution by semiconductor structure submergence.Erosion is used in gas phase etching
Gas is carved as etchant, wherein semiconductor structure is exposed in etching gas.First in insulating laminate structure 130
In the case of interlayer insulating film 131 and the second interlayer insulating film 132 are made of silica and silicon nitride respectively, in wet etching
C can be used in gas phase etching using phosphoric acid solution as etchant4F8、C4F6、CH2F2And O2One of or it is more
Kind.In an etching step, etchant is full of grid line gap 103.The second interlayer insulating film 132 in insulating laminate structure 130
End is exposed in the opening in grid line gap 103, and therefore, the second interlayer insulating film 132 touches etchant.Etchant is by grid line
The opening in gap 103 is gradually to the second interlayer insulating film of etched inside 132 of insulating laminate structure 130.Due to the choosing of etchant
Selecting property, the etching remove the second interlayer insulating film 132 relative to the first interlayer insulating film 131 in insulating laminate structure 130.And
Due to the blocking of the first isolation structure 102, etchant will not carry out the second interlayer insulating film 132 of 110 other side of channel column
Etching.
Further, using grid line gap 103 as etchant channel, using isotropic etching by the first isolation structure
The first interlayer insulating film 131 removal of 102 other sides is to form cavity 105, as shown in Fig. 8, Figure 10, wherein Figure 10 Fig. 8
The middle sectional view along line B-B.
In this step, the method for removing the first interlayer insulating film 131 is similar with the second interlayer insulating film 132 of removal, this
Place repeats no more.
Further, using grid line gap 103 as deposit channel, using atomic layer deposition (ALD), in grid line gap
103 and cavity 105 in filling metal layer formed grid conductor, then carry out etch-back (etch back), re-form grid line seam
Gap 103, as shown in Figure 11 to 14, wherein Figure 12 is the sectional view in Figure 11 along line A-A, and Figure 13 is in Figure 11 along line B-B
Sectional view, Figure 14 are the sectional view in Figure 11 along line C-C.
In this embodiment, metal layer is for example made of tungsten.First isolation structure, 102 side grid conductor (121a,
122a, 123a) the first interlayer insulating film 131 in insulating laminate structure 130 has been replaced so as to form the first rhythmic structure of the fence
120a.The grid conductor (121b, 122b, 123b) of first isolation structure, 102 other side has been replaced in insulating laminate structure 130
Second interlayer insulating film 132 is so as to form the second rhythmic structure of the fence 120b.
Figure 15 a to 16c shows the effect analysis figure of 3D memory device according to an embodiment of the present invention.
As shown in Figure 15 a to Figure 15 c, wherein Figure 15 b is the channel of n-th layer and corresponding part in Figure 15 a rhythmic structure of the fence
Column along X/Y plane sectional view, Figure 15 c be in Figure 15 a rhythmic structure of the fence N+1 layers with the channel column of corresponding part along X/Y plane
Sectional view.
In ideal technology, to increase the storage unit of 3D memory device, it is necessary to increase the stacking of rhythmic structure of the fence
The number of plies, specifically, needing to increase the number of plies of grid conductor 121 ', to increase what channel column 110 ' was formed with grid conductor 121 '
Storage unit, and in order to realize the electric isolution between grid conductor 121 ', also simultaneously needs increased grid conductor 121 ' it
Between formed interlayer insulating film 130 ', therefore, the size of 3D memory device also will increase, and in practical applications, rhythmic structure of the fence is in Z
There is the space greater than 40% to be occupied on direction by interlayer insulating film 130 ', rhythmic structure of the fence is caused to waste in z-direction largely
Resource, for example, actually having 64 layers of grid line metal (grid conductor 121 ') and 64 for 64 layers of 3D memory device
Layer dielectric medium (interlayer insulating film 130 '), dielectric medium waste the space of 3D memory device nearly half in z-direction.
As shown in Figure 16 a to Figure 16 c, wherein Figure 16 b is the channel of n-th layer and corresponding part in Figure 16 a rhythmic structure of the fence
Column along X/Y plane sectional view, Figure 16 c be in Figure 16 a rhythmic structure of the fence N+1 layers with the channel column of corresponding part along X/Y plane
Sectional view.
In an embodiment of the present invention, to the storage unit of increase 3D memory device, it is only necessary to by 110 side of channel column
Grid conductor 121a, be arranged in a staggered manner with the grid conductor 121b of 110 other side of channel column, realize grid in z-direction and lead
The staggered floor of body 121a and 121b, and storage unit is continued presence in z-direction in each layer, i.e., in rhythmic structure of the fence,
The part of channel column 110 corresponding to each layer including interlayer insulating film is fully utilized, with grid conductor 121a
Storage unit is formed with 121b, to increase at least 1 times of storage density in Z-direction.
In addition, running through the second isolation structure 103 of channel column 110 and rhythmic structure of the fence by being formed, respectively by channel column
The grid conductor 121a and 121b of the staggered floor of 110 two sides is divided into two, in each layer, the storage list of the every side of channel column 110
Member is two.
In conjunction with the improvement on tri- directions XYZ, the storage density of 3D memory device is at least promoted to original 4 times, and 3D
The size of memory device does not increase, and compared to ideal technology, has achieved the effect that the size for reducing 3D memory device.
In the above description, the technical details such as composition, the etching of each layer are not described in detail.But
It will be appreciated by those skilled in the art that can be by various technological means, come layer, the region etc. for forming required shape.In addition, being
Formation same structure, those skilled in the art can be devised by and process as described above not fully identical method.
In addition, although respectively describing each embodiment above, but it is not intended that the measure in each embodiment cannot be advantageous
Ground is used in combination.
The embodiment of the present invention is described above.But the purpose that these embodiments are merely to illustrate that, and
It is not intended to limit the scope of the invention.The scope of the present invention is limited by appended claims and its equivalent.This hair is not departed from
Bright range, those skilled in the art can make a variety of alternatives and modifications, these alternatives and modifications should all fall in of the invention
Within the scope of.
Claims (12)
1. a kind of 3D memory device, comprising:
Semiconductor substrate；
Rhythmic structure of the fence is located in the semiconductor substrate, including the grid conductor and interlayer insulating film being alternately stacked；And
Channel column runs through the rhythmic structure of the fence,
The 3D memory device further includes the second isolation structure through the channel column and the rhythmic structure of the fence,
Wherein, second isolation structure is in the plane parallel with the semiconductor substrate surface by the channel column and institute
State rhythmic structure of the fence separation.
2. 3D memory device according to claim 1 further includes through the channel column and the rhythmic structure of the fence
The rhythmic structure of the fence is divided into the first rhythmic structure of the fence and the second gate by the first isolation structure, first isolation structure
Laminated construction,
On the direction vertical with the semiconductor substrate surface, the grid conductor of first rhythmic structure of the fence and described second
The grid conductor of rhythmic structure of the fence is arranged in a staggered manner.
3. 3D memory device according to claim 2, wherein first isolation structure will be described along the first direction
Channel column is divided equally,
Second isolation structure divides equally the channel column along the second direction.
4. 3D memory device according to claim 3, wherein the angle of the first direction and the second direction is 90
Degree.
5. 3D memory device according to claim 2, wherein the material of first isolation structure includes silicon carbide.
6. 3D memory device according to claim 2, wherein the material of the interlayer insulating film of first rhythmic structure of the fence
Selected from one of oxide and nitride,
Another kind of the material of the interlayer insulating film of second rhythmic structure of the fence in oxide and nitride.
7. 3D memory device according to claim 2, wherein first isolation structure divides equally the channel column.
8. -7 any 3D memory device according to claim 1, wherein the multiple channel column is arranged in array, each column
The channel column Heterogeneous Permutation of the channel column and adjacent column.
9. 3D memory device according to claim 8, wherein channel column described in each column is by same first isolation structure
Separate.
10. -7 any 3D memory device according to claim 1, further includes grid line gap, run through the rhythmic structure of the fence,
The multiple channel column is between the grid line gap.
11. a kind of method for manufacturing 3D memory device, comprising:
Rhythmic structure of the fence is formed on a semiconductor substrate, including the grid conductor and interlayer insulating film being alternately stacked；And
Channel column is formed through the rhythmic structure of the fence,
The method also includes forming the second isolation structure through the channel column and the rhythmic structure of the fence,
Wherein, second isolation structure is in the plane parallel with the semiconductor substrate surface by the channel column and institute
State rhythmic structure of the fence separation.
12. according to the method for claim 11, further including forming the first isolation structure through the channel column, by the grid
Laminated construction is separated into the first rhythmic structure of the fence and the second rhythmic structure of the fence separates,
Wherein, on the direction vertical with the semiconductor substrate surface, the grid conductor of first rhythmic structure of the fence and institute
The grid conductor for stating the second rhythmic structure of the fence is arranged in a staggered manner.
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| CN110676259A (en) * | 2019-08-22 | 2020-01-10 | 长江存储科技有限责任公司 | Three-dimensional storage structure and manufacturing method thereof |
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| CN103066076A (en) * | 2011-10-24 | 2013-04-24 | 爱思开海力士有限公司 | 3-D nonvolatile memory device and method of manufacturing same, and memory system |
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