CN109216160A - 边缘粗糙度减小 - Google Patents

边缘粗糙度减小 Download PDF

Info

Publication number
CN109216160A
CN109216160A CN201810697196.2A CN201810697196A CN109216160A CN 109216160 A CN109216160 A CN 109216160A CN 201810697196 A CN201810697196 A CN 201810697196A CN 109216160 A CN109216160 A CN 109216160A
Authority
CN
China
Prior art keywords
mask
gas
tcp power
processing
pulsed bias
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201810697196.2A
Other languages
English (en)
Other versions
CN109216160B (zh
Inventor
金艳莎
谭忠魁
崔麟
符谦
马丁·沈
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lam Research Corp
Original Assignee
Lam Research Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lam Research Corp filed Critical Lam Research Corp
Publication of CN109216160A publication Critical patent/CN109216160A/zh
Application granted granted Critical
Publication of CN109216160B publication Critical patent/CN109216160B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002Preparing wafers
    • H01L21/02005Preparing bulk and homogeneous wafers
    • H01L21/02008Multistep processes
    • H01L21/0201Specific process step
    • H01L21/02021Edge treatment, chamfering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002Preparing wafers
    • H01L21/02005Preparing bulk and homogeneous wafers
    • H01L21/02008Multistep processes
    • H01L21/0201Specific process step
    • H01L21/02019Chemical etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002Preparing wafers
    • H01L21/02005Preparing bulk and homogeneous wafers
    • H01L21/02035Shaping
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02312Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02312Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
    • H01L21/02315Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02631Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338Process specially adapted to improve the resolution of the mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

本发明涉及边缘粗糙度减小。提供了一种用于处理在掩模下方具有蚀刻层的层堆的方法。所述掩模通过以下方式处理:使处理气体流动,其中所述处理气体包括溅射气体和修整气体;提供脉冲TCP功率以从所述处理气体产生等离子体;以及提供脉冲偏置,其中所述脉冲偏置与所述脉冲TCP功率具有相同的周期,其中所述脉冲TCP功率和脉冲偏置提供具有高于溅射阈值的第一偏置和第一TCP功率的第一状态,从而导致来自所述溅射气体的物质溅射所述掩模并且再沉积来自所述掩模的材料,以及提供具有低于所述溅射阈值的第二偏置和第二TCP功率的第二状态,其中所述第二TCP功率大于所述第一TCP功率,其导致来自所述修整气体的物质化学修整所述掩膜。

Description

边缘粗糙度减小
技术领域
本公开涉及半导体器件的形成。更具体地说,本公开涉及通过蚀刻特征来形成半导体器件。
背景技术
在半导体晶片处理期间,特征可被蚀刻到各种层中。蚀刻特征的线边缘粗糙度或线宽粗糙度的增大可能增加器件泄漏。
发明内容
为了实现前述目的,并且根据本公开内容的目的,提供了一种用于在等离子体处理室中处理在掩模下方具有蚀刻层的层堆的方法。所述掩模通过以下方式处理:使处理气体连续流入所述等离子体处理室,其中所述处理气体包括溅射气体和修整气体;提供脉冲TCP功率以从所述处理气体产生等离子体;以及提供脉冲偏置,其中所述脉冲偏置与所述脉冲TCP功率具有相同的周期,其中所述脉冲TCP功率和脉冲偏置提供具有第一TCP功率和高于溅射阈值的第一偏置的第一状态,从而导致来自所述溅射气体的物质溅射所述掩模并且再沉积来自所述掩模的材料,以及提供具有第二TCP功率和低于所述溅射阈值的第二偏置的第二状态,其中所述第二TCP功率大于所述第一TCP功率,其导致来自所述修整气体的物质化学修整所述掩膜。
在另一实现方式中,提供了一种用于在等离子体处理室中处理在掩模下方具有蚀刻层的层堆的方法。所述掩模通过以下方式处理:使处理气体连续流入所述等离子体处理室,其中所述处理气体包括溅射气体和修整气体;提供TCP功率以从所述处理气体产生等离子体;以及提供脉冲偏置,其中所述脉冲偏置提供具有高于溅射阈值的所述第一偏置的第一状态,从而导致来自所述溅射气体的物质溅射所述掩模以及再沉积来自所述掩模的材料,并且提供具有低于所述溅射阈值的第二偏置的第二状态,从而导致来自所述修整气体的物质化学修整所述掩膜。在处理所述掩模之后蚀刻所述掩模下方的所述蚀刻层。
具体而言,本发明的一些方面可以阐述如下:
1.一种用于在等离子体处理室中处理在掩模下方具有蚀刻层的层堆的方法,其包括:
处理所述掩模,其包括:
使处理气体连续流入所述等离子体处理室,其中所述处理气体包括溅射气体和修整气体;
提供脉冲TCP功率以从所述处理气体产生等离子体;以及
提供脉冲偏置,其中所述脉冲偏置与所述脉冲TCP功率具有相同的周期,其中所述脉冲TCP功率和脉冲偏置提供具有高于溅射阈值的第一偏置和第一TCP功率的第一状态,从而导致来自所述溅射气体的物质溅射所述掩模并且再沉积来自所述掩模的材料,以及提供具有低于所述溅射阈值的第二偏置和第二TCP功率的第二状态,其中所述第二TCP功率大于所述第一TCP功率,其导致来自所述修整气体的物质化学修整所述掩膜。
2.根据条款1所述的方法,其中当提供所述脉冲TCP功率和所述脉冲偏置时,所述使所述处理气体连续流入提供恒定流量的所述处理气体。
3.根据条款1所述的方法,其中所述脉冲TCP功率和脉冲偏置是同步且异相的。
4.根据条款1所述的方法,其中所述掩模包括基于氧化硅的材料,所述溅射气体包括O2,并且所述修整气体包括含卤素的气体。
5.根据条款1所述的方法,其中所述处理气体还包括钝化气体。
6.根据条款5所述的方法,其中所述钝化气体包含COS或SO2中的至少一种。
7.根据条款1所述的方法,其中所述脉冲TCP功率和脉冲偏置具有介于1Hz和10kHz之间且包括1Hz和10kHz的频率。
8.根据条款1所述的方法,其还包括在处理所述掩模之后蚀刻所述掩模下方的所述蚀刻层。
9.根据条款8所述的方法,其还包括去除所述掩模。
10.根据条款1所述的方法,其中所述掩模形成棱形图案,并且其中所述处理所述掩模使所述棱形图案转换为圆形图案。
11.一种用于在等离子体处理室中处理在掩模下方具有蚀刻层的层堆的方法,其包括:
处理所述掩模,其包括:
使处理气体连续流入所述等离子体处理室,其中所述处理气体包括溅射气体和修整气体;
提供TCP功率以将所述处理气体形成为等离子体;以及
提供脉冲偏置,其中所述脉冲偏置提供具有高于溅射阈值的所述第一偏置的第一状态,从而导致来自所述溅射气体的物质溅射所述掩模以及再沉积来自所述掩模的材料,并且提供具有低于所述溅射阈值的第二偏置的第二状态,从而导致来自所述修整气体的物质化学修整所述掩膜,并且
在处理所述掩模之后蚀刻所述掩模下方的所述蚀刻层。
12.根据条款11所述的方法,其中,当提供所述脉冲偏置时,所述使所述处理气体连续流入提供恒定流量的所述处理气体。
13.根据条款11所述的方法,其还包括去除所述掩模。
14.根据条款11所述的方法,其中所述掩模形成棱形图案,并且其中所述处理所述掩模使所述棱形图案转换为圆形图案。
这些和其他特征将结合下面的附图在下文的详细描述中更详细地描述。
附图说明
本发明在附图中的图形是通过举例的方式而不是通过限制的方式示出,其中相同的附图标记表示类似的元件,并且其中:
图1是可以在一实施方式中使用的工艺的高级流程图。
图2是处理图案化掩模的步骤的更详细的流程图。
图3A-D是根据一实施方式处理的层堆(stack)的示意性横截面图。
图4A-B是根据一实施方式处理的层堆的线的顶视图。
图5是可用于实施本实施方式的等离子体处理室的示意图。
图6示出了适用于实现在实施方式中使用的控制器的计算机系统。
具体实施方式
现在将参照如附图中所示的其几个优选的实施方式详细描述本公开。在下面的描述中,阐述了许多具体细节以便彻底理解本公开。然而,对本领域的技术人员将显而易见的是,在没有部分或所有这些具体细节的情况下可以实现本公开。在其他情况下,没有详细描述众所周知的工艺步骤和/或结构从而避免不必要地使本公开难以理解。
为了便于理解,图1是实施方式的高级流程图。在蚀刻层上具有图案化掩模的层堆放置在等离子体室中的衬底支撑件上(步骤104)。处理图案化的掩模(步骤108)。蚀刻所述蚀刻层(步骤112)。掩模被移除(步骤116)。将层堆从等离子体室移除(步骤120)。图2是处理图案化掩模的步骤的更详细流程图(步骤108)。处理图案化掩模(步骤108)包括多个循环,其中每个循环包括溅射阶段(步骤204)和修整阶段(步骤208)。
实施例
在本发明的实施方式的一个实施例中,层堆放置在等离子体室中的衬底支撑件上(步骤104)。图3A是层堆300的横截面示意图,其中衬底304布置在蚀刻层308下方,而蚀刻层308布置在图案化掩模312下方。在此实施例中,图案化掩模312为氧化硅掩模且蚀刻层308为导电钨层。在各种实施方式中,一个或多个层可以位于衬底304和蚀刻层308之间,或位于蚀刻层308和图案化掩模312之间。图4A是具有蚀刻层308和图案化掩模312的层堆300的俯视示意图。在此实施方式中,图案化掩模形成菱形图案,如图所示。菱形图案由两组以非垂直角度相交的平行线图案提供。用具有圆形图案的掩模蚀刻所述蚀刻层308将是更加合乎期望的。
图5示意性示出了可用于根据本发明的一个实施方式执行层堆300的等离子体处理系统500的示例。该等离子体处理系统500包括等离子体反应器502,在等离子体反应器502内具有等离子体处理室504。通过匹配网络508调谐的等离子体电源506提供功率至靠近功率窗512定位的TCP线圈510,从而通过提供感应耦合功率在该等离子体处理室504中产生等离子体514。该TCP线圈(上电源)510可以被配置来在等离子体处理室504中产生均匀的扩散分布。例如,该TCP线圈510可以被配置来在等离子体514中产生环形功率分布。提供功率窗512以将等离子体处理室504与该TCP线圈510隔离,同时允许能量从TCP线圈510传递到等离子体处理室504。通过匹配网络518调谐的晶片偏压电源516提供功率至电极520以在被支撑在电极520上的衬底304上设置偏置电压。控制器524为等离子体电源506和晶片偏压电源516设定值。
该等离子体电源506和该晶片偏压电源516可被配置以在特定的射频下进行操作,该射频诸如例如13.56MHz、27MHz、2MHz、400kHz或它们的组合。该等离子体电源506和晶片偏压电源516可以是适当地设置以提供一系列的功率,以实现所期望的工艺性能。例如,在本发明的一个实施方式中,该等离子体电源506可供应的功率的范围为50至5000瓦特,以及该晶片偏压电源516可供应的偏置电压的范围为20至2000伏。此外,该TCP线圈510和/或电极520可以包括两个或更多个子线圈或子电极,其可以通过单个电源供电或通过多个电源供电。
如图5所示,该等离子体处理系统500进一步包括气体源/气体供给机构530。该气体源/气体供给机构530提供气体至气体进口532。处理气体和副产物经由压强控制阀542和泵544从等离子体处理室504移除,该压强控制阀542和泵544也可以起到维持等离子体处理室504内的特定压强的作用。该气体源/气体供给机构530和泵544由控制器524控制。LamResearch公司(Fremont,CA)的Kiyo系统可用于实践实施方式。
图6是显示计算机系统600的高级框图,其适合用于实现在本发明的实施方式中使用的控制器524。该计算机系统可以具有许多物理形式,范围从集成电路、印刷电路板和小型手持设备到巨型超级计算机。计算机系统600包括一个或多个处理器602,并且还可以包括电子显示设备604(用于显示图形、文本和其他数据)、主存储器606(例如,随机存取存储器(RAM))、存储设备608(例如,硬盘驱动器)、可移动存储设备610(例如,光盘驱动器)、用户接口设备612(例如,键盘、触摸屏、小键盘、鼠标或其他指针设备等)以及通信接口614(例如,无线网络接口)。通信接口614允许软件和数据经由链路在计算机系统600和外部设备之间传输。该系统还可以包括上述设备/模块所连接到的通信基础设施616(例如,通信总线、交叉杆或网络)。
通过通信接口614传输的信息可以是信号(诸如电子、电磁、光学或能够经由携带信号的通信链路被通信接口614接收的其他信号)的形式,并且可以使用电线或电缆、光纤、电话线、手机链路、射频链路和/或其他通信渠道来实现。可以设想,具有这样的通信接口,在执行上述方法步骤的过程中一个或多个处理器602可以从网络接收信息,或可以输出信息到网络。此外,本发明的方法实施方式可以在处理器单独执行,或者可以通过网络(如Internet)结合共享该处理的部分的远程处理器执行。
术语“非瞬时计算机可读介质”一般用来指例如主存储器、辅助存储器、可移动存储以及存储设备(如硬盘、闪速存储器、磁盘驱动存储器、CD-ROM和其他形式的永久性存储器)等介质,并且不应被解释为涵盖瞬态标的物,例如载波或信号。计算机代码的实施例包括机器代码(诸如由编译器产生的)和包含由计算机使用解释器执行的更高级代码的文件。计算机可读介质还可以是通过体现在载波中并且表示可由处理器执行的指令序列的计算机数据信号传输的计算机代码。
处理图案化的掩模(步骤108)。图2是处理图案化掩模的步骤的更详细流程图(步骤108)。处理图案化掩模(步骤108)包括多个循环,其中每个循环包括溅射阶段(步骤204)和修整阶段(步骤208)。对于溅射阶段(步骤204)和修整阶段(步骤208)两者,连续提供处理气体。处理气体包括溅射气体和修整气体。在这个实施例中,处理气体是作为溅射气体的1200sccm O2和作为修整气体的60sccm CF4。在溅射阶段(步骤204)期间,在13.56MHz下提供200瓦的TCP功率以及提供幅值为至少200伏的偏置。偏置高于形成图案化掩模的材料的溅射阈值。结果,在溅射阶段期间,一些掩模被溅射掉并重新沉积在掩模的另一部分上。在修整阶段期间(步骤208),在13.56MHz下提供1500瓦特的TCP功率,并提供小于100伏特的偏置。该偏置低于形成图案化掩模的材料的溅射阈值。因此,在修整阶段期间,材料不会被溅射并重新沉积在掩模上。相反,来自修整气体的等离子体成分与掩模化学相互作用,导致掩模被化学修整。
图3B是在处理图案化掩模108之后的层堆300的横截面示意图。图4B是在处理图案化掩模108之后的线的顶部示意图。在溅射期间,掩模312的侧壁中的一些被溅射并且重新沉积在掩模312的其他部分上。溅射和再沉积的组合与化学修整交替导致菱形图案掩模312形成圆形图案掩模,如图所示。另外,已经发现线边缘粗糙度和线宽粗糙度降低。
蚀刻所述蚀刻层(步骤112)。用于蚀刻所述蚀刻层的示例配方提供蚀刻气体,其包括在3mTorr的压强下,20sccm Cl2、13sccm NF3、15sccm O2和125sccm N2。通过提供400瓦的TCP功率从蚀刻气体形成等离子体。提供80伏的偏置电压。图3C是蚀刻层304已经被蚀刻之后的层堆300的侧面示意图。将掩模去除(步骤116)。图3D是在去除掩模之后层堆300的侧面示意图。将层堆从室去除(步骤120)。由于在该实施方式中,蚀刻层是导电层,通过蚀刻掉除了由圆形掩模图案覆盖的区域之外的导电层,可以形成导电焊盘。
该实施方式允许菱形掩模图案形成为圆形掩模图案。另外,该实施方式减小了线边缘粗糙度和线宽粗糙度。线边缘粗糙度和线宽粗糙度的减小是通过改变图案化掩模形状的相同机制来实现的。溅射选择性地去除从图案化掩模伸出的粗糙部分(或在图案化掩模内的凸起),如菱形的角部。该再沉积选择性地增加了图案化掩模的更多凹陷部分(或凹口),例如棱形形状的边的中间。所述修整防止关键尺寸(CD)的增长。通过选择性地去除延伸出的部分并选择性地沉积在凹陷部分上并且修整以防止CD生长,掩模具有减小的线边缘粗糙度和/或线宽粗糙度。这提供了具有减小的线边缘粗糙度和/或线宽粗糙度的蚀刻特征。
多种实施方式在处理掩模期间提供恒定气流,同时等离子体和偏置功率被施以脉冲。通过仅对偏置功率和等离子体功率施以脉冲而不对气流施以脉冲,该施以脉冲可以在较高的频率下进行。优选地,偏置功率和等离子体功率以介于1Hz和10kHz之间(包括1和10kHz)的频率施以脉冲。更优选地,偏置功率和等离子体功率以介于10Hz和1kHz之间(包括10Hz和1kHz)的频率施以脉冲。最优选地,偏置功率和等离子体功率以介于100Hz和500Hz之间(包括100Hz和500Hz)的频率施以脉冲。在一些实施方式中,只有偏置功率被施以脉冲。优选地,偏置功率和等离子体功率都以相同周期和异相同步施以脉冲,使得当等离子体功率最低时偏置功率最高,并且当偏置功率最低时等离子体功率最高。对于氧化硅掩模,溅射阈值为120伏。在溅射阶段期间,偏置功率的幅值优选为至少200伏。更优选地,偏置功率的幅值在200到1500伏之间。在修整期间,偏置的幅值优选小于100伏。更优选地,在修整期间,不施加偏置。
在多种实施方式中,修整气体可以是含卤素的气体。优选地,含卤素的气体含有氟。优选地,处理气体还包含钝化气体。优选地,钝化气体是COS或SO2中的至少一种。在多种实施方式中,溅射气体可以包含Ar或O2。O2相对于SiO2掩模是惰性的并且可能能够去除任何剩余的光致抗蚀剂或其他有机残留物。掩模的溅射和再沉积也可以称为掩模的重新分布。
在其他实施方式中,蚀刻层可以是诸如Ti、TiN、W或WN之类的导电材料。在其他实施方式中,中间层可以放置在图案化掩模和蚀刻层之间。可以使用分开的蚀刻工艺来蚀刻中间层,或者可以用单个蚀刻工艺来蚀刻多个层。这样的中间层可以是导电层或介电层或其他类型的层。这些层可以是抗反射涂层。
虽然本发明已根据几个优选的实施方式进行了描述,但是存在落入本发明的范围之内的变更、修改、置换和多种替代等同方案。还应当注意,有许多实现本发明的方法和装置的替代方式。因此,下面所附的权利要求旨在被解释为包括落入本发明的真正的精神和范围之内的所有这些变更、修改、置换和多种替代等同方案。

Claims (10)

1.一种用于在等离子体处理室中处理在掩模下方具有蚀刻层的层堆的方法,其包括:
处理所述掩模,其包括:
使处理气体连续流入所述等离子体处理室,其中所述处理气体包括溅射气体和修整气体;
提供脉冲TCP功率以从所述处理气体产生等离子体;以及
提供脉冲偏置,其中所述脉冲偏置与所述脉冲TCP功率具有相同的周期,其中所述脉冲TCP功率和脉冲偏置提供具有高于溅射阈值的第一偏置和第一TCP功率的第一状态,从而导致来自所述溅射气体的物质溅射所述掩模并且再沉积来自所述掩模的材料,以及提供具有低于所述溅射阈值的第二偏置和第二TCP功率的第二状态,其中所述第二TCP功率大于所述第一TCP功率,其导致来自所述修整气体的物质化学修整所述掩膜。
2.根据权利要求1所述的方法,其中当提供所述脉冲TCP功率和所述脉冲偏置时,所述使所述处理气体连续流入提供恒定流量的所述处理气体。
3.根据权利要求1所述的方法,其中所述脉冲TCP功率和脉冲偏置是同步且异相的。
4.根据权利要求1所述的方法,其中所述掩模包括基于氧化硅的材料,所述溅射气体包括O2,并且所述修整气体包括含卤素的气体。
5.根据权利要求1所述的方法,其中所述处理气体还包括钝化气体。
6.根据权利要求5所述的方法,其中所述钝化气体包含COS或SO2中的至少一种。
7.根据权利要求1所述的方法,其中所述脉冲TCP功率和脉冲偏置具有介于1Hz和10kHz之间且包括1Hz和10kHz的频率。
8.根据权利要求1所述的方法,其还包括在处理所述掩模之后蚀刻所述掩模下方的所述蚀刻层。
9.根据权利要求8所述的方法,其还包括去除所述掩模。
10.一种用于在等离子体处理室中处理在掩模下方具有蚀刻层的层堆的方法,其包括:
处理所述掩模,其包括:
使处理气体连续流入所述等离子体处理室,其中所述处理气体包括溅射气体和修整气体;
提供TCP功率以将所述处理气体形成为等离子体;以及
提供脉冲偏置,其中所述脉冲偏置提供具有高于溅射阈值的所述第一偏置的第一状态,从而导致来自所述溅射气体的物质溅射所述掩模以及再沉积来自所述掩模的材料,并且提供具有低于所述溅射阈值的第二偏置的第二状态,从而导致来自所述修整气体的物质化学修整所述掩膜,并且
在处理所述掩模之后蚀刻所述掩模下方的所述蚀刻层。
CN201810697196.2A 2017-06-29 2018-06-29 边缘粗糙度减小 Active CN109216160B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/637,828 2017-06-29
US15/637,828 US10020183B1 (en) 2017-06-29 2017-06-29 Edge roughness reduction

Publications (2)

Publication Number Publication Date
CN109216160A true CN109216160A (zh) 2019-01-15
CN109216160B CN109216160B (zh) 2024-01-30

Family

ID=62749615

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810697196.2A Active CN109216160B (zh) 2017-06-29 2018-06-29 边缘粗糙度减小

Country Status (3)

Country Link
US (1) US10020183B1 (zh)
KR (1) KR102653067B1 (zh)
CN (1) CN109216160B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111029278B (zh) * 2019-12-10 2021-06-29 长江存储科技有限责任公司 一种晶圆片的加工方法和系统

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060169582A1 (en) * 2005-02-03 2006-08-03 Applied Materials, Inc. Physical vapor deposition plasma reactor with RF source power applied to the target and having a magnetron
US20080182419A1 (en) * 2007-01-16 2008-07-31 Naoki Yasui Plasma processing method
US20130059448A1 (en) * 2011-09-07 2013-03-07 Lam Research Corporation Pulsed Plasma Chamber in Dual Chamber Configuration
US20130213935A1 (en) * 2009-08-07 2013-08-22 Applied Materials, Inc. Synchronized radio frequency pulsing for plasma etching
US20140272728A1 (en) * 2013-03-14 2014-09-18 Varian Semiconductor Equipment Associates, Inc. Techniques for processing photoresist features using ions
US20150380272A1 (en) * 2014-06-30 2015-12-31 Lam Research Corporation Liner and barrier applications for subtractive metal integration

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008021609A1 (en) * 2006-08-07 2008-02-21 Tokyo Electron Limited Method of treating a mask layer prior to performing an etching process
US7682986B2 (en) * 2007-02-05 2010-03-23 Lam Research Corporation Ultra-high aspect ratio dielectric etch
US7838426B2 (en) * 2007-08-20 2010-11-23 Lam Research Corporation Mask trimming
US7785484B2 (en) * 2007-08-20 2010-08-31 Lam Research Corporation Mask trimming with ARL etch
US20120223048A1 (en) * 2009-08-26 2012-09-06 Veeco Process Equipment Inc. System for Fabricating a Pattern on Magnetic Recording Media
US8802571B2 (en) * 2011-07-28 2014-08-12 Lam Research Corporation Method of hard mask CD control by Ar sputtering
JP6243722B2 (ja) * 2013-12-10 2017-12-06 東京エレクトロン株式会社 エッチング処理方法
WO2017151622A1 (en) * 2016-03-04 2017-09-08 Tokyo Electron Limited Trim method for patterning during various stages of an integration scheme

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060169582A1 (en) * 2005-02-03 2006-08-03 Applied Materials, Inc. Physical vapor deposition plasma reactor with RF source power applied to the target and having a magnetron
US20080182419A1 (en) * 2007-01-16 2008-07-31 Naoki Yasui Plasma processing method
US20130213935A1 (en) * 2009-08-07 2013-08-22 Applied Materials, Inc. Synchronized radio frequency pulsing for plasma etching
US20130059448A1 (en) * 2011-09-07 2013-03-07 Lam Research Corporation Pulsed Plasma Chamber in Dual Chamber Configuration
US20140272728A1 (en) * 2013-03-14 2014-09-18 Varian Semiconductor Equipment Associates, Inc. Techniques for processing photoresist features using ions
US20150380272A1 (en) * 2014-06-30 2015-12-31 Lam Research Corporation Liner and barrier applications for subtractive metal integration

Also Published As

Publication number Publication date
KR102653067B1 (ko) 2024-03-29
US10020183B1 (en) 2018-07-10
KR20190002327A (ko) 2019-01-08
CN109216160B (zh) 2024-01-30

Similar Documents

Publication Publication Date Title
KR20190049482A (ko) 스택 내에 피처들을 에칭하기 위한 방법
CN101971291B (zh) 双掩模自对准双图案化技术(SaDPT)工艺
CN101779277B (zh) 用于蚀刻设在反射层下方的介电层的方法和设备
CN101779276B (zh) 掩模修整
CN101292197A (zh) 具有减小的线条边缘粗糙度的蚀刻特征
CN101278381A (zh) 垂直形貌修整
CN101730930A (zh) 在蚀刻高纵横比结构中降低微负载的方法
TW201801184A (zh) 蝕刻介電層中之特徵部的方法
KR20140023219A (ko) 혼합된 모드 펄싱을 갖는 식각
TW201735158A (zh) 混合式階梯蝕刻
TW201436026A (zh) 鎢蝕刻之方法
CN101971301A (zh) 利用稀有气体等离子的线宽粗糙度改进
KR102070459B1 (ko) 평활 측벽의 급속 교번 에칭 프로세스를 위한 제어된 가스 혼합
TW201442108A (zh) 在原處之金屬殘餘物清潔
CN109216160A (zh) 边缘粗糙度减小
TW201707087A (zh) 梯階結構之形成方法
KR102139380B1 (ko) 제어된 위글링에 의한 에칭을 위한 방법
TW201906005A (zh) 多孔低介電常數介電蝕刻
KR102595435B1 (ko) 패턴 붕괴를 방지하기 위한 에칭 후 처리
KR102148036B1 (ko) 비아 제공 방법
TW201717260A (zh) 陰影修整線邊緣粗糙度減低
CN109997212B (zh) 在有机层蚀刻中生成竖直轮廓的方法
KR102626483B1 (ko) 반도체 프로세싱을 위한 실리콘-기반 증착
TWI768026B (zh) 用於半導體處理之矽基沉積
CN107785253B (zh) 利用侧边溅射的线边缘粗糙表面改进

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant