CN109103169B - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN109103169B
CN109103169B CN201810632849.9A CN201810632849A CN109103169B CN 109103169 B CN109103169 B CN 109103169B CN 201810632849 A CN201810632849 A CN 201810632849A CN 109103169 B CN109103169 B CN 109103169B
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cnts
conductive pattern
pattern
substrate
insulating interlayer
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CN109103169A (zh
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洪义官
文光辰
李来寅
李镐珍
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H10K30/82—Transparent electrodes, e.g. indium tin oxide [ITO] electrodes
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Abstract

一种半导体器件包括：位于第一衬底上的第一绝缘夹层的上部的第一导电图案、垂直地延伸的多个第一导电纳米管(CNT)、位于第二衬底下方的第二绝缘夹层的下部的第二导电图案、以及垂直地延伸的多个第二CNT。第二绝缘夹层的下表面接触第一绝缘夹层的上表面。多个第一CNT中的每一个的侧壁的至少一部分被第一导电图案覆盖，并且多个第二CNT中的每一个的侧壁的至少一部分被第二导电图案覆盖。第一导电图案和第二导电图案垂直地面向彼此，并且多个第一CNT中的至少一个与多个第二CNT中的至少一个彼此接触。

Description

半导体器件
相关申请的交叉引用
本申请要求于2017年6月20日向韩国知识产权局(KIPO)提交的韩国专利申请NO.10-2017-0077788的优先权，其全部内容通过引用的方式并入此文。
技术领域
本文公开的示例性实施例涉及半导体器件。更具体地，本文公开的示例性实施例涉及包括多个依次堆叠的衬底的半导体器件
背景技术
为了实现半导体器件的高度集成化，可以在垂直方向上将芯片、封装或衬底堆叠起来。因此，可以采用叠层芯片(COC)结构或叠层封装(POP)结构。当具有其中包含导电图案的绝缘夹层的衬底彼此接合以形成堆叠结构时，导电图案彼此之间需要实现良好的粘附，以使半导体器件可以具备较高的可靠性。
发明内容
示例性实施例提供了一种高可靠性半导体器件。
根据本发明构思的示例性实施例，提供了一种半导体器件。该半导体器件可以包括第一导电图案、多个第一碳纳米管(CNT)、第二导电图案以及多个第二CNT。第一导电图案可以被包含在第一衬底上的第一绝缘夹层的上部。多个第一CNT可以相对于第一衬底的上表面在垂直方向上延伸，并且多个第一CNT中的每一个的侧壁的至少一部分可以被第一导电图案覆盖。第二导电图案可以被包含在第二衬底下方的第二绝缘夹层的下部，并且第二绝缘夹层的下表面可以接触第一绝缘夹层的上表面。多个第二CNT可以在垂直方向上延伸，并且多个第二CNT中的每一个的侧壁的至少一部分可以被第二导电图案覆盖。第一导电图案和第二导电图案可以在垂直方向上彼此面对，并且多个第一CNT中的至少一个和多个第二CNT中的至少一个可以彼此接触。
根据本发明构思的示例性实施例，提供了一种半导体器件。该半导体器件可以包括第一导电图案、多个第一碳纳米管(CNT)、第二导电图案以及多个第二CNT。第一导电图案可以被包含在第一衬底上的第一绝缘夹层的上部。多个第一CNT可以形成在第一导电图案的上表面上的第一凹陷上，并且多个第一CNT中的每一个可以相对于第一衬底的上表面在垂直方向上延伸。第二导电图案可以被包含在第二衬底下方的第二绝缘夹层的下部，并且第二绝缘夹层的下表面可以接触第一绝缘夹层的上表面。多个第二CNT可以形成在第二导电图案的下表面下方的第二凹陷下方，并且多个第二CNT中的每一个可以在垂直方向上延伸。第一导电图案和第二导电图案可以在垂直方向上彼此面对，并且多个第一CNT中的至少一个和多个第二CNT中的至少一个可以彼此接触。
根据本发明构思的示例性实施例，提供了一种半导体器件。该半导体器件可以包括第一导电图案、多个第一碳纳米管(CNT)、第二导电图案以及多个第二CNT。多个第一CNT可以在垂直方向上延伸穿过第一导电图案，并且多个第一CNT中的每一个可以从第一导电图案的上表面突出。多个第二CNT可以在垂直方向上延伸穿过第二导电图案，并且多个第二CNT中的每一个可以从第二导电图案的下表面突出。多个第一CNT中的至少一个的上部和多个第二CNT中的至少一个的下部可以彼此接触。
在根据本发明构思的示例性实施例的制造半导体器件的方法中，当绝缘夹层以及相应衬底上的绝缘夹层所包含的导电图案彼此接合时，导电图案之间的粘合性可以因为导电图案中的CNT而得到增强，它们之间的接触电阻可以减小并且可以提高它们之间的电连接的可靠性。
附图说明
结合附图，根据下面的详细描述将更清楚地理解本发明构思的示例性实施例。图1至图26表示如本文所述的非限制性示例性实施例。
图1至图7是示出了根据本发明构思的示例性实施例的制造半导体器件的方法的各阶段的截面图；
图8至图9是示出了根据本发明构思的示例性实施例的制造半导体器件的方法的各阶段的截面图；
图10至图13是示出了根据本发明构思的示例性实施例的制造半导体器件的方法的各阶段的截面图；
图14至图16是示出了根据本发明构思的示例性实施例的制造半导体器件的方法的各阶段的截面图；
图17至图18是示出了根据本发明构思的示例性实施例的制造半导体器件的方法的各阶段的截面图；
图19至图22是示出了根据本发明构思的示例性实施例的制造半导体器件的方法的各阶段的截面图；
图23至图25是示出了根据本发明构思的示例性实施例的制造半导体器件的方法的各阶段的截面图；以及
图26是示出了根据本发明构思的示例性实施例的半导体器件的截面图。
具体实施方式
图1至图7是示出了根据本发明构思的示例性实施例的制造半导体器件的方法的各阶段的截面图。
参考图1，第一绝缘夹层110可以形成在第一衬底100上，可以将第一绝缘夹层110的上部去除以形成第一沟槽120，并且第一阻挡层130可以形成在第一沟槽120的内壁和第一绝缘夹层110的上表面上。
衬底100可以包括半导体材料(如硅、锗、硅锗等)或者III-V半导体化合物(如GaP、GaAs、GaSb等)。在示例性实施例中，衬底100可以是绝缘体上硅(SOI)衬底或者绝缘体上锗(GOI)衬底。
第一绝缘夹层110可以包括氧化硅或低k介电材料。
第一阻挡层130可以包括金属氮化物(如氮化钛、氮化钽等)和/或金属(如钛、钽等)。
参考图2，可以将第一阻挡层130部分地去除以在第一沟槽120的内壁上形成第一阻挡图案135，并且第一碳纳米管(CNT)结构140可以形成在第一阻挡图案135的表面上。
在示例性实施例中，可以通过化学机械抛光(CMP)工艺和/或回蚀工艺来去除第一绝缘夹层110的顶表面上的第一阻挡层130的一部分，从而在第一沟槽120的内壁上形成第一阻挡图案135。替代地，可以形成覆盖第一沟槽120的光刻胶图案(未示出)，并且可以将光刻胶图案用作蚀刻掩模来对第一阻挡层130进行图案化，从而在第一沟槽120的内壁上形成第一阻挡图案135。
在示例性实施例中，第一CNT 140可以通过化学气相沉积(CVD)工艺形成，并且可以选择性地仅形成在第一阻挡图案135的表面上。可以采用碳和氢来执行CVD工艺，因此，第一CNT 140可以包括具有化学式CxHy的材料。
在示例性实施例中，第一CNT 140可以仅形成在第一沟槽120的底部上的第一阻挡图案135的表面上，并且可以相对于衬底100的上表面在垂直方向上延伸(例如，如图所示的水平定向)。第一CNT 140的顶表面可以与第一绝缘夹层110的顶表面基本上共面，不过，本发明构思可以不局限于此。在示例性实施例中，多个第一CNT 140可以形成在第一沟槽120中，并且多个第一CNT 140中的每一个可以具有导电性。
参考图3，可以在第一阻挡图案135、多个第一CNT 140和第一绝缘夹层110上形成籽晶层(未示出)，并且可以在籽晶层上形成第一导电层150以充分填充第一沟槽120的剩余部分。
第一导电层150可以包括金属(如铜、铝等)，并且可以通过电镀工艺或非电镀工艺形成。
参考图4A，可以使第一导电层150的上部平坦化，直到第一绝缘夹层110的顶表面被暴露以在第一沟槽120中形成第一导电图案155为止。
在示例性实施例中，平坦化工艺可以通过CMP工艺来执行，并且在执行CMP工艺时，可能会发生下陷(dishing)。因此，第一导电图案155的上表面的高度和/或第一阻挡图案135的顶表面的高度可以不等于第一绝缘夹层110的顶表面的高度，并且第一凹陷160可以形成在第一导电图案155和/或第一阻挡图案135上。
在平坦化工艺期间，可以保持多个第一CNT 140的顶表面的高度，这些高度可以基本上等于第一绝缘夹层110的顶表面的高度。因此，多个第一CNT 140中的每一个的大部分侧壁可以被第一导电图案155覆盖，然而，多个第一CNT 140中的每一个的上侧壁可以从第一导电图案155的上表面突出。
参考图4B和图4C，第一凹陷160的深度可以比图4A的深度更深。
在示例性实施例中，图4A和图4B中示出的第一凹陷160可以具有约至约的深度。
参考图5，可以再次在第二衬底200上执行基本上与参考图1至图4所示的工艺相同或相似的工艺。
因此，可以在第二衬底200上形成第二绝缘夹层210，可以去除第二绝缘夹层210的上部以形成第二沟槽(未示出)，并且可以在第二沟槽的内壁上形成第二阻挡图案235。多个第二CNT 240(例如，导电CNT)可以形成在第二沟槽的底部上的第二阻挡图案235的表面上，并且可以相对于第二衬底200的上表面在垂直方向上延伸。多个第二CNT 240中的每一个的顶表面可以与第二绝缘夹层210的顶表面基本上共面。
第二导电层可以被形成为充分填充第二沟槽的剩余部分，并且可以使第二导电层的上部平坦化，直到第二绝缘夹层210的顶表面被暴露以形成第二导电图案255为止。
在示例性实施例中，第二导电图案255的上表面的高度和/或第二阻挡图案235的顶表面的高度可以不等于第二绝缘夹层210的顶表面的高度，并且第二凹陷(未示出)可以形成在第二导电图案255和/或第二阻挡图案235上。可以保持多个第二CNT 240的顶表面的高度，这些高度可以基本上等于第二绝缘夹层210的顶表面的高度。因此，多个第二CNT 240中的每一个的大部分侧壁可以被第二导电图案255覆盖，然而，多个第二CNT 240中的每一个的上侧壁可以从第二导电图案255的上表面突出。
在形成第二导电图案255之后，可以将第二衬底200旋转180度，这样使得第二绝缘夹层210可以设置在第二衬底200下方，并且因此，多个第二CNT 240和第二导电图案255可以面向下方。
第一绝缘夹层110和第二绝缘夹层210可以接合在一起，使得第一导电图案155和第二导电图案255彼此面对，并且可以执行热处理。在示例性实施例中，在热处理期间，第一导电图案155和第二导电图案255可以发生热膨胀，由此去除第一凹陷160和第二凹陷，并且因此，第一导电图案155的上表面和第二导电图案255的下表面可以彼此接触。
在示例性实施例中，多个第一CNT 140的顶表面和多个第二CNT 240的底表面可以在接合工艺期间彼此接触。第一阻挡图案135和第二阻挡图案235可以彼此接触，然而，当发生未对准时，第一阻挡图案135可以接触第二绝缘夹层210的下表面，而第二阻挡图案235可以接触第一绝缘夹层110的上表面。
如上所述，当相应的第一衬底100和第二衬底200上的第一绝缘夹层110和第二绝缘夹层210彼此接合并且由相应的第一绝缘夹层110和第二绝缘夹层210包含的第一导电图案155和第二导电图案255彼此接合时，相应的第一导电图案155和第二导电图案255中的多个第一CNT 140和多个第二CNT 240也可以彼此接触。因此，第一导电图案155与第二导电图案255之间的粘合性可以得到提高，第一导电图案155与第二导电图案255之间的接触电阻可以降低并且可以增强它们之间的电连接的可靠性。
上述附图示出了在相应的第一绝缘夹层110和第二绝缘夹层210中形成一个第一导电图案155和一个第二导电图案255，然而，本发明构思并不局限于此。因此，可以在第一绝缘夹层110和第二绝缘夹层210中的每一个中形成多个导电图案。
参考不同于图5的图6A，在热处理期间，第一导电图案155和第二导电图案255可能不会充分地膨胀以去除第一凹陷160和第二凹陷，因此，可以在第一导电图案155的上表面与第二导电图案255的下表面之间形成第一气隙170。
然而，在示例性实施例中，多个第一CNT 140的顶表面可以接触多个第二CNT 240的底表面，因此，即使第一气隙170形成在第一导电图案155与第二导电图案255之间，第一导电图案155和第二导电图案255仍可以经由多个第一CNT 140和多个第二CNT 240彼此接合。
图6A中所示的第一导电图案155与第二导电图案255之间的粘合性或电连接的可靠性可以低于图5中所示的第一导电图案155与第二导电图案255之间的粘合性或电连接的可靠性。然而，粘合性或电连接的可靠性可以高于在第一导电图案155和第二导电图案255不具有多个第一CNT和多个第二CNT的情况下所获得的粘合性或电连接的可靠性。
图6A示出了第一导电图案155和第二导电图案255彼此之间完全不接触，然而，本发明构思可以不局限于此。即使可能没有通过第一导电图案155和第二导电图案255的热膨胀将第一凹陷160和第二凹陷完全地去除，仍可以去除第一凹陷160和第二凹陷的至少一部分，从而使得第一导电图案155和第二导电图案255彼此之间可以部分地接触。
图6B和图6C示出了对应于图4B和图4C中所示的第一凹陷160的第一气隙170。
参考与图6A类似的图7，即使第一气隙170形成在第一导电图案155与第二导电图案255之间，多个第一CNT 140的顶表面仍可能没有完全地接触多个第二CNT 240的对应底表面，但是，多个第一CNT 140可以设置在多个第二CNT 240之间。即使在这种情况下，至少多个第一CNT 140的上边缘可以接触多个第二CNT 240的下边缘，因此，第一导电图案155与第二导电图案255之间的粘合性或电连接的可靠性可以得到提高。
图8至图9是示出了根据示例性实施例的制造半导体器件的方法的各阶段的截面图。此方法可以包括与参考图1至图7所示的工艺基本上相同或相似的工艺，因此，在此不再对其进行详述。
参考图8，可以执行与参考图1和图2所示的工艺基本上相同或相似的工艺。
然而，多个第一CNT 140的顶表面的高度可以高于第一绝缘夹层110的顶表面的高度。
参考图9，可以执行与参考图3、图4和图7所示的工艺基本上相同或相似的工艺。
然而，多个第一CNT 140的顶表面的高度高于第一绝缘夹层110的顶表面的高度，并且多个第二CNT 240的底表面的高度低于第二绝缘夹层210的底表面的高度。因此，当包含相应的第一导电图案155和第二导电图案255的第一绝缘夹层110和第二绝缘夹层210彼此接合时，在多个第二CNT 240之间的多个第一CNT 140的上侧壁可以接触多个第二CNT240的下侧壁。因此，多个第一CNT 140和多个第二CNT 240可以用作钩环固定件(hook andloop fastener)，并且第一导电图案155与第二导电图案255之间的粘合性和电连接的可靠性可以得到提高。
图10至图13是示出了根据示例性实施例的制造半导体器件的方法的各阶段的截面图。此方法可以包括与参考图1至图7或图8至图9所示的工艺基本上相同或相似的工艺，因此，在此不再对其进行详述。
参考图10，可以执行与参考图1所示的工艺基本上相同或相似的工艺，并且可以执行与参考图3和图4所示的工艺基本上相同或相似的工艺。
也就是说，在第一沟槽120的内壁上形成第一阻挡图案135之后，第一导电图案155可以形成在第一阻挡图案135上，以填充第一沟槽120。
第一凹陷160可以形成在第一导电图案155上。
参考图11，可以执行与参考图2所示的工艺基本上相同或相似的工艺。
然而，可以在第一凹陷160中的第一导电图案155上形成多个第三CNT 145(例如导电CNT)。在示例性实施例中，多个第三CNT 145的顶表面的高度可以与第一绝缘夹层110的顶表面基本上共面，然而，本发明构思不局限于此。
参考图12A，可以执行与参考图6A所示的工艺基本上相同或相似的工艺。
因此，当包含相应的第一导电图案155和第二导电图案255的第一绝缘夹层110和第二绝缘夹层210彼此接合时，即使在第一导电图案155与第二导电图案155之间形成了第一气隙170，多个第三CNT 145的顶表面仍可以接触多个第四CNT 245的底表面，因此，第一导电图案155与第二导电图案255之间的粘合性和电连接的可靠性可以得到提高。
图12B和图12C示出了其中由参考图11示出的工艺所形成的第一凹陷160具有分别参考图4B和图4C所示的第一凹陷160的深度的情况。
参考与图9类似的图13，当包含相应的第导电图案155和第二导电图案255的第一绝缘夹层110和第二绝缘夹层210彼此接合时，多个第三CNT 145可以设置在多个第四CNT245之间，并且多个第三CNT 145的上侧壁可以接触多个第四CNT 245的下侧壁。
类似于图8，多个第三CNT 145的顶表面的高度可以高于第一绝缘夹层110的顶表面的高度，并且多个第四CNT 245的顶表面的高度可以高于第二绝缘夹层210的顶表面的高度。因此，当第一绝缘夹层110和第二绝缘夹层210彼此接合时，多个第三CNT 145和多个第四CNT 245可以用作钩环固定件。因此，第一导电图案155与第二导电图案255之间的粘合性和电连接的可靠性可以得到提高。
图14至图16是示出了根据示例性实施例的制造半导体器件的方法的各阶段的截面图。此方法可以包括与参考图1至图7所示的工艺基本上相同或相似的工艺，因此，在此不再对其进行详述。
参考图14，可以去除第一衬底100上的第一绝缘夹层110的上部以形成第三沟槽(未示出)，第三阻挡图案335可以形成在第三沟槽的内壁上，并且多个第五CNT 340可以形成在第三沟槽的底部上的第三阻挡图案335的表面上。
第一绝缘层可以形成在第三阻挡图案335、多个第五CNT 340和第一绝缘夹层110上，从而充分地填充第三沟槽的剩余部分，并且可以使第一绝缘层的上部平坦化，直到第一绝缘夹层110的顶表面可以被暴露以在第三沟槽中形成第一绝缘图案350为止。
参考图15，可以执行与参考图1至图4所示的工艺基本上相同或相似的工艺，从而在第一绝缘夹层110的上部形成第一阻挡图案135、多个第一CNT 140和第一导电图案155。
参考图16，可以执行与参考图6所示的工艺基本上相同或相似的工艺。
因此，当第一绝缘夹层110和第二绝缘夹层210彼此接合时，第一导电图案155和第二导电图案255可以彼此接合，并且多个第一CNT 140和多个第二CNT 240可以彼此接合。此外，第一绝缘图案350和第二绝缘图案450也可以彼此接合，并且多个第五CNT 340和多个第六CNT 440也可以彼此接合。如果没有发生未对准，则第三阻挡图案335和第四阻挡图案435可以接触来彼此接合。
因此，除了第一导电图案155与第二导电图案255之间的接合以及多个第一CNT140与多个第二CNT 240之间的接合之外，还可以执行第一绝缘图案350与第二绝缘图案450之间的接合以及多个第五CNT 340与多个第六CNT 440之间的接合，因此，第一绝缘夹层110与第二绝缘夹层210之间的粘合性可以得到提高，第一导电图案155与第二导电图案255之间的电连接的可靠性可以得到增强。
图16示出了第一导电图案155与第二导电图案255之间的接合以及多个第一CNT140与多个第二CNT 240之间的接合类似于图6的接合，并且第一绝缘图案350与第二绝缘图案450之间的接合以及多个第五CNT 340与多个第六CNT 440之间的接合类似于图5的接合，然而，本发明构思并不局限于此，而是也可以类似于参考本文所述的任何其他附图而示出的接合。
图17至图18是示出了根据示例性实施例的制造半导体器件的方法的各阶段的截面图。此方法可以包括与参考图14至图16示出的工艺基本上相同或相似的工艺，因此，在此不再对其进行详述。
参考图17，可以执行与参考图14所示的工艺基本上相同或相似的工艺。
然而，多个第五CNT 340的顶表面的高度可以高于第一绝缘夹层110的顶表面的高度，并且第一绝缘图案350的顶表面的高度可以低于第一绝缘夹层110的顶表面的高度。当执行用于形成第一绝缘图案350的CMP工艺时，可以在第一绝缘图案350上形成第三凹陷360，并且多个第五CNT 340的上侧壁可以从第一绝缘图案350的顶表面突出。
参考图18，可以执行与参考图15和图16所示的工艺基本上相同或相似的工艺。
然而，第一导电图案155与第二导电图案255之间的接合以及多个第一CNT 140与多个第二CNT 240之间的接合可以与参考图9所示的接合基本上相同或相似，并且第一绝缘图案350与第二绝缘图案450之间的接合以及多个第五CNT 340与多个第六CNT 440之间的接合也可以与参考图9所示的接合基本上相同或相似。
因此，可以在第一绝缘图案350与第二绝缘图案450之间形成第二气隙370，并且多个第五CNT 340的上部和多个第六CNT 440的下部可以通过第二气隙370暴露。
在参考图14至图16以及图17至图18示出的制造半导体器件的方法中，分别在第一绝缘夹层110和第二绝缘夹层210的上部形成一个第一绝缘图案350和一个第二绝缘图案450，然而，本发明构思并不限于此，并且可以在第一绝缘夹层110和第二绝缘夹层210中的每一个中形成多个绝缘图案。特别地，绝缘图案可以另外形成在以相对较低密度形成导电图案的区域中，以便起到在CMP工艺期间使密度更均匀的虚设图案的作用。
图19至图22是示出了根据示例性实施例的制造半导体器件的方法的各阶段的截面图。此方法可以包括与参考前面附图所示的工艺基本上相同或相似的工艺，因此，在此不再对其进行详述。
参考图19，第三绝缘夹层510和第四绝缘夹层520可以依次地形成在第三衬底500上，并且第五阻挡图案535、多个第七CNT 540和第三导电图案555可以形成在第四绝缘夹层520的上部。
可以在第三衬底500上形成动态随机存取存储器(DRAM)器件，并且DRAM器件的各种元件(例如，栅极结构、源极/漏极层、位线、电容器、接触插塞、通孔、布线等)可以被第三绝缘夹层510覆盖。
可以在第四绝缘夹层520中进一步形成各种布线，并且某些布线可以电连接到第三导电图案555。
在示例性实施例中，第五阻挡图案535、多个第七CNT 540和第三导电图案555可以通过与参考图1至图4所示的工艺基本上相同或相似的工艺来形成。
上述工艺也可以在第四衬底600上执行，使得第五绝缘夹层610和第六绝缘夹层620可以依次地形成在第四衬底600上，并且第六阻挡图案635、多个第八CNT 640以及第四导电图案655可以形成在第六绝缘夹层620的上部。
逻辑器件可以形成在第四衬底600上，并且逻辑器件的各种元件(例如，栅极结构、源极/漏极层、位线、电容器、接触插塞、通孔、布线等)可以被第五绝缘夹层610覆盖。
可以在第六绝缘夹层620中进一步形成各种布线，并且某些布线可以电连接到第四导电图案655。
可以执行与参考图5所示的工艺基本上相同或相似的工艺，由此使得包含第三导电图案555的第四绝缘夹层520以及包含第四导电图案655的第六绝缘夹层620可以彼此接合。第四绝缘夹层520和第六绝缘夹层620也可以通过其它工艺彼此接合，例如与参考图6A-6C、图7、图9、图12A-12C、图13、图16或图18所示的工艺基本上相同或相似的工艺。
参考图20，半导体层710可以形成在第五衬底700上，并且光电二极管720可以形成在半导体层710的上部。
第五衬底700可以包括有源像素区域、外围区域和输入/输出(I/O)区域，并且第五衬底700可以掺杂有例如p型杂质。在示例性实施例中，半导体层710可以通过外延生长工艺形成在第五衬底700上，并且半导体层710可以以低于第五衬底700的掺杂浓度掺杂有例如p型杂质。
可以在半导体层710上形成栅电极(未示出)，并且可以在栅电极的两侧进一步形成杂质区域，从而形成晶体管(未示出)。可以在第五衬底700的有源像素区域上形成能够形成单位像素的传送晶体管、复位晶体管、转换晶体管和选择晶体管，并且可以在第五衬底700的外围区域上形成用于电路的晶体管。
可以通过将杂质掺杂到半导体层710中来形成光电二极管720，并且可以在第五衬底700的有源像素区域上的半导体层710的各部分处形成多个光电二极管720。
第七绝缘夹层730、第八绝缘夹层740和第九绝缘夹层760可以依次形成在半导体层710和光电二极管720上，并且第一布线752、第二布线754、第三布线772和第四布线774可以形成在第七绝缘夹层730、第八绝缘夹层740或第九绝缘夹层760中的一个或多个中。在示例性实施例中，第一布线752和第三布线772可以形成在第五衬底700的有源像素区域上，并且第二布线754和第四布线774可以形成在第五衬底700的I/O区域上。
第一布线752、第二布线754、第三布线772和第四布线774可以包括金属，例如铜、铂、钨、铝等，并且例如可以通过镶嵌工艺来形成。
参考图21，在去除了第四衬底600的上部之后，可以在第四衬底600上形成第十绝缘夹层810，并且可以在第十绝缘夹层810的上部形成第七阻挡图案835、多个第九CNT 840以及第五导电图案855。
在示例性实施例中，第四衬底600的上部可以通过研磨工艺去除。
另外，第十一绝缘夹层910可以形成在第五衬底700上的第九绝缘夹层760和第三布线772和第四布线774上，且可以在第十一绝缘夹层910的上部形成第八阻挡图案935、多个第十CNT 940和第六导电图案955，并且第五衬底700可以旋转180度，从而使得第十绝缘夹层810和第十一绝缘夹层910可以彼此接合。第五导电图案855和第六导电图案955以及多个第九CNT 840和多个第十CNT 940可以通过与参考图5、图6A-6C等所示的工艺基本上相同或相似的工艺来接合。
参考图22，在去除了第五衬底700以暴露半导体层710的上表面之后，可以在半导体层710的暴露的上表面上形成栅格结构960。
在示例性实施例中，栅格结构960可以形成为不与有源像素区域中的光电二极管720垂直地重叠，并且单位像素可以由栅格结构960限定。栅格结构960可以包括金属，如钨、铝等。
当栅格结构960形成在有源像素区域中时，可以在外围区域中形成用于阻碍入射光的阻碍层(未示出)，并且接触插塞(未示出)和焊盘(未示出)(它们中的一些可以电连接到第二布线754)可以形成在I/O区域中。
可以在栅格结构960和半导体层710上共形地形成保护层970，可以在保护层970上形成滤色器层980，并且在有源像素区域中，可以在滤色器层980中形成滤色器985。
滤色器层980可以包括例如有机层或光阻层。滤色器985可以通过对滤色器层980进行图案化来形成，并且红光、绿光和蓝光可以分别穿透滤色器985。
微透镜990可以形成在每一个滤色器985上，使得可以制造出半导体器件。
半导体器件可以包括依次堆叠的DRAM器件、逻辑器件和互补金属氧化物半导体(CMOS)图像传感器，它们可以通过分别包含第三导电图案555的第四绝缘夹层520、包含第四导电图案655的第六绝缘夹层620、包含第五导电图案855的第十绝缘夹层810和包含第六导电图案955的第十一绝缘夹层910来彼此接合，并且它们之间的粘合性和电连接的可靠性可以因为多个第七CNT 540、多个第八CNT 640、多个第九CNT 840和多个第十CNT 940而得到提高。
图23至图25是示出了根据示例性实施例的制造半导体器件的方法的各阶段的截面图。此方法可以包括与参考图19至图22所示的工艺基本上相同或相似的工艺，因此，在此不再对其进行详述。
参考图23，可以执行与参考图19至图21所示的工艺基本上相同或相似的工艺。
然而，可以不执行用于形成DRAM器件的工艺，例如在第三衬底500上依次形成第三绝缘夹层510和第四绝缘夹层520，并在第四绝缘夹层520的上部形成第五阻挡图案535、多个第七CNT 540以及第三导电图案555。
因此，第四衬底600上的第十绝缘夹层810的上部处的第五导电图案855和多个第九CNT 840可以分别与第五衬底700上的第十一绝缘夹层910的上部处的第六导电图案955和多个第十CNT 940接合。
不同于图21，可以不执行对第四衬底600的部分去除。
参考图24，可以执行与参考图22所示的工艺基本上相同或相似的工艺，这样使得去除了第五衬底700，并且形成了栅格结构960、保护层970、滤色器层980、滤色器985和微透镜990。
参考图25，透明粘合剂1000可以接合到其上具有微透镜990的滤色器层980的上表面，可以在透明粘合剂1000上形成处理衬底(handling substrate)1100，并且可以使用处理衬底1100来将整个结构旋转180度。
各种布线以及覆盖布线的第十二绝缘夹层1110可以形成在第四衬底600上，并且可以在第十二绝缘夹层1110上形成包括DRAM器件的芯片1200。
第九阻挡图案1135、多个第十一CNT 1140和第七导电图案1155可以形成在第十二绝缘夹层1110的上部，以便电连接到一些布线，并且芯片1200可以在其下部包括第十阻挡图案1235、多个第十二CNT 1240和第八导电图案1255。因此，第七导电图案1155和第八导电图案1255可以彼此接合，并且多个第十一CNT 1140和多个第十二CNT 1240可以彼此接合。
此半导体器件可以包括接触式图像传感器(CIS)、逻辑器件和DRAM器件，它们依次堆叠为通过参考图19至图22所示的方法而制造的半导体器件，并且CIS、逻辑器件与DRAM器件之间的粘合性和电连接的可靠性可以通过多个第九CNT 840、多个第十CNT 940、多个第十一CNT 1140和多个第十二CNT 1240而得到提高。
图26是示出了根据示例性实施例的半导体器件的截面图。此半导体器件可以包括与先前示出的元件基本上相同或相似的元件，因此，在此不再对其进行详述。
参考图26，半导体器件可以包括逻辑裸片1400以及依次堆叠在封装衬底1300上的第一DRAM裸片1500、第二DRAM裸片1700和第三DRAM裸片1900。
封装衬底1300和逻辑裸片1400可以通过设置在其间的凸块1350而彼此电连接。插入件(未示出)可以进一步设置在封装衬底1300与逻辑裸片1400之间，使得封装衬底1300与逻辑裸片1400之间的电连接可以变得更加容易。
逻辑裸片1400与第一DRAM裸片1500，或者第一DRAM裸片1500、第二DRAM裸片1700与第三DRAM裸片1900可以通过参考图1至图18所示的方法而彼此接合。
特别地，第十一阻挡图案1435、多个第十三CNT 1440和第九导电图案1455可以形成在逻辑裸片1400的上部，并且第十二阻挡图案1535、多个第十四CNT 1540和第十导电图案1555可以形成在第一DRAM裸片1500的下部。第九导电图案1455和第十导电图案1555可以彼此接合，并且多个第十三CNT 1440和多个第十四CNT 1540可以彼此接合。
另外，第十三阻挡图案1635、多个第十五CNT 1640和第十一导电图案1655可以形成在第一DRAM裸片1500的上部，并且第十四阻挡图案1735、多个第十六CNT 1740和第十二导电图案1755可以形成在第二DRAM裸片1700的下部。第十一导电图案1655和第十二导电图案1755可以彼此接合，并且多个第十五CNT 1640和多个第十六CNT 1740可以彼此接合。
另外，第十五阻挡图案1835、多个第十七CNT 1840和第十三导电图案1855可以形成在第二DRAM裸片1700的上部，并且第十六阻挡图案1935、多个第十八CNT 1940和第十四导电图案1955可以形成在第三DRAM裸片1900的下部。第十三导电图案1855和第十四导电图案1955可以彼此接合，并且多个第十七CNT 1840和多个第十八CNT 1940可以彼此接合。
图26示出了半导体器件包括依次堆叠的三个DRAM裸片，即，第一DRAM裸片1500、第二DRAM裸片1700和第三DRAM裸片1900，然而本发明构思可以不局限于此，并且半导体器件可以包括三个以上依次堆叠的DRAM裸片。
逻辑裸片1400与第一DRAM裸片1500，或者第一DRAM裸片1500、第二DRAM裸片1700和第三DRAM裸片1900中的一个可以不通过导电图案和CNT进行接合，而是可以通过例如硅通孔(TSV)和凸块进行接合。
前述内容是对示例性实施例的说明，不应被解释为对其加以了限制。尽管已经描述了一些示例性实施例，但是本领域技术人员将容易理解的是，在不实质地脱离本发明构思的新颖教导和优点的前提下可以在示例性实施例中作出许多修改。因此，所有这样的修改旨在被包括在如权利要求中所限定的本发明构思的范围内。在权利要求中，手段加功能的句型旨在涵盖执行所述功能时本文中所描述的结构，其不仅涵盖结构等同物，而且涵盖等同结构。因此，应当理解，前述内容是对各种示例性实施例的说明，不应被解释为局限于所公开的具体示例性实施例，并且，对所公开的示例性实施例以及其他示例性实施例作出的修改旨在被包括在所附权利要求的范围内。

Claims (12)

1.一种堆叠的半导体器件，包括：
设置有第一导电图案的第一衬底，所述第一衬底包括:
所述第一导电图案，所述第一导电图案被包含在第一衬底上的第一绝缘夹层的上部沟槽中；
多个第一碳纳米管CNT，所述多个第一CNT形成在所述第一导电图案中，并相对于所述第一衬底的上表面在垂直方向上延伸，所述多个第一CNT中的每一个的侧壁的至少一部分被所述第一导电图案覆盖；
设置有第二导电图案的第二衬底，所述第二衬底包括：
所述第二导电图案，所述第二导电图案被包含在第二衬底下方的第二绝缘夹层的下部沟槽中，所述第二绝缘夹层的下表面接触所述第一绝缘夹层的上表面；以及
多个第二CNT，所述多个第二CNT形成在所述第二导电图案中，并在垂直方向上延伸，所述多个第二CNT中的每一个的侧壁的至少一部分被所述第二导电图案覆盖，
其中所述多个第一CNT的顶表面与所述第一绝缘夹层的顶表面基本上共面，并且所述多个第二CNT的底表面与所述第二绝缘夹层的底表面基本上共面，
其中所述第一衬底和所述第二衬底彼此接合以形成堆叠结构，且当所述第一衬底和所述第二衬底彼此接合时，所述第一导电图案和所述第二导电图案在垂直方向上彼此面对，并且所述多个第一CNT中的至少一个和所述多个第二CNT中的至少一个彼此接触，以改善所述第一导电图案和所述第二导电图案之间的粘合性和电连接。
2.根据权利要求1所述的半导体器件，其中所述多个第一CNT中的所述至少一个的顶表面与所述多个第二CNT中的所述至少一个的底表面彼此接触。
3.根据权利要求1所述的半导体器件，其中，在所述第一导电图案与所述第二导电图案之间存在有第一气隙。
4.根据权利要求1所述的半导体器件，其中所述第一导电图案的顶表面与所述第二导电图案的底表面彼此接触。
5.根据权利要求1所述的半导体器件，还包括：
第一阻挡图案，所述第一阻挡图案覆盖所述第一导电图案的下表面和侧壁；以及
第二阻挡图案，所述第二阻挡图案覆盖所述第二导电图案的上表面和侧壁。
6.根据权利要求5所述的半导体器件，其中所述多个第一CNT的底表面接触所述第一阻挡图案的表面，并且所述多个第二CNT的顶表面接触所述第二阻挡图案的表面。
7.根据权利要求4所述的半导体器件，还包括：
第一绝缘图案，所述第一绝缘图案被包含在所述第一绝缘夹层的上部；
多个第三CNT，所述多个第三CNT在垂直方向上延伸，所述多个第三CNT中的每一个的侧壁的至少一部分被所述第一绝缘图案覆盖；
第二绝缘图案，所述第二绝缘图案被包含在所述第二绝缘夹层的下部；以及
多个第四CNT，所述多个第四CNT在垂直方向上延伸，所述多个第四CNT中的每一个的侧壁的至少一部分被所述第二绝缘图案覆盖，
其中所述第一绝缘图案和所述第二绝缘图案在垂直方向上彼此面对，并且所述多个第三CNT中的至少一个与所述多个第四CNT中的至少一个彼此接触。
8.根据权利要求7所述的半导体器件，其中所述第一绝缘图案的顶表面与所述第二绝缘图案的底表面彼此接触。
9.根据权利要求7所述的半导体器件，其中在所述第一绝缘图案与所述第二绝缘图案之间存在有第二气隙。
10.根据权利要求1所述的半导体器件，其中所述第一绝缘夹层和所述第二绝缘夹层至少包括基本上相同的材料，并且所述第一导电图案和所述第二导电图案至少包括基本上相同的材料。
11.一种堆叠的半导体器件，包括：
设置有第一导电图案的第一衬底，所述第一衬底包括：
所述第一导电图案，所述第一导电图案被包含在第一衬底上的第一绝缘夹层的上部沟槽中；
多个第一碳纳米管CNT，所述多个第一CNT在垂直方向上延伸穿过所述第一导电图案，所述多个第一CNT中的每一个从所述第一导电图案的上表面突出；
设置有第二导电图案的第二衬底，所述第二衬底包括：
所述第二导电图案，所述第二导电图案被包含在第二衬底下方的第二绝缘夹层的下部沟槽中，所述第二绝缘夹层的下表面接触所述第一绝缘夹层的上表面；以及
多个第二CNT，所述多个第二CNT在垂直方向上延伸穿过所述第二导电图案，所述多个第二CNT中的每一个从所述第二导电图案的下表面突出，
其中所述多个第一CNT的顶表面与所述第一绝缘夹层的顶表面基本上共面，并且所述多个第二CNT的底表面与所述第二绝缘夹层的底表面基本上共面，
其中所述第一衬底和所述第二衬底彼此接合以形成堆叠结构，且当所述第一衬底和所述第二衬底彼此接合时，所述第一导电图案和所述第二导电图案在垂直方向上彼此面对，并且所述多个第一CNT中的至少一个的上部与所述多个第二CNT中的至少一个的下部彼此接触，以改善所述第一导电图案和所述第二导电图案之间的粘合性和电连接。
12.根据权利要求11所述的半导体器件，其中，
其中在所述第一导电图案与所述第二导电图案之间存在有气隙。
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