CN109103107A - 具有锗硅源漏的mos晶体管的制造方法 - Google Patents
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Abstract
本发明公开了一种具有锗硅源漏的MOS晶体管的制造方法,包括步骤:步骤一、提供一硅衬底,在硅衬底的表面形成栅极结构。步骤二、在栅极结构的两侧形成侧面具有∑形状的凹槽,包括分步骤:步骤21、形成硬掩膜层;步骤22、光刻定义出凹槽的形成区域,进行硬掩膜层的刻蚀;进行硅衬底的第一次干法刻蚀并形成具有第一体积的凹槽;步骤23、采用第一离子注入工艺对凹槽的周侧的硅进行预处理;步骤24、进行第二次湿法刻蚀将凹槽扩展到第二体积;步骤三、在凹槽中填充锗硅外延层形成嵌入式锗硅层。步骤四、进行源漏注入形成源区和漏区。本发明能扩大凹槽的体积从而扩大嵌入式锗硅层的体积,从而改善MOS晶体管特别是PMOS管的电学性能。
Description
技术领域
本发明涉及一种半导体集成电路制造方法,特别是涉及一种具有锗硅源漏的MOS晶体管的制造方法。
背景技术
MOS晶体管特别是PMOS管的源漏区往往需要形成嵌入式锗硅外延层,嵌入式锗硅外延层能够对PMOS管的沟道区的应力进行调制从而有利于提高PMOS的载流子迁移率,从而提高PMOS管的电学性能。MOS晶体管也通常简称为FET组成,PMOS管简称为pFET组件,NMOS管简称为nFET组件。
发明内容
本发明所要解决的技术问题是提供一种具有锗硅源漏的MOS晶体管的制造方法,能增加嵌入式锗硅外延层的体积,从而提高器件的电学性能。
为解决上述技术问题,本发明提供的具有锗硅源漏的MOS晶体管的制造方法包括如下步骤:
步骤一、提供一硅衬底,在所述硅衬底的表面形成栅极结构,所述栅极结构的侧面形成有侧墙。
步骤二、在所述栅极结构的两侧形成侧面具有∑(sigma)形状的凹槽,包括如下分步骤:
步骤21、形成硬掩膜层。
步骤22、采用光刻工艺在所述栅极结构的两侧定义出所述凹槽的形成区域,采用刻蚀工艺将所述凹槽形成区域的所述硬掩膜层去除;对所述凹槽形成区域的的所述硅衬底进行第一次干法刻蚀并形成具有第一体积的所述凹槽。
步骤23、采用第一离子注入工艺对第一体积的所述凹槽的周侧的硅进行预处理,所述预处理用于增加后续第二次湿法刻蚀的效率。
步骤24、进行第二次湿法刻蚀将所述凹槽由第一体积扩展到第二体积,通过所述预处理增加所述第二次湿法刻蚀形成的所述第二体积。
步骤三、在所述凹槽中填充锗硅外延层形成嵌入式锗硅外延层,通过增加所述第二体积增加所述嵌入式锗硅外延层并提高MOS晶体管的电学性能。
步骤四、在形成有所述嵌入式锗硅外延层的所述栅极结构的两侧进行源漏注入形成源区和漏区。
进一步的改进是,具有锗硅源漏的MOS晶体管为PMOS管。
进一步的改进是,步骤一中所述栅极结构由栅介质层和多晶硅栅叠加而成。
进一步的改进是,所述栅极结构作为伪栅,在所述步骤四的所述源区和所述漏区形成之后所述伪栅被去除,之后在所述伪栅去除的区域中形成金属栅结构。
进一步的改进是,所述金属栅结构为HKMG。
进一步的改进是,步骤一中在所述硅衬底表面形成有浅沟槽场氧,由所述浅沟槽场氧隔离出有源区,MOS晶体管形成于有源区中。
进一步的改进是,步骤一中所述侧墙的材料为氮化硅。
进一步的改进是,所述硬掩膜层的材料为氮化硅。
进一步的改进是,所述第一离子注入工艺的注入杂质包括硅,砷,氮,氩气,注入剂量为3E13cm-2~2E14cm-2。
进一步的改进是,步骤三中形成嵌入式锗硅外延层的分步骤包括:
步骤31、形成由锗硅材料组成的缓冲层。
步骤32、形成由锗硅材料组成的主体层,所述主体层的锗浓度大于所述缓冲层的锗浓度。
步骤33、形成由硅材料组成的盖帽层。
进一步的改进是,所述缓冲层由第一缓冲子层和第二缓冲子层叠加而成。
进一步的改进是,所述第一缓冲子层的锗浓度为25%,所述第二缓冲子层的锗浓度为25%~30%。
进一步的改进是,所述主体层的锗浓度为30%~40%。
进一步的改进是,在同一所述硅衬底上还同时形成有NMOS管,在步骤二和三中所述NMOS管被保护而不形成所述凹槽以及所述嵌入式锗硅外延层。
进一步的改进是,所述NMOS管形成于P阱上,所述PMOS管形成于N阱上。
本发明对∑形状的凹槽的形成工艺做了精心的设计,主要是对凹槽的刻蚀工艺进行了改进,将凹槽的刻蚀工艺分成了第一次干法刻蚀和第二次湿法刻蚀,且在第二次湿法刻蚀之前增加了一次采用第一次离子注入工艺进行的预处理,通过预处理增加第二次湿法刻蚀的效率,如通过使凹槽周侧的硅在经过第一次离子注入后使晶格结构改变,晶格结构改变后的硅中非晶结构会增加,从而有利用湿法刻蚀,从而使得第二次湿法刻蚀完成后使凹槽的体积扩展的更大,即第二体积的值会得到增加,由于最后嵌入式锗硅外延层是形成于第二体积的凹槽中,故能增加嵌入式锗硅外延层的体积,本发明利用到嵌入式锗硅外延层的体积越大MOS晶体管的电学性能越好的特征,实现对MOS晶体管特别是PMOS管的电学性能的改善。
附图说明
下面结合附图和具体实施方式对本发明作进一步详细的说明:
图1是本发明实施例方法的流程图;
图2A-图2E是本发明实施例方法各步骤中的器件结构图。
具体实施方式
如图1所示,是本发明实施例方法的流程图;如图2A至图2E所示,是本发明实施例方法各步骤中的器件结构图,本发明实施例具有锗硅源漏的MOS晶体管的制造方法包括如下步骤:
步骤一、如图2A所示,提供一硅衬底101,在所述硅衬底101的表面形成栅极结构105,所述栅极结构105的侧面形成有侧墙106,该侧墙106也同时延伸到所述栅极结构105的表面。
所述栅极结构105由栅介质层和多晶硅栅叠加而成。所述栅极结构105作为伪栅,在所述步骤四的所述源区和所述漏区形成之后所述伪栅去除,之后在所述伪栅去除的区域中形成金属栅结构。所述金属栅结构为HKMG。
在所述硅衬底101表面形成有浅沟槽场氧,由所述浅沟槽场氧隔离出有源区,MOS晶体管形成于有源区中。
所述侧墙106的材料为氮化硅。
本发明实施例中,具有锗硅源漏的MOS晶体管为PMOS管。在同一所述硅衬底101上还同时形成有NMOS管,在形成步骤二和三中所述NMOS管被保护而不形成凹槽以及嵌入式锗硅外延层。所述NMOS管形成于P阱104上,所述PMOS管形成于N阱103上。
步骤二、在所述栅极结构105的两侧形成侧面具有∑形状的凹槽,包括如下分步骤:
步骤21、如图2B所示,形成硬掩膜层107。
步骤22、如图2C所示,采用光刻工艺在所述栅极结构105的两侧定义出所述凹槽的形成区域,采用刻蚀工艺将所述凹槽形成区域的所述硬掩膜层107去除;对所述凹槽形成区域的的所述硅衬底101进行第一次干法刻蚀并形成具有第一体积的所述凹槽,图2C用标记108a标出了具有第一体积的所述凹槽。
步骤23、如图2D所示,采用第一离子注入工艺对第一体积的所述凹槽的周侧的硅进行预处理,所述预处理用于增加后续第二次湿法刻蚀的效率。第一离子注入工艺如标记201所示。
所述第一离子注入工艺的注入杂质包括硅,砷,氮,氩气,注入剂量为3E13cm-2~2E14cm-2。本发明实施例中,所述第一离子注入工艺能使凹槽周侧的硅的晶格结构改变,晶格结构改变后的硅中非晶结构会增加,从而有利用后续的湿法刻蚀。
步骤24、如图2E所示,进行第二次湿法刻蚀将所述凹槽由第一体积扩展到第二体积,通过所述预处理增加所述第二次湿法刻蚀形成的所述第二体积。
图2E中单独将形成所述凹槽的区域的多个所述栅极结构105表示出来,为了更清楚的表示所述凹槽结构,图2E中的各区域都采用不带填充的线体图形表示。最后形成的所述凹槽如标记108所示,标记108的顶部开口减小且顶部开口和所述栅极结构105侧面的侧墙106对齐,如虚线AA所示,图2E中的侧墙106叠加了所述硬掩膜层107刻蚀后残留在所述栅极结构105的侧面的部分;标记108的所述凹槽的口径逐渐增加并在增加到最大口径后又逐渐减少,最大口径的两侧和所述栅极结构105的侧面对齐,如虚线BB所示。
步骤三、如图2E所示,在所述凹槽中填充锗硅外延层形成嵌入式锗硅外延层,通过增加所述第二体积增加所述嵌入式锗硅外延层并提高MOS晶体管的电学性能。
如图2E所示,形成嵌入式锗硅外延层的分步骤包括:
步骤31、形成由锗硅材料组成的缓冲层。
所述缓冲层由第一缓冲子层1091和第二缓冲子层1092叠加而成。图2E中,第一缓冲子层1091和第二缓冲子层1092之间用一根虚线分割。
所述第一缓冲子层1091的锗浓度为25%,所述第二缓冲子层1092的锗浓度为25%~30%。
步骤32、形成由锗硅材料组成的主体层1093,所述主体层1093的锗浓度大于所述缓冲层的锗浓度。较佳为,所述主体层1093的锗浓度为30%~40%。
步骤33、形成由硅材料组成的盖帽层1094。
步骤四、在形成有所述嵌入式锗硅外延层的所述栅极结构105的两侧进行源漏注入形成源区和漏区。
本发明实施例对∑形状的凹槽的形成工艺做了精心的设计,主要是对凹槽的刻蚀工艺进行了改进,将凹槽的刻蚀工艺分成了第一次干法刻蚀和第二次湿法刻蚀,且在第二次湿法刻蚀之前增加了一次采用第一次离子注入工艺进行的预处理,通过预处理增加第二次湿法刻蚀的效率,如通过使凹槽周侧的硅在经过第一次离子注入后使晶格结构改变,晶格结构改变后的硅中非晶结构会增加,从而有利用湿法刻蚀,从而使得第二次湿法刻蚀完成后使凹槽的体积扩展的更大,即第二体积的值会得到增加,由于最后嵌入式锗硅外延层是形成于第二体积的凹槽中,故能增加嵌入式锗硅外延层的体积,本发明实施例利用到嵌入式锗硅外延层的体积越大MOS晶体管的电学性能越好的特征,实现对MOS晶体管特别是PMOS管的电学性能的改善。
以上通过具体实施例对本发明进行了详细的说明,但这些并非构成对本发明的限制。在不脱离本发明原理的情况下,本领域的技术人员还可做出许多变形和改进,这些也应视为本发明的保护范围。
Claims (15)
1.一种具有锗硅源漏的MOS晶体管的制造方法,其特征在于,包括如下步骤:
步骤一、提供一硅衬底,在所述硅衬底的表面形成栅极结构,所述栅极结构的侧面形成有侧墙;
步骤二、在所述栅极结构的两侧形成侧面具有∑形状的凹槽,包括如下分步骤:
步骤21、形成硬掩膜层;
步骤22、采用光刻工艺在所述栅极结构的两侧定义出所述凹槽的形成区域,采用刻蚀工艺将所述凹槽形成区域的所述硬掩膜层去除;对所述凹槽形成区域的的所述硅衬底进行第一次干法刻蚀并形成具有第一体积的所述凹槽;
步骤23、采用第一离子注入工艺对第一体积的所述凹槽的周侧的硅进行预处理,所述预处理用于增加后续第二次湿法刻蚀的效率;
步骤24、进行第二次湿法刻蚀将所述凹槽由第一体积扩展到第二体积,通过所述预处理增加所述第二次湿法刻蚀形成的所述第二体积;
步骤三、在所述凹槽中填充锗硅外延层形成嵌入式锗硅外延层,通过增加所述第二体积增加所述嵌入式锗硅外延层并提高MOS晶体管的电学性能;
步骤四、在形成有所述嵌入式锗硅外延层的所述栅极结构的两侧进行源漏注入形成源区和漏区。
2.如权利要求1所述的具有锗硅源漏的MOS晶体管的制造方法,其特征在于:具有锗硅源漏的MOS晶体管为PMOS管。
3.如权利要求2所述的具有锗硅源漏的MOS晶体管的制造方法,其特征在于:步骤一中所述栅极结构由栅介质层和多晶硅栅叠加而成。
4.如权利要求3所述的具有锗硅源漏的MOS晶体管的制造方法,其特征在于:所述栅极结构作为伪栅,在所述步骤四的所述源区和所述漏区形成之后所述伪栅被去除,之后在所述伪栅去除的区域中形成金属栅结构。
5.如权利要求4所述的具有锗硅源漏的MOS晶体管的制造方法,其特征在于:所述金属栅结构为HKMG。
6.如权利要求1所述的具有锗硅源漏的MOS晶体管的制造方法,其特征在于:步骤一中在所述硅衬底表面形成有浅沟槽场氧,由所述浅沟槽场氧隔离出有源区,MOS晶体管形成于有源区中。
7.如权利要求1所述的具有锗硅源漏的MOS晶体管的制造方法,其特征在于:步骤一中所述侧墙的材料为氮化硅。
8.如权利要求7所述的具有锗硅源漏的MOS晶体管的制造方法,其特征在于:所述硬掩膜层的材料为氮化硅。
9.如权利要求8所述的具有锗硅源漏的MOS晶体管的制造方法,其特征在于:所述第一离子注入工艺的注入杂质包括硅,砷,氮,氩气,注入剂量为3E13cm-2~2E14cm-2。
10.如权利要求1所述的具有锗硅源漏的MOS晶体管的制造方法,其特征在于:步骤三中形成嵌入式锗硅外延层的分步骤包括:
步骤31、形成由锗硅材料组成的缓冲层;
步骤32、形成由锗硅材料组成的主体层,所述主体层的锗浓度大于所述缓冲层的锗浓度;
步骤33、形成由硅材料组成的盖帽层。
11.如权利要求10所述的具有锗硅源漏的MOS晶体管的制造方法,其特征在于:所述缓冲层由第一缓冲子层和第二缓冲子层叠加而成。
12.如权利要求11所述的具有锗硅源漏的MOS晶体管的制造方法,其特征在于:所述第一缓冲子层的锗浓度为25%,所述第二缓冲子层的锗浓度为25%~30%。
13.如权利要求10所述的具有锗硅源漏的MOS晶体管的制造方法,其特征在于:所述主体层的锗浓度为30%~40%。
14.如权利要求2所述的具有锗硅源漏的MOS晶体管的制造方法,其特征在于:在同一所述硅衬底上还同时形成有NMOS管,在步骤二和三中所述NMOS管被保护而不形成所述凹槽以及所述嵌入式锗硅外延层。
15.如权利要求14所述的具有锗硅源漏的MOS晶体管的制造方法,其特征在于:所述NMOS管形成于P阱上,所述PMOS管形成于N阱上。
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