CN109037329A - Semiconductor devices and preparation method thereof - Google Patents
Semiconductor devices and preparation method thereof Download PDFInfo
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- CN109037329A CN109037329A CN201810802979.2A CN201810802979A CN109037329A CN 109037329 A CN109037329 A CN 109037329A CN 201810802979 A CN201810802979 A CN 201810802979A CN 109037329 A CN109037329 A CN 109037329A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 92
- 238000002360 preparation method Methods 0.000 title abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 174
- 239000002184 metal Substances 0.000 claims abstract description 174
- 239000000758 substrate Substances 0.000 claims description 41
- 239000010936 titanium Substances 0.000 claims description 20
- 229910002601 GaN Inorganic materials 0.000 claims description 18
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 18
- 229910052719 titanium Inorganic materials 0.000 claims description 18
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 16
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims description 14
- 238000000576 coating method Methods 0.000 claims description 14
- 239000011248 coating agent Substances 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 150000004767 nitrides Chemical class 0.000 claims description 11
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 230000005533 two-dimensional electron gas Effects 0.000 claims description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 230000009977 dual effect Effects 0.000 abstract description 4
- 238000000151 deposition Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 8
- 239000004615 ingredient Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 239000004411 aluminium Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 238000009616 inductively coupled plasma Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 3
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229960000909 sulfur hexafluoride Drugs 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The present invention relates to technical field of semiconductors, a kind of semiconductor devices and preparation method thereof is provided.The semiconductor devices includes: first medium layer；Second dielectric layer extends in first grid contact hole the bottom for covering the first grid contact hole；First grid metal layer extends in the first grid contact hole to cover the second dielectric layer for being located at first grid contact hole bottom；Third dielectric layer extends in second grid contact hole the bottom for covering the second grid contact hole；Second grid metal layer extends in the second grid contact hole to cover the third dielectric layer for being located at second grid contact hole bottom；First source/drain；Second source/drain；Grid.The semiconductor devices of dual gate metal structure of the invention can obtain better devices switch characteristic.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of semiconductor devices and a kind of systems of semiconductor devices
Make method.
Background technique
Existing ALGaN (aluminium gallium nitride alloy)/GaN (aluminium gallium nitride alloy) HEMT (High Electron Mobility
Transistor, high electron mobility transistor) etc. semiconductor devices often switching characteristic is bad, it is, therefore, desirable to provide a kind of
Semiconductor devices of switching characteristic and preparation method thereof can be enhanced.
Summary of the invention
To solve the above problems, the present invention provides a kind of semiconductor devices and preparation method thereof of dual gate metal structure,
The switching characteristic of device can be enhanced.
Specifically, a kind of semiconductor devices provided in an embodiment of the present invention, comprising: semiconductor substrate；First medium layer, if
It is placed on the semiconductor substrate；Second dielectric layer is set on the first medium layer and extends to first grid contact hole
The interior bottom to cover the first grid contact hole, the first grid contact hole is through the first medium layer and protrudes into institute
State semiconductor-based intralamellar part；First grid metal layer, is set in the second dielectric layer and extends to the first grid and connect
To cover the second dielectric layer for being located at first grid contact hole bottom in contact hole；Third dielectric layer is set to described
On first grid metal layer and the bottom for covering the second grid contact hole is extended in second grid contact hole, it is described
Second grid contact hole sequentially passes through the first grid metal layer, the second dielectric layer and the first medium layer and protrudes into
The semiconductor-based intralamellar part；Second grid metal layer is set on the third dielectric layer and extends to the second grid
To cover the third dielectric layer for being located at second grid contact hole bottom in contact hole；First source/drain is set to institute
It states on second grid metal layer and the first source drain contact hole of filling, first source drain contact hole sequentially passes through described
Second grid metal layer, the third dielectric layer, the first grid metal layer, the second dielectric layer and the first medium
Layer；Second source/drain, is set on the first grid metal layer and fills the second source drain contact hole, and second source/
Drain contact hole sequentially passes through the first grid metal layer, the second dielectric layer and the first medium layer；And grid,
It is set on the first grid metal layer and the second grid metal layer and fills the first grid contact hole and described
Second grid contact hole.
The present invention in one embodiment, the first grid metal layer is made of the first metal, the second gate
Pole metal layer is made of the second metal, and the work function of first metal is lower than the bimetallic work function；Described first
Gate contact hole is connected with the second grid contact hole.
The present invention in one embodiment, first metal is aluminum metal or nickel metal, and second metal is
Cobalt metal or molybdenum.
The present invention in one embodiment, the semiconductor substrate includes: silicon substrate, and is set to silicon lining
The nitride buffer layer of bottom surface and the aluminum gallium nitride layer for being set to the nitride buffer layer surface.
The present invention in one embodiment, the first grid contact hole and the second grid contact hole are stretched respectively
Enter the aluminum gallium nitride layer.
The present invention in one embodiment, the width of the first grid contact hole and the second grid contact hole
Width ratio be 1:1.
The present invention in one embodiment, be formed with two between the nitride buffer layer and the aluminum gallium nitride layer
Dimensional electron gas channel.
The present invention in one embodiment, first source/drain, second source/drain and/or the grid
It is made of metal ohmic contact, the metal ohmic contact successively includes: the first titanium coating, aluminum metal layer, from bottom to up
Two titanium coatings and titanium nitride layer.
On the other hand, a kind of semiconductor devices provided in an embodiment of the present invention, comprising: semiconductor substrate, the semiconductor
Two-dimensional electron gas channel is formed in substrate；First medium layer is set on the semiconductor substrate；Second dielectric layer, setting
In on the first medium layer and extending in first grid contact hole and cover the bottom of the first grid contact hole, institute
First grid contact hole is stated through the first medium layer and protrudes into the semiconductor-based intralamellar part；First grid metal layer, if
It is placed in the second dielectric layer and extends in the first grid contact hole and the first grid contact hole is located at covering
The second dielectric layer of bottom；Third dielectric layer, is set on the first grid metal layer and extends to second grid and connect
To cover the bottom of the second grid contact hole and be connect with the second dielectric layer in contact hole, the second grid contact
Hole is through the first grid metal layer, the second dielectric layer and the first medium layer and protrudes into the semiconductor substrate
Portion；Second grid metal layer is set on the third dielectric layer and extends in the second grid contact hole to cover position
In second grid contact hole bottom the third dielectric layer and connect with the first grid metal layer；First source/drain
Pole is set on the second grid metal layer and fills the first source drain contact hole, and first source drain contact hole is passed through
Wear the second grid metal layer, the third dielectric layer, the first grid metal layer, the second dielectric layer and described
One dielectric layer；Second source/drain is set on the first grid metal layer and fills the second source drain contact hole, described
The first grid metal layer, the second dielectric layer and the first medium layer are run through in second source drain contact hole；And grid
Pole, be set on the first grid metal layer and the second grid metal layer and fill the first grid contact hole and
The second grid contact hole, the first grid contact hole are connected with the second grid contact hole；Wherein, described first
Gate metal layer is made of the first metal, and the second grid metal layer is made of the second metal, the work content of first metal
Number is different from the bimetallic work function.
Another aspect, a kind of production method of semiconductor devices provided in an embodiment of the present invention, comprising steps of in semiconductor
First medium layer is formed on substrate, wherein being formed with Two-dimensional electron gas channel in the semiconductor substrate；Described first is etched to be situated between
Matter layer and the semiconductor substrate are to form first grid contact hole, wherein the first grid contact hole is situated between through described first
Matter layer and protrude into the semiconductor-based intralamellar part；Second dielectric layer is formed on the first medium layer and makes described second to be situated between
Matter layer extends in the first grid contact hole bottom for covering the first grid contact hole；In the second dielectric layer
Upper formation first grid metal layer simultaneously extends to the first grid metal layer in the first grid contact hole to cover position
The second dielectric layer in first grid contact hole bottom；Etch the first grid metal layer, the second medium
Layer, the first medium layer and the semiconductor substrate are to form second grid contact hole, wherein the second grid contact hole
It is connected with the first grid contact hole, the second grid contact hole runs through the first grid metal layer, described second
Dielectric layer and the first medium layer and protrude into the semiconductor-based intralamellar part；Third is formed on the first grid metal layer
Dielectric layer simultaneously extends to the third dielectric layer in the second grid contact hole to cover the second grid contact hole
It bottom and is connect with the second dielectric layer；Second grid metal layer is formed on the third dielectric layer and makes described second
Gate metal layer extends in the second grid contact hole to cover be located at second grid contact hole bottom described the
It three dielectric layers and is connect with the first grid metal layer；Etch the second grid metal layer, the third dielectric layer, described
First grid metal layer, the second dielectric layer and the first medium layer are to form the first source drain contact hole；Described in etching
First grid metal layer, the second dielectric layer and the first medium layer are to form the second source drain contact hole；Described
Ohmic contact metal layer is formed in one gate metal layer and the second grid metal layer and fills out the ohmic contact metal layer
Be charged to the first grid contact hole, the second grid contact hole, first source drain contact hole and second source/
Drain contact hole；The ohmic contact metal layer, the first grid metal layer and the second grid metal layer are etched with shape
At the grid of the correspondence first grid contact hole and the second grid contact hole, corresponding first source drain contact hole
The first source/drain and corresponding second source drain contact hole the second source/drain, so that the semiconductor devices be made.
In embodiments of the present invention, it is optimized by the structure to semiconductor devices, obtains a kind of double gate metal knot
The semiconductor devices of structure can obtain better devices switch characteristic.
Detailed description of the invention
Fig. 1 is the partial profile structure of the active region of semiconductor devices in one embodiment of the invention.
Fig. 2A is the obtained device active region of step 1 of the production method of semiconductor devices in one embodiment of the invention
The partial profile structure in domain.
Fig. 2 B is the obtained device active region of step 2 of the production method of semiconductor devices in one embodiment of the invention
The partial profile structure in domain.
Fig. 2 C is the obtained device active region of step 3 of the production method of semiconductor devices in one embodiment of the invention
The partial profile structure in domain.
Fig. 2 D is the obtained device active region of step 4 of the production method of semiconductor devices in one embodiment of the invention
The partial profile structure in domain.
Fig. 2 E is the obtained device active region of step 5 of the production method of semiconductor devices in one embodiment of the invention
The partial profile structure in domain.
Fig. 2 F is the obtained device active region of step 6 of the production method of semiconductor devices in one embodiment of the invention
The partial profile structure in domain.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
As shown in Figure 1, a kind of semiconductor devices 100 that one embodiment of the present of invention provides, comprising: semiconductor substrate
110, dielectric layer 120a, dielectric layer 120b, dielectric layer 120c, gate metal layer 130a, gate metal layer 130b, source electrode 140, leakage
Pole 150 and grid 160.
Wherein, dielectric layer 120a is set on semiconductor substrate 110.
Dielectric layer 120b is set on dielectric layer 120a, and is extended in the GH1 of gate contact hole to cover grid contact hole
The bottom of GH1, gate contact hole GH1 is through dielectric layer 120a and protrudes into inside semiconductor substrate 110.
Gate metal layer 130a is set on dielectric layer 120b, and is extended in the GH1 of gate contact hole and be located at grid with covering
The dielectric layer 120b of the pole bottom contact hole GH1.
Dielectric layer 120c is set on gate metal layer 130a, and is extended in the GH2 of gate contact hole and connect with covering grid
The bottom of contact hole GH2 is simultaneously connect with the dielectric layer 120b for being located at the gate contact hole bottom GH1, and gate contact hole GH2 is sequentially passed through
It gate metal layer 130a, dielectric layer 120b and dielectric layer 120a and protrudes into inside semiconductor substrate 110.
Gate metal layer 130b is set on dielectric layer 120c, and is extended in the GH2 of gate contact hole and be located at grid with covering
The dielectric layer 120c of the pole bottom contact hole GH2 is simultaneously connect with the gate metal layer 120a for being located at the gate contact hole bottom GH1.
Source electrode 140 is set on gate metal layer 130b, and fills source contact openings SH, and source contact openings SH is sequentially passed through
Gate metal layer 130b, dielectric layer 120c, gate metal layer 130a, dielectric layer 120b and dielectric layer 120a.
Drain electrode 150 is set on gate metal layer 130a, and fills drain contact hole DH, and drain contact hole DH is sequentially passed through
Gate metal layer 130a, dielectric layer 120b and dielectric layer 120a.
Grid 160 is set on gate metal layer 130a and gate metal layer 130b, and fills gate contact hole GH1 and grid
Pole contact hole GH2, gate contact hole GH1 are connected with gate contact hole GH2.Preferably, the width and grid of gate contact hole GH1
The ratio of the width of pole contact hole GH2 is 1:1, it is, of course, also possible to be other suitable ratio values, such as 1:2,1:3,2:1 etc.
Deng.Certainly, the embodiment of the present invention is not limited thereto system, in some other embodiment, gate contact hole GH1 and gate contact
Hole GH2, which can also be, is spaced apart from each other setting.
Gate contact hole GH1 and gate contact hole GH2 are for example respectively protruding into aluminum gallium nitride layer 115.
Specifically, gate metal layer 130a is for example made of the first metal M1, and gate metal layer 130b is for example by the second gold medal
Belong to M2 composition, the work function of the first metal M1 is not identical as the work function of the second metal M2.Preferably, the work content of the first metal M1
Number is lower than the work function of the second metal M2.
First metal M1 is, for example, aluminum metal or nickel metal, and the second metal M2 is, for example, cobalt metal or molybdenum.Certainly, originally
Inventive embodiments are not limited thereto, as long as can satisfy work function of the work function lower than the second metal M2 of the first metal M1
Condition.
Specifically, semiconductor substrate 110 for example, silicon substrate 111, and it is set to the nitridation on 111 surface of silicon substrate
Gallium buffer layer 113 and the aluminum gallium nitride layer 115 for being set to 113 surface of nitride buffer layer.
Silicon substrate 111 is, for example, P (111) type silicon substrate.
Two-dimensional electron gas channel (2DEG) 117 is for example formed between nitride buffer layer 113 and aluminum gallium nitride layer 115.
The thickness of nitride buffer layer 113 is greater than 3 microns.
Specifically, source electrode 140, drain electrode 150 and/or grid 160 are for example made of metal ohmic contact, the Ohmic contact
Metal for example successively includes: the first titanium coating, aluminum metal layer, the second titanium coating and titanium nitride layer from bottom to up.Wherein, institute
The ingredient for stating the first titanium coating and second titanium coating is titanium (Ti), and the ingredient of the aluminum metal layer is aluminium (Al), institute
The ingredient for stating titanium nitride layer is titanium nitride (TiN).
The material of dielectric layer 120a, 120b, 120c are, for example, silicon nitride.Herein it is noted that dielectric layer 120a,
The material of 120b, 120c for example can also be the material that the dielectric layer of semiconductor devices 100 is suitable as known to other, such as
The high-k such as silica, silica or hafnium oxide (high dielectric) material.
In addition, the embodiment of the present invention also provides the production method of above-mentioned semiconductor device 100.As shown in Fig. 2A to 2F, it is
The partial structurtes diagrammatic cross-section in obtained device active region domain in each step of the production method of semiconductor devices 100.
Specifically, the production method of semiconductor devices 100 specifically includes that
Step 1: as shown in Figure 2 A, after being cleaned to semiconductor substrate 110, LPCVD (Low Pressure
Chemical Vapor Deposition, low-pressure chemical vapor deposition) one layer of dielectric layer 120a of deposition, for being passivated semiconductor
110 surface of substrate, eliminates its surface state, to improve the reliability of finally formed semiconductor devices 100.
Step 2: as shown in Figure 2 B, preparing gate contact hole GH1.The corresponding grid of lithographic definition gate contact hole GH1 connects
Then contact hole region GHZ1 uses sulfur fluoride (SF6) and chlorine (Cl2) be gas source ICP (Inductively Coupled
Plasma, plasma inductive coupling) lithographic method etching grid contact hole GH1, etch away formed in step 1 be located at grid
Pole contacts the aluminum gallium nitride layer 115 of whole dielectric layer 120a and segment thickness of bore region GHZ1.Wherein, the program bag of photoetching
Gluing, exposure and imaging are included.Gate contact hole GH1 is through dielectric layer 120a and extends into inside semiconductor substrate 110.
Step 3: as shown in Figure 2 C, then being sequentially depositing one layer of dielectric layer 120b and one layer of gate metal layer 130a.
Step 4: as shown in Figure 2 D, preparing gate contact hole GH2.The corresponding grid of lithographic definition gate contact hole GH2 connects
Then contact hole region GHZ2 uses sulfur fluoride and chlorine for the ICP lithographic method etching grid contact hole GH2 of gas source, etching
Fall the gate metal layer 130a of the whole positioned at gate contact bore region GHZ2, the nitrogen of dielectric layer 120a, 120b and segment thickness
Change gallium aluminium layer 115.
Step 5: as shown in Figure 2 E, being sequentially depositing one layer of dielectric layer 120c and gate metal layer 130b.
Step 6: as shown in Figure 2 F, source contact openings SH and drain contact hole DH preparation.Lithographic definition source contact porose area
After domain SHZ and drain contact bore region DHZ, sulfur fluoride is used to etch away for the ICP lithographic method of gas source positioned at source contact
Gate metal layer 130b, dielectric layer 120c, gate metal layer 130a, dielectric layer 120b and the dielectric layer 120a of bore region SHZ, with
And gate metal layer 130a, dielectric layer 120b and dielectric layer 120a positioned at drain contact bore region DHZ, to form source contact
Hole SH and drain contact hole DH guarantees that etching stopping in aluminum gallium nitride layer 115, avoids causing larger damage to aluminum gallium nitride layer 115
Wound, so that there are sufficient concentrations of electronics in 117 channel of Two-dimensional electron gas channel, maintains the large current characteristic of device.
Step 7: as shown in Figure 1, PVD (Physical Vapor Deposition, physical vapour deposition (PVD)) deposit ohmic connects
Metal is touched, specifically, on the upper surface (upper surface in Fig. 1) of the structure obtained in step 6 namely gate metal layer 130a
Ohmic contact metal layer is formed with deposit ohmic contact metal on the surface of gate metal layer 130b and makes the Ohmic contact gold
Belong to layer to fill to gate contact hole GH1, gate contact hole GH2, source contact openings SH and drain contact hole DH；Then pass through photoetching
Define source metal electrode region SZ, drain metal electrode region DZ and gate metal electrode region GZ；Step 7 is etched away later
And what is deposited respectively in step 5 is located at source metal electrode region SZ, drain metal electrode region DZ and gate metal electrode
Region GZ whole metal ohmic contacts and gate metal layer 130a, 130b between region two-by-two, finally obtain as shown in Figure 1
Source electrode 140, drain electrode 150 and grid 160.Wherein, the metal ohmic contact for example successively includes: the first titanium from bottom to up
Belong to layer, aluminum metal layer, the second titanium coating and titanium nitride layer.Wherein, first titanium coating and second titanium coating
Ingredient be titanium (Ti), the ingredient of the aluminum metal layer is aluminium (Al), and the ingredient of the titanium nitride layer is titanium nitride (TiN),
When depositing the metal ohmic contact, it is sequentially depositing the first titanium coating, aluminum metal layer, the second titanium coating and titanium nitride layer,
And first titanium coating, the aluminum metal layer, second titanium coating and the titanium nitride layer deposition thickness for example
Respectively 200 angstroms, 1200 angstroms, 200 angstroms and 200 angstroms.
The metal ohmic contact deposition, to keep Ohmic contact good, needs to make each connect by the way of magnetron sputtering
Contact hole namely gate contact hole GH1, gate contact hole GH2, source contact openings SH and drain contact hole DH clean few impurity, because
This, step 7 for example can also include removal step, specifically, for example (,) it is clear in the preceding hydrofluoric acid (HF) of metal ohmic contact deposition
Each contact hole is washed, it will be in nitrogen (N after the metal ohmic contact deposition2) short annealings of 850 DEG C, 45s is carried out under environment
(RTS)。
Further, before step 1, it such as further comprises the steps of: and to form semiconductor substrate 110.Specifically, in silicon substrate
Be sequentially depositing nitride buffer layer 113 and aluminum gallium nitride layer 115 on 111, nitride buffer layer 113 and aluminum gallium nitride layer 115 it
Between formed Two-dimensional electron gas channel 117, ultimately form semiconductor substrate 110.Gallium nitride is third generation semiconductor material with wide forbidden band,
With the characteristics such as big forbidden bandwidth, high electron saturation velocities, high breakdown electric field, higher heat-conductivity, corrosion-resistant and radiation resistance,
And there is stronger advantage under high pressure, high frequency, high temperature, high-power and Flouride-resistani acid phesphatase environmental condition, to be research short wavelength light
The optimal material of electronic device and high voltagehigh frequency rate high power device；Wherein, big forbidden bandwidth is 3.4 electron-volts, high electronics
Saturation rate is 2e7 centimeters per second, and high breakdown electric field is 1e10~-3e10 volts per cm.
By the above process, the semiconductor devices 100 of a complete dual gate metal structure completes.So it is not limited to
This also changes in other embodiments or increases other steps, to complete semiconductor devices 100.
In addition, it is noted that above-mentioned source electrode and drain electrode can be interchanged, so that one of source electrode and drain electrode can claim
Be the first source/drain, the another of source electrode and drain electrode can be referred to as the second source/drain；Correspondingly, above-mentioned source contact openings and
One of drain contact hole can be referred to as the first source drain contact hole, and above-mentioned source contact openings and the another of drain contact hole can
To be referred to as the second source drain contact hole.
In conclusion the embodiment of the present invention is optimized by the structure to semiconductor devices, a kind of bigrid gold is obtained
The semiconductor devices 100 for belonging to structure, can obtain better devices switch characteristic；In addition, work used in the embodiment of the present invention
Skill and condition can be, strong operability compatible with CMOS technology, coordinated well device performance and process complexity it
Between contradiction.Therefore, the semiconductor devices 100 of dual gate metal structure and preparation method thereof that the embodiment of the present invention is proposed is
The design of enhanced semiconductor device high reliability, volume production scheme, which provides, to be used for reference well and refers to, and semiconductor devices 100 can
Applied in the technical fields such as power electronic element, filter, radio communication element, have a good application prospect.
In several embodiments provided herein, it should be understood that disclosed system, device and/or method, it can
To realize by another way.For example, the apparatus embodiments described above are merely exemplary, for example, the unit/
The division of module, only a kind of logical function partition, there may be another division manner in actual implementation, such as multichannel unit
Or module can be combined or can be integrated into another system, or some features can be ignored or not executed.Another point, institute
Display or the mutual coupling, direct-coupling or communication connection discussed can be through some interfaces, device or unit
Indirect coupling or communication connection can be electrical property, mechanical or other forms.
The units/modules as illustrated by the separation member may or may not be physically separated, as
The component that units/modules are shown may or may not be physical unit, it can and it is in one place, or can also be with
It is distributed on multi-channel network unit.Some or all of units/modules therein can be selected to realize according to the actual needs
The purpose of this embodiment scheme.
Finally, it should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
Present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: it still may be used
To modify the technical solutions described in the foregoing embodiments or equivalent replacement of some of the technical features；
And these are modified or replaceed, technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution spirit and
Range.
Claims (10)
1. a kind of semiconductor devices characterized by comprising
Semiconductor substrate；
First medium layer is set on the semiconductor substrate；
Second dielectric layer is set on the first medium layer and extends in first grid contact hole to cover described first
The bottom in gate contact hole, the first grid contact hole is through the first medium layer and protrudes into the semiconductor substrate
Portion；
First grid metal layer is set in the second dielectric layer and extends in the first grid contact hole with covering
The second dielectric layer positioned at first grid contact hole bottom；
Third dielectric layer is set on the first grid metal layer and extends in second grid contact hole described in covering
The bottom of second grid contact hole, the second grid contact hole sequentially pass through the first grid metal layer, second Jie
Matter layer and the first medium layer and protrude into the semiconductor-based intralamellar part；
Second grid metal layer is set on the third dielectric layer and extends in the second grid contact hole with covering
The third dielectric layer positioned at second grid contact hole bottom；
First source/drain, is set on the second grid metal layer and fills the first source drain contact hole, and described first
Source drain contact hole sequentially passes through the second grid metal layer, the third dielectric layer, the first grid metal layer, institute
State second dielectric layer and the first medium layer；
Second source/drain, is set on the first grid metal layer and fills the second source drain contact hole, and described second
Source drain contact hole sequentially passes through the first grid metal layer, the second dielectric layer and the first medium layer；And
Grid, is set on the first grid metal layer and the second grid metal layer and fills the first grid and connect
Contact hole and the second grid contact hole.
2. semiconductor devices as described in claim 1, which is characterized in that the first grid metal layer is by the first metal group
At the second grid metal layer is made of the second metal, and the work function of first metal is lower than the bimetallic function
Function；The first grid contact hole is connected with the second grid contact hole.
3. semiconductor devices as claimed in claim 2, which is characterized in that first metal is aluminum metal or nickel metal, institute
Stating the second metal is cobalt metal or molybdenum.
4. semiconductor devices as described in claim 1, which is characterized in that the semiconductor substrate includes: silicon substrate, Yi Jishe
It is placed in the nitride buffer layer of the surface of silicon and is set to the aluminum gallium nitride layer on the nitride buffer layer surface.
5. semiconductor devices as claimed in claim 4, which is characterized in that the first grid contact hole and the second grid
Contact hole is respectively protruding into the aluminum gallium nitride layer.
6. semiconductor devices as described in claim 1, which is characterized in that the width of the first grid contact hole and described the
The ratio of the width in two gate contact holes is 1:1.
7. semiconductor devices as claimed in claim 4, which is characterized in that the nitride buffer layer and the aluminum gallium nitride layer
Between be formed with Two-dimensional electron gas channel.
8. semiconductor devices as described in claim 1, which is characterized in that first source/drain, second source/drain,
And/or the grid is made of metal ohmic contact, the metal ohmic contact successively includes: the first titanium from bottom to up
Layer, aluminum metal layer, the second titanium coating and titanium nitride layer.
9. a kind of semiconductor devices characterized by comprising
Semiconductor substrate is formed with Two-dimensional electron gas channel in the semiconductor substrate；
First medium layer is set on the semiconductor substrate；
Second dielectric layer is set on the first medium layer and extends in first grid contact hole to cover described first
The bottom in gate contact hole, the first grid contact hole is through the first medium layer and protrudes into the semiconductor substrate
Portion；
First grid metal layer is set in the second dielectric layer and extends in the first grid contact hole with covering
The second dielectric layer positioned at first grid contact hole bottom；
Third dielectric layer is set on the first grid metal layer and extends in second grid contact hole described in covering
The bottom of second grid contact hole is simultaneously connect with the second dielectric layer for being located at first grid contact hole bottom, described
Second grid contact hole is through the first grid metal layer, the second dielectric layer and the first medium layer and protrudes into described
Semiconductor-based intralamellar part；
Second grid metal layer is set on the third dielectric layer and extends in the second grid contact hole with covering
Positioned at second grid contact hole bottom the third dielectric layer and be located at first grid contact hole bottom institute
State the connection of first grid metal layer；
First source/drain, is set on the second grid metal layer and fills the first source drain contact hole, and described first
Source drain contact hole is through the second grid metal layer, the third dielectric layer, the first grid metal layer, described the
Second medium layer and the first medium layer；
Second source/drain, is set on the first grid metal layer and fills the second source drain contact hole, and described second
The first grid metal layer, the second dielectric layer and the first medium layer are run through in source drain contact hole；And
Grid, is set on the first grid metal layer and the second grid metal layer and fills the first grid and connect
Contact hole and the second grid contact hole, the first grid contact hole are connected with the second grid contact hole；
Wherein, the first grid metal layer is made of the first metal, and the second grid metal layer is made of the second metal, institute
The work function for stating the first metal is different from the bimetallic work function.
10. a kind of production method of semiconductor devices, which is characterized in that comprising steps of
First medium layer is formed on a semiconductor substrate, wherein being formed with Two-dimensional electron gas channel in the semiconductor substrate；
The first medium layer and the semiconductor substrate are etched to form first grid contact hole, wherein the first grid connects
Contact hole is through the first medium layer and protrudes into the semiconductor-based intralamellar part；
Second dielectric layer is formed on the first medium layer and the second dielectric layer is made to extend to the first grid contact
The bottom of the first grid contact hole is covered in hole；
First grid metal layer is formed in the second dielectric layer and the first grid metal layer is made to extend to described first
To cover the second dielectric layer for being located at first grid contact hole bottom in gate contact hole；
The first grid metal layer, the second dielectric layer, the first medium layer and the semiconductor substrate are etched with shape
At second grid contact hole, wherein the second grid contact hole is connected with the first grid contact hole, the second gate
Pole contact hole is through the first grid metal layer, the second dielectric layer and the first medium layer and protrudes into the semiconductor
Inside substrate；
Third dielectric layer is formed on the first grid metal layer and the third dielectric layer is made to extend to the second grid
To cover the bottom of the second grid contact hole and be connect with the second dielectric layer in contact hole；
Second grid metal layer is formed on the third dielectric layer and the second grid metal layer is made to extend to described second
In gate contact hole with cover be located at second grid contact hole bottom the third dielectric layer and with the first grid
Metal layer connection；
Etch the second grid metal layer, the third dielectric layer, the first grid metal layer, the second dielectric layer and
The first medium layer is to form the first source drain contact hole；
The first grid metal layer, the second dielectric layer and the first medium layer is etched to connect to form the second source/drain
Contact hole；
Ohmic contact metal layer is formed on the first grid metal layer and the second grid metal layer and makes described ohm
Contact metal layer fill to the first grid contact hole, the second grid contact hole, first source drain contact hole and
Second source drain contact hole；
The ohmic contact metal layer, the first grid metal layer and the second grid metal layer are etched to form corresponding institute
State the grid of first grid contact hole and the second grid contact hole, corresponding first source drain contact hole the first source/
Second source/drain of drain electrode and corresponding second source drain contact hole, so that the semiconductor devices be made.
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| CN201810802979.2A CN109037329A (en) | 2018-07-20 | 2018-07-20 | Semiconductor devices and preparation method thereof |
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| CN112397577A (en) * | 2019-08-14 | 2021-02-23 | 长鑫存储技术有限公司 | Semiconductor device structure and manufacturing method thereof |
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| CN112397577A (en) * | 2019-08-14 | 2021-02-23 | 长鑫存储技术有限公司 | Semiconductor device structure and manufacturing method thereof |
| CN112397577B (en) * | 2019-08-14 | 2024-05-03 | 长鑫存储技术有限公司 | Semiconductor device structure and manufacturing method thereof |
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