CN109524461A - Semiconductor devices and preparation method thereof - Google Patents
Semiconductor devices and preparation method thereof Download PDFInfo
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- CN109524461A CN109524461A CN201811124144.2A CN201811124144A CN109524461A CN 109524461 A CN109524461 A CN 109524461A CN 201811124144 A CN201811124144 A CN 201811124144A CN 109524461 A CN109524461 A CN 109524461A
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- grid
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 92
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 229910052751 metal Inorganic materials 0.000 claims description 59
- 239000002184 metal Substances 0.000 claims description 59
- 230000004888 barrier function Effects 0.000 claims description 31
- 229910002601 GaN Inorganic materials 0.000 claims description 22
- 239000010936 titanium Substances 0.000 claims description 20
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 18
- 229910052719 titanium Inorganic materials 0.000 claims description 18
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 14
- 239000011248 coating agent Substances 0.000 claims description 14
- 238000000576 coating method Methods 0.000 claims description 14
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 230000005533 two-dimensional electron gas Effects 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 10
- 238000000151 deposition Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 7
- 239000004615 ingredient Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000002708 enhancing effect Effects 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- 238000009616 inductively coupled plasma Methods 0.000 description 3
- 238000005036 potential barrier Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- -1 aluminium gold Chemical compound 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The present invention relates to technical field of semiconductors, a kind of semiconductor devices and preparation method thereof is provided.The semiconductor devices includes: semiconductor substrate；Dielectric layer is arranged on the semiconductor substrate；Source electrode and drain electrode is arranged on the dielectric layer；And first grid and second grid, it is spaced apart from each other and is arranged on the dielectric layer；Wherein, between the source electrode and the drain electrode, the source electrode, the drain electrode, the first grid and the second grid extend through the dielectric layer and protrude into the semiconductor substrate to form Schottky contacts with the semiconductor substrate for the first grid and the second grid.Grid control ability can be improved in semiconductor devices of the invention, reduces electric leakage of the grid and OFF state electric leakage, can be realized the Schottky contacts and low drain leakage current of high quality.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of semiconductor devices and a kind of systems of semiconductor devices
Make method.
Background technique
AlGaN (aluminum gallium nitride)/GaN (gallium nitride) HEMT (High Electron Mobility Transistor,
High electron mobility transistor) there is the semiconductor devices such as device excellent characteristics and extensive use to have had several so far
For kind technology for manufacturing enhanced semiconductor device, all these technologies empty grating of semiconductor element using different technologies
Two-dimensional electron gas (2DEG) channel (under zero grid bias) of lower section, this is the normally off necessary to operation.In order to realize this
Target has developed enhanced GaN (gallium nitride) transistor of various technologies.However, it is difficult to be improved using these methods
Low subthreshold value is swung and the uniformity of off-state current and the good Sub-Threshold Characteristic of AlGaN (aluminum gallium nitride) potential barrier thickness.
It is, therefore, desirable to provide a kind of semiconductor devices and preparation method thereof for being able to solve problem above.
Summary of the invention
To solve the above problems, the embodiment of the present invention provides a kind of semiconductor devices and preparation method thereof, grid can be improved
Pole control ability reduces electric leakage of the grid and OFF state electric leakage, and Schottky contacts and the low drain leakage that can be realized high quality are electric
Stream.
Specifically, a kind of semiconductor devices provided in an embodiment of the present invention, comprising: semiconductor substrate；Dielectric layer, setting exist
On the semiconductor substrate；Source electrode and drain electrode is arranged on the dielectric layer；And first grid and second grid, each other
Every setting on the dielectric layer；Wherein, the first grid and the second grid are located at the source electrode and the drain electrode
Between, the source electrode, the drain electrode, the first grid and the second grid extend through the dielectric layer and protrude into described
Semiconductor substrate is to form Schottky contacts with the semiconductor substrate.
The present invention in one embodiment, the semiconductor substrate includes: silicon substrate, and is set to silicon lining
The nitride buffer layer of bottom surface and the aluminum gallium nitride layer for being set to the nitride buffer layer surface；Wherein, the gallium nitride
Two-dimensional electron gas channel can be formed between buffer layer and the aluminum gallium nitride layer；The source electrode, the drain electrode, the first grid
Protrude into the aluminum gallium nitride layer with the second grid to form Schottky contacts with the aluminum gallium nitride layer.
The present invention in one embodiment, the source electrode and the drain electrode are made of metal ohmic contact, described the
One grid and the second grid are made of the gate metal set gradually from bottom to up and the metal ohmic contact；Wherein,
The metal ohmic contact includes the first titanium coating set gradually from bottom to up, aluminum metal layer, the second titanium coating and
Titanium nitride layer, the material of the gate metal are titanium nitride.
The present invention in one embodiment, the material of the dielectric layer is silicon nitride, silica or hafnium oxide.
The present invention in one embodiment, the width of the bottom of the first grid is less than the bottom of the second grid
The width in portion.
The present invention in one embodiment, the width of the bottom of the first grid is the bottom of the second grid
Width half.
The present invention in one embodiment, the semiconductor devices includes double-gate structure high electron mobility crystal
Pipe, and the double-gate structure high electron mobility transistor has the source electrode, the drain electrode, the first grid and described the
Two grids.
On the other hand, a kind of semiconductor devices provided in an embodiment of the present invention, comprising: semiconductor substrate, comprising: silicon lining
Bottom, and be set to the buffer layer of the surface of silicon and be set to the barrier layer of the buffer-layer surface, the buffer layer
Two-dimensional electron gas channel can be formed between the barrier layer；Dielectric layer is arranged on the semiconductor substrate, wherein source electrode
Contact hole, drain contact hole, first grid contact hole and second grid contact hole run through the dielectric layer and protrude into the gesture
Barrier layer；And source electrode, drain electrode, first grid and second grid, it is arranged on the dielectric layer and fills the source electrode respectively and connect
Contact hole, the drain contact hole, the first grid contact hole and the second grid contact hole with the barrier layer to form
Schottky contacts；Wherein, the first grid contact hole and the second grid contact hole are located at the source contact openings and institute
It states between drain contact hole, the width of the first grid contact hole is less than the width of the second grid contact hole.
The present invention in one embodiment, the first grid contact hole is arranged adjacent to the source contact openings, institute
Second grid contact hole is stated to be arranged adjacent to the drain contact hole；The semiconductor devices includes double-gate structure high electron mobility
Transistor, and the double-gate structure high electron mobility transistor has the source electrode, the drain electrode, the first grid and institute
State second grid.
Another aspect, a kind of production method of semiconductor devices provided in an embodiment of the present invention, comprising steps of in semiconductor
Dielectric layer is formed on substrate, wherein the semiconductor substrate includes: semiconductor substrate, and is successively set on the semiconductor
Buffer layer and barrier layer on substrate；The dielectric layer and the barrier layer are etched, to form first grid contact hole and second
Gate contact hole, wherein the first grid contact hole and the second grid contact hole run through the dielectric layer and protrude into
The barrier layer；Gate metal layer is formed on the dielectric layer and the gate metal layer is made to extend to the first grid
It is connect in contact hole and in the second grid contact hole with the bottom for covering the first grid contact hole and the second grid
The bottom of contact hole；The gate metal layer is etched, described in removing other than first grid region and second grid region
Gate metal layer, wherein the first grid contact hole and the second grid contact hole are located at the first grid polar region
Domain and the second grid region；The dielectric layer and the barrier layer are etched, to form source contact openings and drain contact hole,
Wherein, the source contact openings and the drain contact hole run through the dielectric layer and protrude into the aluminum gallium nitride layer；Institute
It states and forms ohmic contact metal layer on gate metal layer and the dielectric layer and fill the ohmic contact metal layer to described
Source contact openings, the drain contact hole, the first grid contact hole and the second grid contact hole；And described in etching
Ohmic contact metal layer is located at source region, drain region, the first grid region and the second grid region with removal
The ohmic contact metal layer in addition, to form the source electrode of the corresponding source contact openings, the corresponding drain contact hole
Drain electrode, the first grid of the corresponding first grid contact hole and the second grid of the corresponding second grid contact hole,
In, the source contact openings and the drain contact hole are located at the source region and the drain region.
In embodiments of the present invention, it is redesigned by structure to semiconductor devices, such as by double gate structures application
In enhancing/depletion-mode AlGaN/GaN HEMT design, grid control ability can be improved, reduce electric leakage of the grid and OFF state leakage
Electricity realizes the Schottky contacts and low drain leakage current of high quality, improves drain leakage effect caused by grid, Neng Gouyou
Effect improves the uniformity of good Sub-Threshold Characteristic and AlGaN potential barrier thickness, keeps the barrier layer below grid thinning to realize enhancing
Operation increases gate leakage and reduces breakdown voltage.
Detailed description of the invention
Fig. 1 is the partial profile structure of the active region of semiconductor devices in one embodiment of the invention.
Fig. 2A is the obtained device active region of step 1 of the production method of semiconductor devices in one embodiment of the invention
The partial profile structure in domain.
Fig. 2 B is the obtained device active region of step 2 of the production method of semiconductor devices in one embodiment of the invention
The partial profile structure in domain.
Fig. 2 C is the obtained device active region of step 3 of the production method of semiconductor devices in one embodiment of the invention
The partial profile structure in domain.
Fig. 2 D is the obtained device active region of step 4 of the production method of semiconductor devices in one embodiment of the invention
The partial profile structure in domain.
Fig. 2 E is the obtained device active region of step 5 of the production method of semiconductor devices in one embodiment of the invention
The partial profile structure in domain.
Fig. 2 F is the obtained device active region of step 6 of the production method of semiconductor devices in one embodiment of the invention
The partial profile structure in domain.
Fig. 2 G is the obtained device active region of step 7 of the production method of semiconductor devices in one embodiment of the invention
The partial profile structure in domain.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
As shown in Figure 1, a kind of semiconductor devices 100 that one embodiment of the present of invention provides, comprising: semiconductor substrate
110, dielectric layer 120, source electrode 140, drain electrode 150, first grid 160a and second grid 160b.
Wherein, dielectric layer 120 is for example set on semiconductor substrate 110；Source electrode 140, drain electrode 150, first grid 160a
It is for example spaced apart from each other and is set on dielectric layer 120 with second grid 160b.For example, the semiconductor devices 100 of the present embodiment
For example including the double-gate structure high electron mobility transistor (HEMT) based on gallium nitride, and the double grid knot based on gallium nitride
Structure high electron mobility transistor (HEMT) has source electrode 140, drain electrode 150, first grid 160a and second grid 160b.
Wherein, first grid 160a and second grid 160b for example positioned at source electrode 140 and drain electrode 150 between, source electrode 140,
Drain electrode 150, first grid 160a and second grid 160b extend through dielectric layer 120 and protrude into inside semiconductor substrate 110 with
Schottky contacts are formed with semiconductor substrate 110.
Specifically, semiconductor substrate 110 for example, such as silicon substrate of semiconductor substrate 111, and it is set to semiconductor
Such as nitride buffer layer of buffer layer 113 on 111 surface of substrate and such as nitrogen of barrier layer 115 for being set to 113 surface of buffer layer
Change gallium aluminium layer.
Semiconductor substrate 111 is, for example, P (111) type silicon substrate.
The thickness of buffer layer 113 is greater than 3 microns.
Two-dimensional electron gas channel (2DEG) 117 can be for example formed between buffer layer 113 and barrier layer 115.
Source electrode 140, drain electrode 150, first grid 160a and second grid 160b for example protrude into inside barrier layer 115 with
Barrier layer 115 forms Schottky contacts.But source electrode 140, drain electrode 150, first grid 160a and second grid 160b do not run through
Barrier layer 115.
Specifically, source electrode 140 and drain electrode 150 are for example made of metal ohmic contact, first grid 160a and second grid
160b is for example made of the gate metal and the metal ohmic contact that set gradually from bottom to up.Wherein, the gate metal
Material be titanium nitride (TiN), the thickness of the gate metal included by first grid 160a and second grid 160b is for example
It is 200 nanometers, the metal ohmic contact for example successively includes: the first titanium coating, aluminum metal layer, the second titanium from bottom to up
Belong to layer and titanium nitride layer.Wherein, the ingredient of first titanium coating and second titanium coating is titanium (Ti), the aluminium gold
The ingredient for belonging to layer is aluminium (Al), and the ingredient of the titanium nitride layer is titanium nitride (TiN).
The material of dielectric layer 120 is, for example, silicon nitride (Si3N4).Herein it is noted that the material example of dielectric layer 120
The material of the dielectric layer 120 of semiconductor devices 100, such as silica, hafnium oxide are suitable as known to can also be other
Equal high-k (Gao Jie electricity) material.
The width L1 of the bottom of first grid 160a is, for example, less than the width L2 of the bottom of second grid 160b.
Further, the width L1 of the bottom of first grid 160a is, for example, the width L2 of the bottom of second grid 160b
Half.Certainly, the ratio of L1 and L2 for example can also be other suitable numerical value.
First grid 160a is for example arranged adjacent to source electrode 140, and second grid 160b such as adjacent drains 150 are arranged.That is,
First grid 160a is arranged between source electrode 140 and second grid 160b, and second grid 160b, which for example be arranged, is draining 150 and the
Between one grid 160a.
In addition, the embodiment of the present invention also provides the production method of above-mentioned semiconductor device 100.As shown in Fig. 2A to 2G, it is
The partial structurtes diagrammatic cross-section in obtained device active region domain in each step of the production method of semiconductor devices 100.
Specifically, the production method of the semiconductor devices 100 specifically includes that
Step 1: as shown in Figure 2 A, dielectric layer 120 is formed on semiconductor substrate 110.Specifically, to semiconductor substrate
It, can be for example using LPCVD (Low Pressure Chemical Vapor Deposition, low pressure chemical after 110 are cleaned
Vapor deposition) one layer of 120 (for example, Si of dielectric layer of deposition3N4, silicon nitride), for being passivated 110 surface of semiconductor substrate, eliminate
Its surface state, to improve the reliability of finally formed semiconductor devices 100.
Step 2: as shown in Figure 2 B, etching media layer 120 and barrier layer 115 are to form first grid contact hole GH1 and the
Two gate contact hole GH2.Specifically, the corresponding gate contact bore region GHZ1 of lithographic definition first grid contact hole GH1 and
The corresponding gate contact bore region GHZ2 of two gate contact hole GH2, then for example, by using sulfur fluoride (SF6) and chlorine (Cl2) it is gas
ICP (Inductively Coupled Plasma, the plasma inductive coupling) lithographic method in body source etches away in step 1
What is formed is located at whole dielectric layers 120 and portion of first grid contact bore region GHZ1 and second grid contact bore region GHZ2
Divide the barrier layer 115 of thickness, to form first grid contact hole GH1 and second grid contact hole GH2.Wherein, the program of photoetching
It include gluing, exposure and imaging.Wherein, first grid contact hole GH1 and second grid contact hole GH2 run through dielectric layer
120 and protrude into barrier layer 115.
Step 3: as shown in Figure 2 C, forming gate metal layer 130 on dielectric layer 120 and extend gate metal layer 140
The bottom and second of first grid contact hole GH1 is covered in first grid contact hole GH1 and in second grid contact hole GH2
The bottom of gate contact hole GH2.Specifically, one layer of gate metal, such as titanium nitride (TiN) are deposited, on dielectric layer 120 with shape
At the gate metal layer 130 of semiconductor devices 100.
Step 4: as shown in Figure 2 D, etching gate metal layer 130 to remove and be located at first grid region GZ1 and second grid
Gate metal layer 130 other than the GZ2 of region, wherein first grid contact hole GH1 and second grid contact hole GH2 for example distinguish
Positioned at first grid region GZ1 and second grid region GZ2.
Step 5: as shown in Figure 2 E, etching media layer 120 and barrier layer 115 are to form source contact openings SH and drain contact
Hole DH.Specifically, after lithographic definition source contact bore region SHZ and drain contact bore region DHZ, use sulfur fluoride for gas source
ICP lithographic method etch away whole media positioned at source contact bore region SHZ and under drain contact bore region DHZ
The barrier layer 115 of layer 120 and segment thickness is to form source contact openings SH and drain contact hole DH.Wherein, source contact openings SH
Run through dielectric layer 120 with drain contact hole DH and protrudes into barrier layer 115.
Step 6: as shown in Figure 2 F, ohmic contact metal layer 170, simultaneously is formed in gate metal layer 130 and dielectric layer 120
Make the filling of ohmic contact metal layer 170 to source contact openings SH, drain contact hole DH, first grid contact hole GH1 and second gate
Pole contact hole GH2.Specifically, exposed gate metal layer 130 and dielectric layer on the surface of the obtained device of step 5
PVD (Physical Vapor Deposition, physical vapour deposition (PVD)) deposits one layer of metal ohmic contact to form Europe on 120
Nurse contact metal layer 170.
Step 7: as shown in Figure 2 G, etching ohmic contact metal layer 170 to remove and be located at source region SZ, drain region
Ohmic contact metal layer 170 other than DZ, first grid region GZ1 and second grid region GZ2, connects to form corresponding source electrode
The source electrode 140 of contact hole SH, the drain electrode 150 for corresponding to drain contact hole DH, the first grid 160a for corresponding to first grid contact hole GH1
With the second grid 160b of corresponding second grid contact hole GH2, wherein source contact openings SH and drain contact hole DH are located at
Source region SZ and drain region DZ.Specifically, pass through lithographic definition source region SZ, drain region DZ and first grid first
Region GZ1 and second grid region GZ2；Etch away later deposited in step 6 be located at source region SZ, drain region DZ, the
Ohmic contact metal layer 170 except one area of grid GZ1 and the second grid region region GZ2 finally obtains the (packet of source electrode 140
Include the ohmic contact metal layer 170 positioned at source region SZ), (metal ohmic contacts including being located at drain region DZ of drain electrode 150
Layer 170), first grid 160a (including be located at first grid region GZ1 ohmic contact metal layer 170 and gate metal layer
130) and second grid 160b is (including the ohmic contact metal layer 170 and gate metal layer positioned at second grid region GZ2
130).It is found that in embodiments of the present invention, the width L1 of the bottom of finally obtained first grid 160a connects equal to first grid
The width of contact hole, the width L2 of the bottom of second grid 160b are equal to the width of second grid contact hole.
Wherein, the metal ohmic contact for example successively includes: the first titanium coating, aluminum metal layer, second from bottom to up
Titanium coating and titanium nitride layer.Wherein, the ingredient of first titanium coating and second titanium coating is titanium (Ti), described
The ingredient of aluminum metal layer is aluminium (Al), and the ingredient of the titanium nitride layer is titanium nitride (TiN), is depositing the metal ohmic contact
When, it is sequentially depositing the first titanium coating, aluminum metal layer, the second titanium coating and titanium nitride layer, and first titanium coating, institute
The deposition thickness for stating aluminum metal layer, second titanium coating and the titanium nitride layer is for example respectively 200 angstroms, 1200 angstroms, 200
Angstrom and 200 angstroms.
The deposition of the metal ohmic contact can be needed for example, by using the mode of magnetron sputtering to keep Ohmic contact good
Make each contact hole namely first grid contact hole GH1, second grid contact hole GH2, source contact openings SH and drain contact hole
DH cleans few impurity, and therefore, step 7 for example can also include removal step, specifically, such as is depositing the Ohmic contact gold
With hydrofluoric acid (HF) each contact hole is cleaned before belonging to, depositing will be in nitrogen (N after the metal ohmic contact2) carry out under environment
850 DEG C, the short annealing (RTS) of 45s.
Further, before step 1, it such as further comprises the steps of: and to form semiconductor substrate 110.Specifically, in semiconductor
Such as nitride buffer layer of buffer layer 113 and such as aluminum gallium nitride layer of barrier layer 115, buffer layer 113 are sequentially depositing on substrate 111
Two-dimensional electron gas channel 117 can be formed between barrier layer 115, ultimately form semiconductor substrate 110.Gallium nitride is that the third generation is loose
Bandgap semiconductor material has big forbidden bandwidth, high electron saturation velocities, high breakdown electric field, higher heat-conductivity, corrosion-resistant and anti-
The characteristics such as radiance and under high pressure, high frequency, high temperature, high-power and Flouride-resistani acid phesphatase environmental condition have stronger advantage, from
But study the optimal material of shortwave opto-electronic device and high voltagehigh frequency rate high power device；Wherein, big forbidden bandwidth is 3.4 electricity
Sub- volt, high electron saturation velocities are 2e7 centimeters per second, and high breakdown electric field is 1e10~-3e10 volts per cm.
By the above process, a complete semiconductor devices 100 completes.It is so without being limited thereto, in other embodiments
In, it also changes or increases other steps, to complete semiconductor devices 100.
In conclusion the embodiment of the present invention is redesigned by the structure to semiconductor devices, by double gate structures application
In enhancing/depletion-mode AlGaN/GaN HEMT design, grid control ability can be improved, reduce electric leakage of the grid and OFF state leakage
Electricity realizes the Schottky contacts and low drain leakage current of high quality, improves drain leakage effect caused by grid, Neng Gouyou
Effect improves the uniformity of good Sub-Threshold Characteristic and AlGaN potential barrier thickness, keeps the barrier layer below grid thinning to realize enhancing
Operation increases gate leakage and reduces breakdown voltage.Semiconductor devices 100 can be applied to power electronic element, filter, wireless
In the technical fields such as telecommunication element, have a good application prospect.
In several embodiments provided herein, it should be understood that disclosed system, device and/or method, it can
To realize by another way.For example, the apparatus embodiments described above are merely exemplary, for example, the unit/
The division of module, only a kind of logical function partition, there may be another division manner in actual implementation, such as multichannel unit
Or module can be combined or can be integrated into another system, or some features can be ignored or not executed.Another point, institute
Display or the mutual coupling, direct-coupling or communication connection discussed can be through some interfaces, device or unit
Indirect coupling or communication connection can be electrical property, mechanical or other forms.
The units/modules as illustrated by the separation member may or may not be physically separated, as
The component that units/modules are shown may or may not be physical unit, it can and it is in one place, or can also be with
It is distributed on multi-channel network unit.Some or all of units/modules therein can be selected to realize according to the actual needs
The purpose of this embodiment scheme.
Finally, it should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
Present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: it still may be used
To modify the technical solutions described in the foregoing embodiments or equivalent replacement of some of the technical features；
And these are modified or replaceed, technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution spirit and
Range.
Claims (10)
1. a kind of semiconductor devices characterized by comprising
Semiconductor substrate；
Dielectric layer is arranged on the semiconductor substrate；
Source electrode and drain electrode is arranged on the dielectric layer；And
First grid and second grid are spaced apart from each other and are arranged on the dielectric layer；
Wherein, the first grid and the second grid are between the source electrode and the drain electrode, the source electrode, the leakage
Pole, the first grid and the second grid extend through the dielectric layer and protrude into the semiconductor substrate with half
Conductor substrate forms Schottky contacts.
2. semiconductor devices as described in claim 1, which is characterized in that the semiconductor substrate includes: silicon substrate, Yi Jishe
It is placed in the nitride buffer layer of the surface of silicon and is set to the aluminum gallium nitride layer on the nitride buffer layer surface；Its
In, Two-dimensional electron gas channel can be formed between the nitride buffer layer and the aluminum gallium nitride layer；The source electrode, the leakage
Pole, the first grid and the second grid protrude into the aluminum gallium nitride layer to form Schottky with the aluminum gallium nitride layer
Contact.
3. semiconductor devices as described in claim 1, which is characterized in that the source electrode and the drain electrode are by metal ohmic contact
Composition, the first grid and the second grid are by the gate metal and the metal ohmic contact that set gradually from bottom to up
Composition；Wherein, the metal ohmic contact includes the first titanium coating, aluminum metal layer, the second titanium set gradually from bottom to up
Metal layer and the first titanium nitride layer, the material of the gate metal are titanium nitride.
4. semiconductor devices as described in claim 1, which is characterized in that the material of the dielectric layer is silicon nitride, silica
Or hafnium oxide.
5. semiconductor devices as described in claim 1, which is characterized in that the width of the bottom of the first grid is less than described
The width of the bottom of second grid.
6. semiconductor devices as described in claim 1, which is characterized in that the width of the bottom of the first grid is described the
The half of the width of the bottom of two grids.
7. such as semiconductor devices described in claim 5 or 6, which is characterized in that the semiconductor devices includes double-gate structure height
Electron mobility transistor, and the double-gate structure high electron mobility transistor has the source electrode, the drain electrode, described the
One grid and the second grid.
8. a kind of semiconductor devices characterized by comprising
Semiconductor substrate, comprising: silicon substrate, and be set to the buffer layer of the surface of silicon and be set to the buffer layer
The barrier layer on surface can form Two-dimensional electron gas channel between the buffer layer and the barrier layer；
Dielectric layer, be arranged on the semiconductor substrate, wherein source contact openings, drain contact hole, first grid contact hole and
Second grid contact hole runs through the dielectric layer and protrudes into the barrier layer；And
Source electrode, drain electrode, first grid and second grid, be arranged fill on the dielectric layer and respectively the source contact openings,
The drain contact hole, the first grid contact hole and the second grid contact hole are to form Schottky with the barrier layer
Contact；
Wherein, the first grid contact hole and the second grid contact hole are located at the source contact openings and the drain electrode connects
Between contact hole, the width of the first grid contact hole is less than the width of the second grid contact hole.
9. semiconductor devices as claimed in claim 8, which is characterized in that the first grid contact hole connects adjacent to the source electrode
Contact hole setting, the second grid contact hole are arranged adjacent to the drain contact hole；The semiconductor devices includes double-gate structure
High electron mobility transistor, and the double-gate structure high electron mobility transistor have the source electrode, it is described drain electrode, it is described
First grid and the second grid.
10. a kind of production method of semiconductor devices, which is characterized in that comprising steps of
Dielectric layer is formed on a semiconductor substrate, wherein the semiconductor substrate includes: semiconductor substrate, and is set gradually
Buffer layer and barrier layer on the semiconductor substrate；
The dielectric layer and the barrier layer are etched, to form first grid contact hole and second grid contact hole, wherein described
First grid contact hole and the second grid contact hole run through the dielectric layer and protrude into the barrier layer；
Gate metal layer is formed on the dielectric layer and extends to the gate metal layer in the first grid contact hole
With in the second grid contact hole to cover the bottom of the first grid contact hole and the bottom of the second grid contact hole
Portion；
The gate metal layer is etched, to remove the gate metal being located at other than first grid region and second grid region
Layer, wherein the first grid contact hole and the second grid contact hole are located at the first grid region and described
Second grid region；
The dielectric layer and the barrier layer are etched, to form source contact openings and drain contact hole, wherein the source contact
Hole and the drain contact hole run through the dielectric layer and protrude into the aluminum gallium nitride layer；
Ohmic contact metal layer is formed in the gate metal layer and the dielectric layer and fills out the ohmic contact metal layer
It is charged to the source contact openings, the drain contact hole, the first grid contact hole and the second grid contact hole；And
The ohmic contact metal layer is etched, source region, drain region, the first grid region and described are located at removal
The ohmic contact metal layer other than second grid region, to form the source electrode of the corresponding source contact openings, corresponding institute
State the drain electrode of drain contact hole, the first grid of the corresponding first grid contact hole and the corresponding second grid contact hole
Second grid, wherein the source contact openings and the drain contact hole are located at the source region and the drain region
Domain.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811124144.2A CN109524461A (en) | 2018-09-26 | 2018-09-26 | Semiconductor devices and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811124144.2A CN109524461A (en) | 2018-09-26 | 2018-09-26 | Semiconductor devices and preparation method thereof |
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| Publication Number | Publication Date |
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ID=65771003
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Country Status (1)
| Country | Link |
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2018
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Application publication date: 20190326 |