CN209282207U - Semiconductor devices - Google Patents
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- CN209282207U CN209282207U CN201821571500.0U CN201821571500U CN209282207U CN 209282207 U CN209282207 U CN 209282207U CN 201821571500 U CN201821571500 U CN 201821571500U CN 209282207 U CN209282207 U CN 209282207U
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Abstract
The utility model relates to technical field of semiconductors, provide a kind of semiconductor devices.The semiconductor devices includes: semiconductor substrate；Dielectric layer is arranged on the semiconductor substrate；Source electrode and drain electrode is arranged on the dielectric layer；And first grid and second grid, it is spaced apart from each other and is arranged on the dielectric layer；Wherein, between the source electrode and the drain electrode, the source electrode, the drain electrode, the first grid and the second grid extend through the dielectric layer and protrude into the semiconductor substrate for the first grid and the second grid.Grid control ability can be improved in the semiconductor devices of the utility model, reduces electric leakage of the grid and OFF state electric leakage, can be realized the Schottky contacts and low drain leakage current of high quality.
Description
Technical field
The utility model relates to technical field of semiconductors more particularly to a kind of semiconductor devices.
Background technique
AlGaN (aluminum gallium nitride)/GaN (gallium nitride) HEMT (High Electron Mobility Transistor,
High electron mobility transistor) there is the semiconductor devices such as device excellent characteristics and extensive use to have had several so far
For kind technology for manufacturing enhanced semiconductor device, all these technologies empty grating of semiconductor element using different technologies
Two-dimensional electron gas (2DEG) channel (under zero grid bias) of lower section, this is the normally off necessary to operation.In order to realize this
Target has developed enhanced GaN (gallium nitride) transistor of various technologies.However, it is difficult to be improved using these methods
Low subthreshold value is swung and the uniformity of off-state current and the good Sub-Threshold Characteristic of AlGaN (aluminum gallium nitride) potential barrier thickness.
It is, therefore, desirable to provide a kind of semiconductor devices for being able to solve problem above.
Utility model content
To solve the above problems, the utility model embodiment provides a kind of semiconductor devices, grid control energy can be improved
Power reduces electric leakage of the grid and OFF state electric leakage, can be realized the Schottky contacts and low drain leakage current of high quality.
Specifically, a kind of semiconductor devices provided by the embodiment of the utility model, comprising: semiconductor substrate；Dielectric layer, if
It sets on the semiconductor substrate；Source electrode and drain electrode is arranged on the dielectric layer；And first grid and second grid, phase
It is mutually arranged at intervals on the dielectric layer；Wherein, the first grid and the second grid are located at the source electrode and the leakage
Between pole, the source electrode, the drain electrode, the first grid and the second grid extend through the dielectric layer and protrude into
The semiconductor substrate.
The utility model in one embodiment, the semiconductor substrate includes: silicon substrate, and is set to described
The nitride buffer layer of surface of silicon and the aluminum gallium nitride layer for being set to the nitride buffer layer surface；Wherein, the source
Pole, the drain electrode, the first grid and the second grid protrude into the aluminum gallium nitride layer.
The utility model in one embodiment, the source electrode and it is described drain electrode be made of metal ohmic contact, institute
First grid and the second grid is stated to be made of the gate metal set gradually from bottom to up and the metal ohmic contact；Its
In, the metal ohmic contact include the first titanium coating set gradually from bottom to up, aluminum metal layer, the second titanium coating and
First titanium nitride layer, the gate metal are another titanium nitride layer.
The utility model in one embodiment, the thickness of the nitride buffer layer is greater than 3 microns.
The utility model in one embodiment, the width of the bottom of the first grid is less than the second grid
Bottom width.
The utility model in one embodiment, the width of the bottom of the first grid is the second grid
The half of the width of bottom.
The utility model in one embodiment, the semiconductor devices includes that double-gate structure high electron mobility is brilliant
Body pipe, and the double-gate structure high electron mobility transistor has the source electrode, the drain electrode, the first grid and described
Second grid.
On the other hand, a kind of semiconductor devices provided by the embodiment of the utility model, comprising: semiconductor substrate, comprising: silicon
Substrate, and be set to the buffer layer of the surface of silicon and be set to the barrier layer of the buffer-layer surface；Dielectric layer, if
It sets on the semiconductor substrate, wherein source contact openings, drain contact hole, first grid contact hole and second grid contact
Kong Jun is through the dielectric layer and protrudes into the barrier layer；And source electrode, drain electrode, first grid and second grid, it is arranged in institute
It states on dielectric layer and fills the source contact openings, the drain contact hole, the first grid contact hole and described respectively
Two gate contact holes；Wherein, the first grid contact hole and the second grid contact hole be located at the source contact openings and
Between the drain contact hole, the width of the first grid contact hole is less than the width of the second grid contact hole.
The utility model in one embodiment, the first grid contact hole is set adjacent to the source contact openings
It sets, the second grid contact hole is arranged adjacent to the drain contact hole；The semiconductor devices includes the high electronics of double-gate structure
Mobility transistor, and the double-gate structure high electron mobility transistor has the source electrode, the drain electrode, the first grid
Pole and the second grid.
The utility model in one embodiment, the width of the first grid contact hole is that the second grid connects
The half of the width of contact hole.
It in the utility model embodiment, is redesigned by structure to semiconductor devices, such as by double gate structures
Applied to enhancing/depletion-mode AlGaN/GaN HEMT design, grid control ability can be improved, reduce electric leakage of the grid and OFF state
The Schottky contacts and low drain leakage current of high quality are realized in electric leakage, improve drain leakage effect caused by grid, can
It is effectively improved the uniformity of good Sub-Threshold Characteristic Yu AlGaN potential barrier thickness, keeps the barrier layer below grid thinning to realize and increase
Strong operation increases gate leakage and reduces breakdown voltage.
Detailed description of the invention
Fig. 1 is the partial profile structure of the active region of semiconductor devices in the utility model one embodiment.
Fig. 2A is that the obtained device of step 1 of the production method of semiconductor devices in the utility model one embodiment has
The partial profile structure of source region.
Fig. 2 B is that the obtained device of step 2 of the production method of semiconductor devices in the utility model one embodiment has
The partial profile structure of source region.
Fig. 2 C is that the obtained device of step 3 of the production method of semiconductor devices in the utility model one embodiment has
The partial profile structure of source region.
Fig. 2 D is that the obtained device of step 4 of the production method of semiconductor devices in the utility model one embodiment has
The partial profile structure of source region.
Fig. 2 E is that the obtained device of step 5 of the production method of semiconductor devices in the utility model one embodiment has
The partial profile structure of source region.
Fig. 2 F is that the obtained device of step 6 of the production method of semiconductor devices in the utility model one embodiment has
The partial profile structure of source region.
Fig. 2 G is that the obtained device of step 7 of the production method of semiconductor devices in the utility model one embodiment has
The partial profile structure of source region.
Specific embodiment
It is practical new below in conjunction with this to keep the objectives, technical solutions, and advantages of the embodiments of the present invention clearer
Attached drawing in type embodiment, the technical scheme in the utility model embodiment is clearly and completely described, it is clear that is retouched
The embodiment stated is the utility model a part of the embodiment, instead of all the embodiments.Based on the implementation in the utility model
Example, every other embodiment obtained by those of ordinary skill in the art without making creative efforts belong to
The range of the utility model protection.
As shown in Figure 1, a kind of semiconductor devices 100 that one embodiment of the utility model provides, comprising: semiconductor-based
Plate 110, dielectric layer 120, source electrode 140, drain electrode 150, first grid 160a and second grid 160b.
Wherein, dielectric layer 120 is for example set on semiconductor substrate 110；Source electrode 140, drain electrode 150, first grid 160a
It is for example spaced apart from each other and is set on dielectric layer 120 with second grid 160b.For example, the semiconductor devices 100 of the present embodiment
For example including the double-gate structure high electron mobility transistor (HEMT) based on gallium nitride, and the double grid knot based on gallium nitride
Structure high electron mobility transistor (HEMT) has source electrode 140, drain electrode 150, first grid 160a and second grid 160b.
Wherein, first grid 160a and second grid 160b for example positioned at source electrode 140 and drain electrode 150 between, source electrode 140,
Drain electrode 150, first grid 160a and second grid 160b extend through dielectric layer 120 and protrude into inside semiconductor substrate 110 with
Schottky contacts are formed with semiconductor substrate 110.
Specifically, semiconductor substrate 110 for example, such as silicon substrate of semiconductor substrate 111, and it is set to semiconductor
Such as nitride buffer layer of buffer layer 113 on 111 surface of substrate and such as nitrogen of barrier layer 115 for being set to 113 surface of buffer layer
Change gallium aluminium layer.
Semiconductor substrate 111 is, for example, P (111) type silicon substrate.
The thickness of buffer layer 113 is greater than 3 microns.
Two-dimensional electron gas channel (2DEG) 117 can be for example formed between buffer layer 113 and barrier layer 115.
Source electrode 140, drain electrode 150, first grid 160a and second grid 160b for example protrude into inside barrier layer 115 with
Barrier layer 115 forms Schottky contacts.But source electrode 140, drain electrode 150, first grid 160a and second grid 160b do not run through
Barrier layer 115.
Specifically, source electrode 140 and drain electrode 150 are for example made of metal ohmic contact, first grid 160a and second grid
160b is for example made of the gate metal and the metal ohmic contact that set gradually from bottom to up.Wherein, the gate metal
Material be titanium nitride (TiN) namely gate metal is titanium nitride layer；Included by first grid 160a and second grid 160b
The thickness of the gate metal is, for example, 200 nanometers, and the metal ohmic contact for example successively includes: the first titanium from bottom to up
Belong to layer, aluminum metal layer, the second titanium coating and titanium nitride layer.Wherein, first titanium coating and second titanium coating
Ingredient be titanium (Ti), the ingredient of the aluminum metal layer is aluminium (Al), and the ingredient of the titanium nitride layer is titanium nitride (TiN).
The material of dielectric layer 120 is, for example, silicon nitride (Si3N4).Herein it is noted that the material example of dielectric layer 120
The material of the dielectric layer 120 of semiconductor devices 100, such as silica, hafnium oxide are suitable as known to can also be other
Equal high-k (Gao Jie electricity) material.
The width L1 of the bottom of first grid 160a is, for example, less than the width L2 of the bottom of second grid 160b.
Further, the width L1 of the bottom of first grid 160a is, for example, the width L2 of the bottom of second grid 160b
Half.Certainly, the ratio of L1 and L2 for example can also be other suitable numerical value.
First grid 160a is for example arranged adjacent to source electrode 140, and second grid 160b such as adjacent drains 150 are arranged.That is,
First grid 160a is arranged between source electrode 140 and second grid 160b, and second grid 160b, which for example be arranged, is draining 150 and the
Between one grid 160a.
In addition, the utility model embodiment also provides the production method of above-mentioned semiconductor device 100.Such as Fig. 2A to 2G institute
Show, the partial structurtes section for obtained device active region domain in each step of the production method of semiconductor devices 100 shows
It is intended to.Specifically, the production method of the semiconductor devices 100 specifically includes that
Step 1: as shown in Figure 2 A, dielectric layer 120 is formed on semiconductor substrate 110.Specifically, to semiconductor substrate
It, can be for example using LPCVD (Low Pressure Chemical Vapor Deposition, low pressure chemical after 110 are cleaned
Vapor deposition) one layer of 120 (for example, Si of dielectric layer of deposition3N4, silicon nitride), for being passivated 110 surface of semiconductor substrate, eliminate
Its surface state, to improve the reliability of finally formed semiconductor devices 100.
Step 2: as shown in Figure 2 B, etching media layer 120 and barrier layer 115 are to form first grid contact hole GH1 and the
Two gate contact hole GH2.Specifically, the corresponding gate contact bore region GHZ1 of lithographic definition first grid contact hole GH1 and
The corresponding gate contact bore region GHZ2 of two gate contact hole GH2, then for example, by using sulfur fluoride (SF6) and chlorine (Cl2) it is gas
ICP (Inductively Coupled Plasma, the plasma inductive coupling) lithographic method in body source etches away in step 1
What is formed is located at whole dielectric layers 120 and portion of first grid contact bore region GHZ1 and second grid contact bore region GHZ2
Divide the barrier layer 115 of thickness, to form first grid contact hole GH1 and second grid contact hole GH2.Wherein, the program of photoetching
It include gluing, exposure and imaging.Wherein, first grid contact hole GH1 and second grid contact hole GH2 run through dielectric layer
120 and protrude into barrier layer 115.
Step 3: as shown in Figure 2 C, forming gate metal layer 130 on dielectric layer 120 and extend gate metal layer 140
The bottom and second of first grid contact hole GH1 is covered in first grid contact hole GH1 and in second grid contact hole GH2
The bottom of gate contact hole GH2.Specifically, one layer of gate metal, such as titanium nitride (TiN) are deposited, on dielectric layer 120 with shape
At the gate metal layer 130 of semiconductor devices 100.
Step 4: as shown in Figure 2 D, etching gate metal layer 130 to remove and be located at first grid region GZ1 and second grid
Gate metal layer 130 other than the GZ2 of region, wherein first grid contact hole GH1 and second grid contact hole GH2 for example distinguish
Positioned at first grid region GZ1 and second grid region GZ2.
Step 5: as shown in Figure 2 E, etching media layer 120 and barrier layer 115 are to form source contact openings SH and drain contact
Hole DH.Specifically, after lithographic definition source contact bore region SHZ and drain contact bore region DHZ, use sulfur fluoride for gas source
ICP lithographic method etch away whole media positioned at source contact bore region SHZ and under drain contact bore region DHZ
The barrier layer 115 of layer 120 and segment thickness is to form source contact openings SH and drain contact hole DH.Wherein, source contact openings SH
Run through dielectric layer 120 with drain contact hole DH and protrudes into barrier layer 115.
Step 6: as shown in Figure 2 F, ohmic contact metal layer 170, simultaneously is formed in gate metal layer 130 and dielectric layer 120
Make the filling of ohmic contact metal layer 170 to source contact openings SH, drain contact hole DH, first grid contact hole GH1 and second gate
Pole contact hole GH2.Specifically, exposed gate metal layer 130 and dielectric layer on the surface of the obtained device of step 5
PVD (Physical Vapor Deposition, physical vapour deposition (PVD)) deposits one layer of metal ohmic contact to form Europe on 120
Nurse contact metal layer 170.
Step 7: as shown in Figure 2 G, etching ohmic contact metal layer 170 to remove and be located at source region SZ, drain region
Ohmic contact metal layer 170 other than DZ, first grid region GZ1 and second grid region GZ2, connects to form corresponding source electrode
The source electrode 140 of contact hole SH, the drain electrode 150 for corresponding to drain contact hole DH, the first grid 160a for corresponding to first grid contact hole GH1
With the second grid 160b of corresponding second grid contact hole GH2, wherein source contact openings SH and drain contact hole DH are located at
Source region SZ and drain region DZ.Specifically, pass through lithographic definition source region SZ, drain region DZ and first grid first
Region GZ1 and second grid region GZ2；Etch away later deposited in step 6 be located at source region SZ, drain region DZ, the
Ohmic contact metal layer 170 except one area of grid GZ1 and the second grid region region GZ2 finally obtains the (packet of source electrode 140
Include the ohmic contact metal layer 170 positioned at source region SZ), (metal ohmic contacts including being located at drain region DZ of drain electrode 150
Layer 170), first grid 160a (including be located at first grid region GZ1 ohmic contact metal layer 170 and gate metal layer
130) and second grid 160b is (including the ohmic contact metal layer 170 and gate metal layer positioned at second grid region GZ2
130).It is found that the width L1 of the bottom of finally obtained first grid 160a is equal to the first grid in the utility model embodiment
The width of pole contact hole, the width L2 of the bottom of second grid 160b are equal to the width of second grid contact hole.
Wherein, the metal ohmic contact for example successively includes: the first titanium coating, aluminum metal layer, second from bottom to up
Titanium coating and titanium nitride layer.Wherein, the ingredient of first titanium coating and second titanium coating is titanium (Ti), described
The ingredient of aluminum metal layer is aluminium (Al), and the ingredient of the titanium nitride layer is titanium nitride (TiN), is depositing the metal ohmic contact
When, it is sequentially depositing the first titanium coating, aluminum metal layer, the second titanium coating and titanium nitride layer, and first titanium coating, institute
The deposition thickness for stating aluminum metal layer, second titanium coating and the titanium nitride layer is for example respectively 200 angstroms, 1200 angstroms, 200
Angstrom and 200 angstroms.
The deposition of the metal ohmic contact can be needed for example, by using the mode of magnetron sputtering to keep Ohmic contact good
Make each contact hole namely first grid contact hole GH1, second grid contact hole GH2, source contact openings SH and drain contact hole
DH cleans few impurity, and therefore, step 7 for example can also include removal step, specifically, such as is depositing the Ohmic contact gold
With hydrofluoric acid (HF) each contact hole is cleaned before belonging to, depositing will be in nitrogen (N after the metal ohmic contact2) carry out under environment
850 DEG C, the short annealing (RTS) of 45s.
Further, before step 1, it such as further comprises the steps of: and to form semiconductor substrate 110.Specifically, in semiconductor
Such as nitride buffer layer of buffer layer 113 and such as aluminum gallium nitride layer of barrier layer 115, buffer layer 113 are sequentially depositing on substrate 111
Two-dimensional electron gas channel 117 can be formed between barrier layer 115, ultimately form semiconductor substrate 110.Gallium nitride is that the third generation is loose
Bandgap semiconductor material has big forbidden bandwidth, high electron saturation velocities, high breakdown electric field, higher heat-conductivity, corrosion-resistant and anti-
The characteristics such as radiance and under high pressure, high frequency, high temperature, high-power and Flouride-resistani acid phesphatase environmental condition have stronger advantage, from
But study the optimal material of shortwave opto-electronic device and high voltagehigh frequency rate high power device；Wherein, big forbidden bandwidth is 3.4 electricity
Sub- volt, high electron saturation velocities are 2e7 centimeters per second, and high breakdown electric field is 1e10~-3e10 volts per cm.
By the above process, a complete semiconductor devices 100 completes.It is so without being limited thereto, in other embodiments
In, it also changes or increases other steps, to complete semiconductor devices 100.
In conclusion the utility model embodiment is redesigned by the structure to semiconductor devices, by double gate structures
Applied to enhancing/depletion-mode AlGaN/GaN HEMT design, grid control ability can be improved, reduce electric leakage of the grid and OFF state
The Schottky contacts and low drain leakage current of high quality are realized in electric leakage, improve drain leakage effect caused by grid, can
It is effectively improved the uniformity of good Sub-Threshold Characteristic Yu AlGaN potential barrier thickness, keeps the barrier layer below grid thinning to realize and increase
Strong operation increases gate leakage and reduces breakdown voltage.Semiconductor devices 100 can be applied to power electronic element, filter, nothing
In the technical fields such as line telecommunication element, have a good application prospect.
Finally, it should be noted that above embodiments are only to illustrate the technical solution of the utility model, rather than its limitations；
Although the utility model is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that:
It is still possible to modify the technical solutions described in the foregoing embodiments, or part of technical characteristic is carried out etc.
With replacement；And these are modified or replaceed, various embodiments of the utility model technology that it does not separate the essence of the corresponding technical solution
The spirit and scope of scheme.
Claims (10)
1. a kind of semiconductor devices characterized by comprising
Semiconductor substrate；
Dielectric layer is arranged on the semiconductor substrate；
Source electrode and drain electrode is arranged on the dielectric layer；And
First grid and second grid are spaced apart from each other and are arranged on the dielectric layer；
Wherein, the first grid and the second grid are between the source electrode and the drain electrode, the source electrode, the leakage
Pole, the first grid and the second grid extend through the dielectric layer and protrude into the semiconductor substrate but do not pass through
Wear the semiconductor substrate.
2. semiconductor devices as described in claim 1, which is characterized in that the semiconductor substrate includes: silicon substrate, Yi Jishe
It is placed in the nitride buffer layer of the surface of silicon and is set to the aluminum gallium nitride layer on the nitride buffer layer surface；Its
In, the source electrode, the drain electrode, the first grid and the second grid protrude into the aluminum gallium nitride layer but not through institute
State aluminum gallium nitride layer.
3. semiconductor devices as described in claim 1, which is characterized in that the source electrode and the drain electrode are by metal ohmic contact
Composition, the first grid and the second grid are by the gate metal and the metal ohmic contact that set gradually from bottom to up
Composition；Wherein, the metal ohmic contact includes the first titanium coating, aluminum metal layer, the second titanium set gradually from bottom to up
Metal layer and the first titanium nitride layer, the gate metal are another titanium nitride layer.
4. semiconductor devices as claimed in claim 2, which is characterized in that the thickness of the nitride buffer layer is greater than 3 microns.
5. semiconductor devices as described in claim 1, which is characterized in that the width of the bottom of the first grid is less than described
The width of the bottom of second grid.
6. semiconductor devices as described in claim 1, which is characterized in that the width of the bottom of the first grid is described the
The half of the width of the bottom of two grids.
7. such as semiconductor devices described in claim 5 or 6, which is characterized in that the semiconductor devices includes double-gate structure height
Electron mobility transistor, and the double-gate structure high electron mobility transistor has the source electrode, the drain electrode, described the
One grid and the second grid.
8. a kind of semiconductor devices characterized by comprising
Semiconductor substrate, comprising: silicon substrate, and be set to the buffer layer of the surface of silicon and be set to the buffer layer
The barrier layer on surface；
Dielectric layer, be arranged on the semiconductor substrate, wherein source contact openings, drain contact hole, first grid contact hole and
Second grid contact hole runs through the dielectric layer and protrudes into the barrier layer but not through the barrier layer；And
Source electrode, drain electrode, first grid and second grid, be arranged fill on the dielectric layer and respectively the source contact openings,
The drain contact hole, the first grid contact hole and the second grid contact hole；
Wherein, the first grid contact hole and the second grid contact hole are located at the source contact openings and the drain electrode connects
Between contact hole, the width of the first grid contact hole is less than the width of the second grid contact hole.
9. semiconductor devices as claimed in claim 8, which is characterized in that the first grid contact hole connects adjacent to the source electrode
Contact hole setting, the second grid contact hole are arranged adjacent to the drain contact hole；The semiconductor devices includes double-gate structure
High electron mobility transistor, and the double-gate structure high electron mobility transistor have the source electrode, it is described drain electrode, it is described
First grid and the second grid.
10. semiconductor devices as claimed in claim 8, which is characterized in that the width of the first grid contact hole is described
The half of the width of second grid contact hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821571500.0U CN209282207U (en) | 2018-09-26 | 2018-09-26 | Semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821571500.0U CN209282207U (en) | 2018-09-26 | 2018-09-26 | Semiconductor devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209282207U true CN209282207U (en) | 2019-08-20 |
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ID=67603911
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821571500.0U Active CN209282207U (en) | 2018-09-26 | 2018-09-26 | Semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209282207U (en) |
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2018
- 2018-09-26 CN CN201821571500.0U patent/CN209282207U/en active Active
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Effective date of registration: 20210205 Address after: 518000 s1704, building 17, merchants Garden City, Liuhe community, Pingshan street, Pingshan District, Shenzhen City, Guangdong Province Patentee after: SHENZHEN JINGXIANG TECHNOLOGY Co.,Ltd. Patentee after: Suzhou Chenhua Semiconductor Technology Co.,Ltd. Address before: 518052 Room 201, building a, No.1 Qianhai 1st Road, Shenzhen Qianhai Shenzhen Hong Kong cooperation zone, Shenzhen City, Guangdong Province Patentee before: SHENZHEN JINGXIANG TECHNOLOGY Co.,Ltd. |
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