CN109786233B - Preparation method of asymmetric surface channel field effect transistor and power device - Google Patents

Preparation method of asymmetric surface channel field effect transistor and power device Download PDF

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CN109786233B
CN109786233B CN201910044410.9A CN201910044410A CN109786233B CN 109786233 B CN109786233 B CN 109786233B CN 201910044410 A CN201910044410 A CN 201910044410A CN 109786233 B CN109786233 B CN 109786233B
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layer
metal
gate
metal layer
drain
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CN109786233A (en
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吕元杰
王元刚
冯志红
蔚翠
周闯杰
宋旭波
何泽召
梁士雄
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CETC 13 Research Institute
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Abstract

The invention provides a preparation method of an asymmetric surface channel field effect transistor and a power device, belonging to the technical field of microwave power devices and comprising the following steps: depositing a metal mask layer; preparing a first photoresist layer; forming a source region graph and a drain region graph; depositing a source metal layer and a drain metal layer on the source region graph and the drain region graph; stripping and removing the first photoresist; coating two photoresist layers; and photoetching the grid corrosion window pattern and the field plate metal window pattern, corroding the metal mask layer at the corresponding part, and depositing a grid metal layer and a field plate metal layer, wherein the space between the two sides of the grid metal layer and the metal mask layer which is not corroded at the corresponding side is not equal, and the effective grid source space is smaller than the effective grid drain space. According to the preparation method of the asymmetric surface channel field effect transistor, the device with the effective grid-source spacing smaller than the effective grid-drain spacing can give consideration to the saturation current, the breakdown voltage and the working voltage are effectively improved, and the power density of the device is improved.

Description

Preparation method of asymmetric surface channel field effect transistor and power device
Technical Field
The invention belongs to the technical field of microwave power devices, and particularly relates to a preparation method of an asymmetric surface channel field effect transistor and a power device.
Background
Surface channel devices have great advantages in high speed, high confinement and the like, and are concerned in the high frequency field. The commonly used surface channel materials at present comprise a p-type surface channel formed by processing diamond by hydrogen plasma, and two-dimensional materials such as graphene, BN, black phosphorus, two-dimensional GaN and the like. The characteristics of the surface channel device are greatly influenced by the surface state, and the self-alignment process developed in recent years effectively solves the problems. However, the self-aligned process can only realize the structure of the device with equal spacing between the gate source and the gate drain, and the breakdown voltage is generally low in order to take account of the saturation current, so that the self-aligned process is difficult to take account of the breakdown voltage and the saturation current.
Disclosure of Invention
The invention aims to provide a preparation method of an asymmetric surface channel field effect transistor, and aims to solve the technical problem of low breakdown voltage in the prior art.
In order to achieve the purpose, the invention adopts the technical scheme that: the preparation method of the asymmetric surface channel field effect transistor comprises the following steps:
depositing a metal mask layer on the surface channel epitaxial layer;
preparing a first photoresist layer on the metal mask layer;
exposing and developing to form a source region graph and a drain region graph;
removing the first photoresist layer at the source region pattern and the drain region pattern by wet etching;
depositing a source metal layer and a drain metal layer on the source region graph and the drain region graph;
coating a second photoresist layer and a third photoresist layer on the metal mask layer, the source metal layer and the drain metal layer;
photoetching at least one grid corrosion window pattern and at least one field plate metal window pattern between the source metal layer and the drain metal layer, and corroding the metal mask layer at the corresponding part;
a gate metal layer is correspondingly deposited at the gate corrosion window pattern, a field plate metal layer is correspondingly deposited at the field plate metal window pattern, and the gate metal layer is not connected with the field plate metal layer;
the device comprises a source metal layer, a drain metal layer, a gate metal layer, a source metal layer, a drain metal layer and a drain metal layer, wherein the distances between two sides of the gate metal layer and a non-corroded metal mask layer on the corresponding side are different, the distance between the gate metal layer and the non-corroded metal mask layer on one side of the source metal layer is an effective gate-source distance, the distance between the gate metal layer and the non-corroded metal mask layer on one side of the drain metal layer is an effective gate-drain distance, and the.
Further, a gate metal layer is deposited at the gate corrosion window pattern, and before a field plate metal is deposited at the field plate metal window pattern:
and a gate lower dielectric layer is deposited on the surface channel epitaxial layer, and the gate metal layer and the field plate metal are respectively deposited on the gate lower dielectric layer.
Further, the under-gate dielectric layer is a single-layer dielectric;
or, the grid lower dielectric layer is a multilayer dielectric.
Further, when the number of the grid corrosion window patterns is two or more, the structures of the grid corrosion window patterns are the same;
or, the structure of at least one of the gate etch window patterns is different from the structure of the other gate etch window patterns;
or, the structures of the grid corrosion window patterns are different.
Further, when the number of the gate metal layers is two or more, the structure of the gate metal layers is one or more of a straight gate, a T-shaped gate, a TT-shaped gate, a TTT-shaped gate, a U-shaped gate and a Y-shaped gate.
Further, when the number of the field plate metal window patterns is two or more, the structures of the field plate metal window patterns are the same;
or, the structure of at least one field plate metal window pattern is different from that of other field plate metal window patterns;
or, the structures of the field plate metal window patterns are different.
Further, no voltage is applied to the field plate metal layer;
alternatively, a separate voltage is applied.
Furthermore, the metal mask layer and the source metal layer are the same in metal type as the drain metal layer;
or the metal mask layer is different from the metal types of the source metal layer and the drain metal layer.
Furthermore, the metal mask layer, the source metal layer, the drain metal layer, the gate metal layer and the field plate metal layer are all single-layer metals;
or, both are multilayer metals;
or at least one single layer metal and one multi-layer metal.
The invention also aims to provide an asymmetric surface channel field effect transistor which is prepared by the method.
The preparation method of the asymmetric surface channel field effect transistor has the advantages that: compared with the prior art, the effective grid-source spacing is not equal to the effective grid-drain spacing, and the device with the effective grid-source spacing smaller than the effective grid-drain spacing can give consideration to saturation current, effectively improve breakdown voltage and working voltage, and improve the power density of the device.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed for the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a metal mask layer prepared by the method for preparing an asymmetric surface channel field effect transistor according to the embodiment of the present invention;
fig. 2 is a schematic structural diagram of a first photoresist layer prepared by the method for preparing an asymmetric surface channel field effect transistor according to the embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a source-drain metal layer prepared by the method for preparing an asymmetric surface channel field effect transistor according to the embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a photoresist layer for manufacturing a method of manufacturing an asymmetric surface channel field effect transistor according to an embodiment of the present invention;
FIG. 5 is a schematic structural diagram of a lithographic pattern of a method for manufacturing an asymmetric surface channel field effect transistor according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of an asymmetric surface channel FET fabricated in accordance with an embodiment of the present invention;
fig. 7 is a top view of an asymmetric surface channel field effect transistor made in accordance with an embodiment of the present invention.
Wherein, the labels in the figure are:
1-surface channel epitaxial layer; 2-a metal mask layer; 3-a source metal layer; 4-a second photoresist layer; 5-a gate lower dielectric layer; 6-a gate metal layer; 7-field plate metal layer; 8-a leakage metal layer; 9-a third photoresist layer; 10-etching a window pattern; 11-field plate metal window pattern; 12-first photoresist layer.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1 to 5, a method for fabricating an asymmetric surface channel field effect transistor according to the present invention will now be described. The preparation method of the asymmetric surface channel field effect transistor comprises the following steps:
depositing a metal mask layer 2 on the surface channel epitaxial layer 1, as shown in fig. 1;
preparing a first photoresist layer 12 on the metal mask layer 2, see fig. 2;
exposing and developing to form a source region pattern and a drain region pattern, as shown in FIG. 2;
wet etching is carried out to remove the first photoresist layer 12 at the positions of the source region pattern and the drain region pattern, and the figure 2 is referred;
depositing a source metal layer 3 and a drain metal layer 8 at the positions of the source region pattern and the drain region pattern, and referring to FIG. 3;
coating a second photoresist layer 4 and a third photoresist layer 9 on the metal mask layer 2, the source metal layer 3 and the drain metal layer 8, see fig. 4;
photoetching at least one gate corrosion window pattern 10 and at least one field plate metal window pattern 11 between the source metal layer 3 and the drain metal layer 8, and corroding the metal mask layer 2 at the corresponding part, as shown in fig. 5;
correspondingly depositing a gate metal layer 6 at the gate corrosion window pattern 10, correspondingly depositing a field plate metal layer 7 at the field plate metal window pattern 11, wherein the gate metal layer 6 is not connected with the field plate metal layer 7, as shown in fig. 6;
the distances between the two sides of the gate metal layer 6 and the non-corroded metal mask layer 2 on the corresponding side are different, the distance between the gate metal layer 6 and the non-corroded metal mask layer 2 on the side biased to the source metal layer 3 is an effective gate-source distance, the distance between the gate metal layer 6 and the non-corroded metal mask layer 2 on the side biased to the drain metal layer 8 is an effective gate-drain distance, that is, the effective gate-source distance is not equal to the effective gate-drain distance, and the effective gate-source distance is smaller than the effective gate-drain distance, see fig. 6.
Compared with the prior art, the preparation method of the asymmetric surface channel field effect transistor has the advantages that the effective grid-source spacing is not equal to the effective grid-drain spacing, the effective grid-source spacing is smaller than the effective grid-drain spacing, the saturation current is considered, the breakdown voltage and the working voltage are effectively improved, and the power density of the device is improved.
Wherein a mesa isolation process may be performed after any of the above steps to separate the device fabricated according to the present invention from other parts.
Referring to fig. 6, as a specific embodiment of the method for manufacturing an asymmetric surface channel field effect transistor according to the present invention, before depositing a gate metal layer 6 at the gate etching window pattern 10 and depositing a field plate metal at the field plate metal window pattern 11: and a gate lower dielectric layer 5 is deposited on the surface channel epitaxial layer 1, and the gate metal layer 6 and the field plate metal are respectively deposited on the gate lower dielectric layer 5. That is, the gate lower dielectric layer 5 may be disposed below the gate metal layer 6 and the field plate metal layer 7, see fig. 6, or the gate metal layer 6 and the field plate metal layer 7 may be directly formed on the surface channel epitaxial layer 1.
Referring to fig. 6, as a specific embodiment of the method for manufacturing an asymmetric surface channel field effect transistor according to the present invention, the under-gate dielectric layer 5 is a single-layer dielectric; or, the gate lower dielectric layer 5 is a multilayer dielectric.
Referring to fig. 5, as a specific embodiment of the method for manufacturing an asymmetric surface channel field effect transistor according to the present invention, when the number of the gate etching window patterns 10 is two or more, the structures of the gate etching window patterns 10 are the same; or, the structure of at least one of the gate etch window patterns 10 is different from the structure of the other gate etch window patterns 10; alternatively, the structures of the gate etch window patterns 10 are different. Fig. 5 shows a gate etching window pattern 10, and two or three patterns may be simultaneously etched, and the structures and the sizes of the patterns may be completely the same or not completely the same, depending on actual needs.
As a specific implementation manner of the preparation method of the asymmetric surface channel field effect transistor provided by the present invention, when the number of the gate metal layers 6 is two or more, the structure of the gate metal layer 6 is one or a combination of more than one of a straight gate, a T-type gate, a TT-type gate, a TTT-type gate, a U-type gate and a Y-type gate. In the figure of the present embodiment, the gate metal layer 6 is a T-shaped gate, referring to fig. 6, the T-shaped gate helps to take account of the characteristics of gate parasitic capacitance and gate resistance, and improve the frequency characteristics of the device, and the structure and number of the gate metal layer 6 are determined according to the structure and number of the gate etching window patterns 10.
Referring to fig. 5, as a specific embodiment of the method for manufacturing an asymmetric surface channel field effect transistor provided by the present invention, when the number of the field plate metal window patterns 11 is two or more, the structures of the field plate metal window patterns 11 are the same; alternatively, the structure of at least one of the field plate metal window patterns 11 is different from the structures of the other field plate metal window patterns 11; alternatively, the structures of the field plate metal window patterns 11 are different. Fig. 5 shows a field plate metal window pattern 11, and according to actual needs, two, three, four, etc. patterns may be lithographically formed, and the structures of these patterns may or may not be completely the same, and the structure of the field plate metal layer 7 shown in fig. 6 is a T-shaped structure.
As a specific embodiment of the method for manufacturing the asymmetric surface channel field effect transistor provided by the present invention, no voltage is applied to the field plate metal layer 7; alternatively, a separate voltage is applied. The field plate metal layer 7 functions to facilitate formation of an asymmetric structure, and in addition, a field plate structure can be formed.
Referring to fig. 3, as a specific embodiment of the method for manufacturing an asymmetric surface channel field effect transistor according to the present invention, the metal type of the metal mask layer 2 is the same as the metal type of the source metal layer 3 and the metal type of the drain metal layer 8; or, the metal mask layer 2 is different from the source metal layer 3 and the drain metal layer 8 in metal type. The metal of the metal mask layer 2, the metal of the source metal layer 3 and the metal of the drain metal layer 8 are all metals conventionally used in the preparation of the existing semiconductor device.
Referring to fig. 6, as a specific embodiment of the method for manufacturing an asymmetric surface channel field effect transistor provided by the present invention, the metal mask layer 2, the source metal layer 3, the drain metal layer 8, the gate metal layer 6, and the field plate metal layer 7 are all single-layer metals; or, both are multilayer metals; or at least one single layer metal and one multi-layer metal.
As a specific embodiment of the method for manufacturing the asymmetric surface channel field effect transistor, the surface channel epitaxial layer 1 is a diamond p-type surface channel, or is a two-dimensional material such as graphene, BN, black phosphorus, GaN, and the like, and the substrate used is a material such as diamond, SiC, GaN, sapphire, Si, Au, quartz, SiO2, SiN, copper, and the like, or a composite substrate formed by combining a plurality of materials.
In this embodiment, two photoresist layers are used, the gate erosion window pattern 10 and the field plate metal window pattern 11 are formed by exposure and development, which may be one-time exposure and one-time development, or multiple exposure and multiple development, where the number of layers of each photoresist layer may be two or more.
And preparing a passivation layer after the gate metal layer 6 and the field plate metal layer 7 to protect the device, wherein the passivation layer is a single-layer or multi-layer medium.
Referring to fig. 6 to 7, the invention further provides a power device manufactured by the method. In fig. 7, S represents the source metal layer 3, D represents the gate metal layer 6, and G represents the drain metal layer 8. The transistor prepared by the method has the advantages that the grid is deviated to the source instead of the middle of the source and the drain, namely the source metal layer 3 and the drain metal layer 8 are asymmetrically distributed relative to the grid metal layer 6, the field plate metal window is additionally arranged between the source grid and the drain, the grid is deviated to the source device, the saturation current can be considered, the breakdown voltage and the working voltage can be effectively improved, and the power density of the device can be improved.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims (9)

1. The preparation method of the asymmetric surface channel field effect transistor is characterized by comprising the following steps:
depositing a metal mask layer on the surface channel epitaxial layer;
preparing a first photoresist layer on the metal mask layer;
exposing and developing to form a source region graph and a drain region graph;
removing the first photoresist layer at the source region pattern and the drain region pattern by wet etching;
depositing a source metal layer and a drain metal layer on the source region graph and the drain region graph;
coating a second photoresist layer and a third photoresist layer on the metal mask layer, the source metal layer and the drain metal layer;
photoetching at least one grid corrosion window pattern and at least one field plate metal window pattern between the source metal layer and the drain metal layer, and corroding the metal mask layer at the corresponding part;
a gate metal layer is correspondingly deposited at the gate corrosion window pattern, a field plate metal layer is correspondingly deposited at the field plate metal window pattern, and the gate metal layer is not connected with the field plate metal layer;
the device comprises a device, a source metal layer, a drain metal layer, a gate metal layer, a source metal layer, a drain metal layer and a drain metal layer, wherein the distances between two sides of the gate metal layer and non-corroded metal mask layers on corresponding sides are different, the distance between the gate metal layer and the non-corroded metal mask layer on one side of the source metal layer is an effective gate-source distance, the distance between the gate metal layer and the non-corroded metal mask layer on one side of the drain metal layer is an effective gate-drain distance, and the effective;
when the number of the grid corrosion window patterns is two or more, the structures of the grid corrosion window patterns are the same;
or, the structure of at least one of the gate etch window patterns is different from the structure of the other gate etch window patterns;
or, the structures of the grid corrosion window patterns are different.
2. The method of claim 1, wherein depositing a gate metal layer at the gate etch window pattern and prior to depositing a field plate metal at the field plate metal window pattern:
and a gate lower dielectric layer is deposited on the surface channel epitaxial layer, and the gate metal layer and the field plate metal are respectively deposited on the gate lower dielectric layer.
3. The method of manufacturing an asymmetric surface channel field effect transistor as claimed in claim 2, characterized in that: the grid lower dielectric layer is a single-layer dielectric;
or, the grid lower dielectric layer is a multilayer dielectric.
4. The method of manufacturing an asymmetric surface channel field effect transistor as claimed in claim 1, wherein: when the number of the gate metal layers is two or more, the structure of the gate metal layers is one or more of a straight gate, a T-shaped gate, a TT-shaped gate, a TTT-shaped gate, a U-shaped gate and a Y-shaped gate.
5. The method of manufacturing an asymmetric surface channel field effect transistor as claimed in any of claims 1 to 4, characterized in that: when the number of the field plate metal window patterns is two or more, the structures of the field plate metal window patterns are the same;
or, the structure of at least one field plate metal window pattern is different from that of other field plate metal window patterns;
or, the structures of the field plate metal window patterns are different.
6. The method of manufacturing an asymmetric surface channel field effect transistor as claimed in claim 5, wherein: no voltage is applied to the field plate metal layer;
alternatively, a separate voltage is applied.
7. The method of manufacturing an asymmetric surface channel field effect transistor as claimed in claim 1, wherein: the metal mask layer is the same as the metal types of the source metal layer and the drain metal layer;
or the metal mask layer is different from the metal types of the source metal layer and the drain metal layer.
8. The method of manufacturing an asymmetric surface channel field effect transistor as claimed in claim 1, wherein: the metal mask layer, the source metal layer, the drain metal layer, the gate metal layer and the field plate metal layer are all single-layer metals;
or, both are multilayer metals;
or at least one single layer metal and one multi-layer metal.
9. A power device, characterized by: prepared by the process of any one of claims 1 to 8.
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