KR20100000586A - Making mathod trainsistor - Google Patents
Making mathod trainsistor Download PDFInfo
- Publication number
- KR20100000586A KR20100000586A KR1020080060143A KR20080060143A KR20100000586A KR 20100000586 A KR20100000586 A KR 20100000586A KR 1020080060143 A KR1020080060143 A KR 1020080060143A KR 20080060143 A KR20080060143 A KR 20080060143A KR 20100000586 A KR20100000586 A KR 20100000586A
- Authority
- KR
- South Korea
- Prior art keywords
- film
- etching
- insulating film
- gate
- high frequency
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 26
- 230000001681 protective effect Effects 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 20
- 230000005669 field effect Effects 0.000 claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 238000001312 dry etching Methods 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims 1
- 230000005684 electric field Effects 0.000 description 4
- 230000005685 electric field effect Effects 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000001413 cellular effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000609 electron-beam lithography Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical group ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
Abstract
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a field effect transistor for an ultra-high frequency integrated circuit device, and more particularly, to depositing a first insulating film on a semiconductor substrate, forming a constant photoresist pattern on the first insulating film, and Forming a protective film on the upper portion, forming a second insulating film on the protective film to have a width equal to a gate length formed later, and forming a second insulating film on the lower portion of the second insulating film etched after the step. Selectively etching the protective film having the same width as the etched second insulating film, etching all the remaining portions of the first oxide film and the second oxide film exposed to the lower portion of the protective film after the step, and etching the recess after the step Forming a groove B on the semiconductor substrate, and injecting a gate metal into the groove B to form a T-type gate. And removing the remaining portions except the first oxide film on the semiconductor substrate around the T-type gate and exposing the T-type gate to the top. It is a very useful and effective invention to improve the high frequency characteristics by improving the flow of current because the resistance is reduced by reducing the length.
Description
BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an ultra-high frequency integrated circuit device (MMIC), and in particular, reduces the resistance by reducing the length of the gate electrode for transistors used in the ultra-high frequency integrated circuit, thereby improving the flow of current to improve the high frequency characteristics.
The present invention relates to a field effect transistor (FET) fabrication method of an ultra-high frequency integrated circuit (MMIC) device, which is intended to be improved. Various manufacturing techniques are used for the method, and in recent years, a metal oxide semiconductor field effect transistor (MOSFET), in which an oxide film is coated on a semiconductor substrate to produce an electric field effect, and an electron moving speed is higher than that of a silicon substrate. Mess type that produces electric field effect using double gallium arsenide (GaAs) as substrate
Metal semiconductor field effect transistors (MESFETs) and insulator gate field effect transistors (IGEFTs) are used.
As described above, in the method of manufacturing a semiconductor device, a high frequency integrated circuit (MMIC), which is widely applied to wireless communication such as a cellular phone and satellite communication, is frequently used. Type electric field
Effect transistors (MESFETs) and the like have high frequency characteristics, and thus they are mainly used. Many efforts have been made to reduce the length of gate electrodes in order to improve the high frequency characteristics of these transistors.
In addition, in order to improve the high frequency characteristics of the scalpel type field effect transistor and the ultra-high speed electronic transistor, it is very important to improve the high frequency characteristics because the length of the transistor is reduced and the resistance is increased to increase the operation speed. Using a -Line or g-Line photolithography (Mask Contact Aligner), it was very difficult to form a pattern for etching the gate to less than 0.6㎛.
Therefore, in order to form a gate length of 0.25 μm or less, a method of forming a gate of 0.25 μm or less using an electron beam lithography or a stepper, which is very precise and expensive equipment, is conventionally used. It is adopted. As described above, the equipment for forming the gate length of 0.25 μm or less is very expensive, and even if such equipment is used, the gate pattern must be accurately formed to be 0.25 μm or less, so that the manufacturing process takes a lot of time and productivity is reduced. There was a problem.
You should be able to understand electric fields and transistors.
BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a device for a microwave integrated circuit (MMIC), and more particularly, to reduce the resistance by reducing the length of a gate electrode for a transistor used in a microwave integrated circuit, thereby improving the flow of current to improve the high frequency characteristics.
A field effect transistor (FET) manufacturing method of an integrated circuit (MMIC) device.
In general, there are many kinds of semiconductor devices, and various manufacturing techniques are used to configure transistors, capacitors, etc. formed in the semiconductor device, and in recent years, MOS is formed to apply an oxide film on a semiconductor substrate to produce an electric field effect. Metal oxide semiconductor field effect (MOSFET)
transistors and electrons move six times faster than silicon.
A scalpel type electric field using gallium arsenide (GaAs) as a substrate to produce an electric field effect
Metal semiconductor field effect transistors (MESFETs) and insulator gate field effect transistors (IGEFTs) are used.
As described above, in the method of manufacturing a semiconductor device, a high frequency integrated circuit (MMIC), which is widely applied to wireless communication such as a cellular phone and satellite communication, is frequently used. Type electric field
Effect transistors (MESFETs), etc., because of their high frequency characteristics, are often used a lot, and much effort has been made to reduce the length of gate electrodes in order to improve the high frequency characteristics of these transistors.
In addition, in order to improve the high frequency characteristics of the scalpel type field effect transistor and the ultra-high speed electronic transistor, it is very important to improve the high frequency characteristics because the length of the transistor is reduced and the resistance is increased to increase the operation speed. It was very difficult to form a pattern for etching the gate to 0.6 μm or less using -Line or g-Line mask contact aligner. Therefore, the gate length is conventionally formed to be 0.25 μm or less. In order to achieve this, a gate of 0.25 μm or less is formed by using electron beam lithography or stepper, which is very precise and expensive equipment.
Adopting the law, but. As described above, the equipment for forming the gate length of 0.25 μm or less is very expensive, and even if such equipment is used, the gate pattern must be accurately formed to be 0.25 μm or less, so that the manufacturing process takes a lot of time and productivity is reduced. There was a problem.
The objective is to deposit a first insulating film on a semiconductor substrate, to form a predetermined photoresist pattern on the first insulating film, to form a protective film on the photoresist pattern, and a second insulating film on the protective film. Forming a second insulating film to have the same width as a later formed gate length, and selectively etching the passivation film under the etched second insulating film to the same width as the etched second insulating film. And etching the remaining portions of the first oxide film and the second oxide film exposed to the lower portion of the protective film after the step, and forming a groove B on the semiconductor substrate by recess etching after the step; A metal for gate is implanted into B to form a T-type gate, and the remainder except for the first oxide film on the semiconductor substrate around the T-type gate. By removing the part exposing the T-shaped gate with an upper
It is achieved by providing a method for manufacturing a field effect transistor of the ultra-high frequency integrated circuit device, characterized in that the first and second oxide film is silicon nitride (Si 3 N 4) or silicon oxide (SiO 2), Preferably, the protective film is formed of aluminum (Al). As shown in FIG. 2, the gap between the photoresist patterns is 0.6 μm, and the gap A of the second oxide film shown in FIG. 4 is It is to be formed to 0.25㎛ corresponding to the length of the gate.
The second oxide layer is etched by RIE dry etching using Freon (CF 4) gas and oxygen (O 2), and the method of selectively etching the protective layer is boron trichloride (BCl 3) gas. RIE dry etching is used.
Hereinafter, the manufacturing process according to the present invention will be described in detail with reference to the accompanying drawings.
First, as shown in FIGS. 1 to 3, a first oxide film 20 made of silicon nitride (SI 3 N 4) or silicon oxide (SiO 2) is deposited on the semiconductor substrate 10, and then, Deposition of the photosensitive film pattern 30 having an interval of about 0.6㎛,
FIG. 3 is a view showing a state in which a protective film 40 made of aluminum (Al), which serves as a protective role, is stacked on the photosensitive film pattern 30. As shown in FIG. 4, after the step, silicon nitride (Si 3 N 4) or in order to adjust the gap of the T-type gate formed to have a predetermined distance A on the protective film 40 to have a 0.25 μm or silicon
2 is a view showing a state of stacking a second oxide film 50 for controlling a gap formed of oxide (SiO 2).
In addition, FIG. 5 is a view showing a state in which a portion of the second oxide film 50 is etched by RiE dry etching using Freon (CF 4) gas and oxygen (O 2) vertically. 6 shows that the protective film 40 at the bottom of the second oxide film 50 etched after the step is selectively boron trichloride (BCl 3) having the same width as that of the second oxide film 50 for adjusting the gap. RIE dry etching using gas
In addition, FIG. 7 shows a state in which both the first oxide film 20 and the remaining portions of the second oxide film 50 exposed to the lower portion of the protective film 40 are etched after the step. FIG. 8 is a view showing a state in which a groove B is formed on the semiconductor substrate 10 by recess etching after the above step so that a T-type gate can be installed on the semiconductor substrate 10. FIG. Similarly, a gate metal is injected into the groove B to form a T-type gate 60, and FIG. 10 shows the first oxide film 20 on the semiconductor substrate 1 around the T-type gate 60. Lift-off ball for remaining part
The figure shows a state in which the T-type gate 60 is exposed to the upper side by removing the positive electrode.
Therefore, when using the method for manufacturing a field effect transistor of the ultra-high frequency integrated circuit device according to the present invention as described above, it is formed to have a gap of about 0.6㎛ on the photosensitive film pattern, the T-type gate is formed on the photosensitive film pattern Forming a protective film on the portion and forming a second oxide film that can adjust the gap in the groove portion of the protective film, while adjusting the interval (A) to etch the groove portion so that the interval of the oxide film is about 0.25㎛, the pattern of the gate (photosensitive film T-type of 0.25 µm due to the spacer role of the oxide film for adjusting the spacing despite the use of a conventional photolithography apparatus having a masking interval of pattern) of about 0.6 µm
It is a very useful and effective invention to simplify the gate and reduce the cost and increase productivity due to the use of expensive equipment.
A method for manufacturing a field effect transistor for an ultra high frequency integrated circuit device, comprising: depositing a first insulating film on a semiconductor substrate, forming a constant photoresist pattern on the first insulating film, and forming a protective film on the photoresist pattern Forming a second insulating film having a width equal to a gate length formed after the second insulating film is laminated on the protective film; and etching the protective film under the second insulating film etched after the step. Selectively etching the same width as that of the second insulating film, etching the remaining portions of the first oxide film and the second oxide film exposed to the lower portion of the protective film after the step, and performing a recess etching after the step, on the semiconductor substrate. Forming a groove B, and injecting a gate metal into the groove B to form a T-type gate, and the main portion of the T-type gate And removing the remaining portion except the first oxide layer on the semiconductor substrate, exposing the T-type gate to the top.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020080060143A KR20100000586A (en) | 2008-06-25 | 2008-06-25 | Making mathod trainsistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020080060143A KR20100000586A (en) | 2008-06-25 | 2008-06-25 | Making mathod trainsistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20100000586A true KR20100000586A (en) | 2010-01-06 |
Family
ID=41810966
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020080060143A KR20100000586A (en) | 2008-06-25 | 2008-06-25 | Making mathod trainsistor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20100000586A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9966799B2 (en) | 2011-05-17 | 2018-05-08 | Samsung Electronics Co., Ltd. | Apparatus for and method of protecting wireless-coupled power devices from overvoltage, overcurrent, and overtemperature using hysteresis |
| KR20190016162A (en) | 2017-08-07 | 2019-02-18 | 경수 예 | Washing machine water control device |
-
2008
- 2008-06-25 KR KR1020080060143A patent/KR20100000586A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9966799B2 (en) | 2011-05-17 | 2018-05-08 | Samsung Electronics Co., Ltd. | Apparatus for and method of protecting wireless-coupled power devices from overvoltage, overcurrent, and overtemperature using hysteresis |
| KR20190016162A (en) | 2017-08-07 | 2019-02-18 | 경수 예 | Washing machine water control device |
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| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E601 | Decision to refuse application |