CN111384166A - Semiconductor device and semiconductor device manufacturing method - Google Patents
Semiconductor device and semiconductor device manufacturing method Download PDFInfo
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- CN111384166A CN111384166A CN201811647961.6A CN201811647961A CN111384166A CN 111384166 A CN111384166 A CN 111384166A CN 201811647961 A CN201811647961 A CN 201811647961A CN 111384166 A CN111384166 A CN 111384166A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 80
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 43
- 238000002161 passivation Methods 0.000 claims abstract description 80
- 230000004888 barrier function Effects 0.000 claims abstract description 70
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims description 37
- 230000008569 process Effects 0.000 claims description 20
- 230000005533 two-dimensional electron gas Effects 0.000 claims description 10
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 abstract description 18
- 239000000463 material Substances 0.000 description 15
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- 238000010899 nucleation Methods 0.000 description 13
- 238000010586 diagram Methods 0.000 description 10
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- 239000007769 metal material Substances 0.000 description 3
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- 238000000151 deposition Methods 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Abstract
The application provides a semiconductor device and a manufacturing method of the semiconductor device, and relates to the technical field of semiconductors. Wherein, the semiconductor device includes: a substrate; a channel layer fabricated on a substrate; a barrier layer manufactured on one surface of the channel layer far away from the substrate; a stress enhancement type passivation layer is manufactured on one surface of the barrier layer away from the channel layer; an electrode made on the basis of a passivation layer, wherein the electrode comprises a source electrode, a drain electrode and a grid electrode positioned between the source electrode and the drain electrode; and at least one groove structure which is arranged between the grid electrode and the drain electrode and is formed on the basis of the stress enhancement type passivation layer, wherein the distance between the groove structure and the grid electrode is smaller than that between the groove structure and the drain electrode. With the above arrangement, the problems of low breakdown voltage, high manufacturing complexity, and poor high-frequency power characteristics of the conventional semiconductor device can be solved.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor device and a method for manufacturing the semiconductor device.
Background
Nitride semiconductor materials, such as GaN, have High saturated Electron mobility rates, High breakdown voltages and wide forbidden bandwidths, and due to these characteristics, nitride-based High Electron Mobility Transistor (HEMT) devices attract the attention of researchers and semiconductor manufacturers. Among them, GaN HEMT devices have a very wide application prospect in the fields of high-speed, high-efficiency, high-frequency communication and power electronics in the next 20 years.
The withstand voltage value in an actual GaN HEMT can only reach 20-30% of a theoretical value generally, because the phenomenon of electric field concentration occurs under the condition that high voltage is applied to a drain terminal at the edge of a grid electrode close to a drain electrode, and the high electric field in a local area can cause high leakage and even material breakdown, so that the breakdown voltage of a device is reduced. Therefore, breakdown generally occurs at the edge of the gate near the drain side in GaN HEMT devices. Meanwhile, along with the increase of time, the high electric field can also cause the degradation and denaturation of a dielectric layer or a semiconductor material layer on the surface of the device, so that the working reliability of the device is influenced, and the service life of the device is shortened.
Therefore, in the structural design and process development of an actual device, various methods are always adopted to reduce the strong electric field near the gate of the device so as to improve the breakdown voltage of the device and obtain excellent reliability. For example, a field plate is placed on the side of the gate near the drain end, as shown in fig. 1. The field plate is usually connected with the source electrode or the grid electrode, an additional potential is generated in the grid-drain region, and an electric field peak near the edge of the grid electrode close to the drain end can be effectively stabilized, so that the breakdown voltage of the device and the reliability of the device are improved.
However, the above method of adding a field plate has many disadvantages. For example, compared with a process without a field plate, the manufacturing process needs to add process steps such as photolithography, metal deposition, etching, and the like, which increases the manufacturing complexity, increases the cost, and also reduces the yield. In order to effectively increase the breakdown voltage, a field plate having a certain length is generally provided, which causes a large parasitic capacitance and affects the high-frequency power characteristics of the device.
Therefore, it is an urgent technical problem to improve a technical solution that can improve the breakdown voltage of a semiconductor device without the problems of high manufacturing complexity and poor high-frequency power characteristics.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device, which can solve the problems of low breakdown voltage, high manufacturing complexity and poor high-frequency power characteristics of the conventional semiconductor device.
In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:
a semiconductor device, comprising:
a substrate;
a channel layer fabricated on the substrate;
a barrier layer manufactured on one surface of the channel layer far away from the substrate;
the passivation layer is manufactured on one surface of the barrier layer, which is far away from the channel layer;
an electrode made on the basis of the passivation layer, wherein the electrode comprises a source electrode, a drain electrode and a grid electrode positioned between the source electrode and the drain electrode;
the passivation layer is a stress enhanced passivation layer;
and at least one groove structure which is arranged between the grid electrode and the drain electrode and is opened based on the stress enhancement type passivation layer, wherein the distance between the groove structure and the grid electrode is smaller than that between the groove structure and the drain electrode.
In a preferred option of the embodiment of the present application, in the semiconductor device, the two-dimensional electron gas at the interface between the barrier layer and the channel layer corresponding to the position of the groove structure is at least partially depleted.
In a preferred option of the embodiment of the present application, in the semiconductor device, a cross-sectional area of a portion close to the barrier layer in the groove structure is smaller than a cross-sectional area of a portion far from the barrier layer.
In an embodiment of the present invention, in the semiconductor device, in the cross-sectional structure formed along the thickness direction of the passivation layer, a first included angle is formed between one side of the groove structure close to the gate and the thickness direction, and a second included angle is formed between one side of the groove structure far away from the gate and the thickness direction, and the first included angle is equal to the second included angle.
In an embodiment of the present invention, in the semiconductor device, in the cross-sectional structure formed along the thickness direction of the passivation layer, a first included angle is formed between one side of the groove structure close to the gate and the thickness direction, and a second included angle is formed between one side of the groove structure far away from the gate and the thickness direction, and the first included angle is smaller than the second included angle.
In a preferred option of the embodiment of the present application, in the above semiconductor device, in a cross-sectional structure formed along a thickness direction of the passivation layer, the groove structure includes a first side edge close to the gate, a second side edge far away from the gate, and a bottom edge connected between the first side edge and the second side edge, where the bottom edge is not parallel to the barrier layer, the first side edge forms a first included angle with the thickness direction, the second side edge forms a second included angle with the thickness direction, and the bottom edge forms a third included angle with the thickness direction, where the first included angle is equal to the second included angle and smaller than the third included angle.
In a preferred option of the embodiment of the present invention, in the semiconductor device, the number of the groove structures is two or more, and a distance between each groove structure and the gate is smaller than a distance between each groove structure and the drain.
In a preferred option of this embodiment, in the semiconductor device, the groove structure extends from a surface of the passivation layer away from the barrier layer to an inside of the passivation layer; or
The groove structure extends from a surface of the passivation layer away from the barrier layer to an interface of the passivation layer and the barrier layer; or
The groove structure penetrates through the passivation layer from a surface of the passivation layer far away from the barrier layer and extends to the inner part of the barrier layer.
On the basis, the embodiment of the present application further provides a semiconductor device manufacturing method for manufacturing the semiconductor device, where the method includes:
providing a substrate, and manufacturing a channel layer on the substrate;
manufacturing a barrier layer on one surface of the channel layer far away from the substrate;
manufacturing a stress enhancement type passivation layer on one surface of the barrier layer, which is far away from the channel layer;
opening a source electrode groove, a drain electrode groove and a grid electrode groove which are respectively used for manufacturing a source electrode, a drain electrode and a grid electrode positioned between the source electrode and the drain electrode on the basis of the surface, far away from the barrier layer, of the stress enhancement type passivation layer;
and a groove structure is arranged on the surface of the passivation layer away from the barrier layer, and the distance between the groove structure and the grid groove is smaller than the distance between the groove structure and the drain groove.
In a preferred option of the embodiment of the present application, in the method for manufacturing a semiconductor device, the stress-enhanced passivation layer is grown by a high frequency PECVD process.
In a preferred option of the embodiment of the present application, in the method for manufacturing a semiconductor device, a cross-sectional area of a portion close to the barrier layer in the groove structure is smaller than a cross-sectional area of a portion far from the barrier layer.
In a preferred option of the embodiment of the present invention, in the method for manufacturing a semiconductor device, two or more groove structures are formed on a surface of the passivation layer away from the barrier layer, and a distance between each groove structure and the gate is smaller than a distance between each groove structure and the drain.
The application provides a semiconductor device and a semiconductor device manufacturing method, set up the groove structure that is located between grid and the drain electrode and the distance between this grid is less than and the distance between the drain electrode based on stress enhancement mode passivation layer to form the phenomenon that stress enhancement and concentration at the border position of groove structure, thus reduce the concentration of the two-dimensional electron gas (2DEG) that the barrier layer of this position below and the interface of channel layer formed, and then reduce the electric field intensity of this position department, on the basis that the complexity is lower and the high frequency power characteristic is not influenced in the manufacturing, improve the breakdown voltage of device, have high practical value.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a schematic diagram of a prior art semiconductor device including a field plate.
Fig. 2 is a schematic structural diagram of a semiconductor device according to an embodiment of the present application.
Fig. 3 is a schematic structural diagram of a semiconductor device (having a two-groove structure) according to an embodiment of the present application.
Fig. 4 is a schematic structural diagram of a semiconductor device (where the first included angle is equal to the second included angle) provided in this embodiment of the present application.
Fig. 5 is another schematic structural diagram of a semiconductor device (where the first included angle is equal to the second included angle) provided in this embodiment of the present application.
Fig. 6 is a schematic structural diagram of a semiconductor device (where the first included angle is smaller than the second included angle) according to an embodiment of the present application.
Fig. 7 is another schematic structural diagram of a semiconductor device (the first included angle is smaller than the second included angle) according to an embodiment of the present disclosure.
Fig. 8 is a schematic structural diagram of a semiconductor device (having a first side, a second side, and a bottom) according to an embodiment of the present disclosure.
Fig. 9 is a schematic structural diagram of a semiconductor device (having a plurality of side edges and a bottom edge) provided in an embodiment of the present application.
Fig. 10 is a schematic structural diagram of a semiconductor device (including a nucleation layer and a buffer layer) according to an embodiment of the present disclosure.
Fig. 11 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application.
Icon: 100-a semiconductor device; 110-a substrate; 121-a nucleation layer; 123-a buffer layer; 130-a channel layer; 140-barrier layer; 150-a passivation layer; 161-source; 163-drain; 165-a gate; 170-groove structure; l1-first side; l2-second side edge; l3-bottom edge.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. In the description of the present application, the terms "first," "second," "third," "fourth," and the like are used merely to distinguish one description from another, and are not to be construed as merely or implying relative importance.
As shown in fig. 2, the present embodiment provides a semiconductor device 100 that may include a substrate 110, a channel layer 130, a barrier layer 140, a passivation layer 150, an electrode, and a groove structure 170.
In detail, the channel layer 130 is fabricated on the substrate 110. The barrier layer 140 is fabricated on a side of the channel layer 130 remote from the substrate 110, wherein the channel layer 130 and the barrier layer 140 constitute a semiconductor heterostructure to form a high concentration of a two-dimensional electron gas (2DEG) at an interface of the channel layer 130 and the barrier layer 140. The passivation layer 150 is formed on a side of the barrier layer 140 away from the channel layer 130, and the passivation layer 150 is a stress enhanced passivation layer 150. The electrode is formed based on the passivation layer 150, and includes a source electrode 161, a drain electrode 163, and a gate electrode 165 between the source electrode 161 and the drain electrode 163. The groove structure 170 is located between the gate electrode 165 and the drain electrode 163 and is formed by opening the passivation layer 150, and a distance between the groove structure 170 and the gate electrode 165 is smaller than a distance between the groove structure and the drain electrode 163.
The stress which is stronger and more concentrated than the traditional structure can be formed at the edge position of the groove structure 170 by forming a groove with a certain shape in the stress enhancement type passivation layer 150, and the stress is increased and is intensively utilized to partially exhaust or exhaust the concentration of two-dimensional electron gas (2DEG) formed at the interface of the barrier layer 140 and the channel layer 130 below the position, so that the electric field intensity (namely, the electric field intensity at the position corresponding to the grid 165) at the position is reduced, the breakdown voltage of the device is improved on the basis that the manufacturing complexity is low and the high-frequency power characteristic is not influenced, and the high-frequency power semiconductor device has extremely high practical value.
Optionally, the lattice size difference between the passivation layer 150 and the barrier layer 140 is controlled to achieve a stress enhanced passivation layer 150. Preferably, the stress enhanced passivation layer 150 is a stress enhanced SiN layer. For example, a high frequency PECVD growth process may be used to implement a SiN film layer with a relatively strong stress.
The groove structure 170 is arranged to control the position and strength of stress concentration, so that the two-dimensional electron gas formed at the interface between the barrier layer 140 and the channel layer 130 under the groove structure 170 is effectively used up or partially used up.
Optionally, the number of the groove structures 170 is not limited, and may be selected according to practical application requirements, for example, requirements for breakdown voltage and complexity of the process may be considered comprehensively. Specifically, in an alternative example, the groove structure 170 may be one if the requirement for the breakdown voltage is not high (i.e., the reduction degree of the concentration of the two-dimensional electron gas (2DEG) is not high). For another example, in another alternative example, if the requirement for the complexity of the process is not high (i.e. the reduction degree of the concentration of the two-dimensional electron gas (2DEG) is high), the number of the groove structures 170 may be two or more, as shown in fig. 3.
The specific shape of the groove structure 170 is not limited, and may be selected according to the actual application requirement. In the present embodiment, in order to make the stress formed by the groove structure 170 more concentrated, in the groove structure 170, the cross-sectional area of a portion close to the barrier layer 140 is smaller than that of a portion far from the barrier layer 140.
For example, in an alternative example, referring to fig. 4 and 5, in the cross-sectional structure formed along the thickness direction of the passivation layer 150, a side of the groove structure 170 close to the gate electrode 165 forms a first included angle with the thickness direction, a side far away from the gate electrode 165 forms a second included angle with the thickness direction, and the first included angle is equal to the second included angle, where the first included angle is α, and the second included angle is β.
That is, in the cross-sectional structure formed in the thickness direction of the passivation layer 150, the cross-section of the groove structure 170 may be an isosceles trapezoid (as shown in fig. 4) or an isosceles triangle (as shown in fig. 5).
For another example, in another alternative example, with reference to fig. 6 and 7, in the cross-sectional structure formed along the thickness direction of the passivation layer 150, a side of the groove structure 170 close to the gate 165 forms a first included angle with the thickness direction, a side of the groove structure away from the gate 165 forms a second included angle with the thickness direction, and the first included angle is smaller than the second included angle, where the first included angle is α, and the second included angle is β.
That is, in the cross-sectional structure formed in the thickness direction of the passivation layer 150, the cross-section of the groove structure 170 may be a trapezoid (as shown in fig. 6) or a triangle (as shown in fig. 7) having no isosceles shape. By setting the first included angle to be smaller than the second included angle, the generated stress can be further concentrated at a position close to the gate electrode 165, so that the two-dimensional electron gas at the position corresponding to the gate electrode 165 is further suppressed, and the breakdown voltage of the semiconductor device 100 is further improved.
For another example, in an alternative example, with reference to fig. 8, in a cross-sectional structure formed along a thickness direction of the passivation layer 150, the groove structure 170 includes a first side L1 close to the gate 165, a second side L2 far away from the gate 165, and a bottom L3 connected between the first side L1 and the second side L2, where the bottom L3 is not parallel to the barrier layer 140, the first side L1 forms a first included angle with the thickness direction, the second side L2 forms a second included angle with the thickness direction, and the bottom L3 forms a third included angle with the thickness direction, where the first included angle is equal to the second included angle, and the first included angle is smaller than the third included angle, where the first included angle is α, the second included angle is β, and the third included angle is θ.
In the example shown in fig. 8, since the stress formed by the groove structure 170 is concentrated further near the corresponding position of the gate 165, the breakdown voltage of the semiconductor device 100 can be further improved, and the on-resistance can be kept low, so that the problem that the semiconductor device 100 consumes more power in the using process due to the high on-resistance can be avoided, and the semiconductor device has higher economic characteristics.
It should be noted that the groove structure 170 may further include more shapes in the cross-sectional structure formed along the thickness direction of the passivation layer 150, for example, in the structure shown in fig. 9, the groove structure 170 may further be formed by more side edges or bottom edges, which is not particularly limited herein.
Optionally, when the groove structure 170 is formed on a surface of the passivation layer 150 away from the barrier layer 140, a depth of the groove structure 170 is not limited, and may be selected according to practical application requirements.
For example, in an alternative example, the groove structure 170 extends from a surface of the passivation layer 150 remote from the barrier layer 140 to an interior of the passivation layer 150. That is, an end of the groove structure 170 near the substrate 110 is located inside the passivation layer 150.
For another example, in another alternative example, the groove structure 170 extends from a surface of the passivation layer 150 away from the barrier layer 140 to an interface of the passivation layer 150 and the barrier layer 140. That is, an end of the groove structure 170 near the substrate 110 is located at an interface of the passivation layer 150 and the barrier layer 140.
For another example, in another alternative example, the groove structure 170 extends through the passivation layer 150 from a surface of the passivation layer 150 away from the barrier layer 140 and into the interior of the barrier layer 140. That is, an end of the recess structure 170 near the substrate 110 is located inside the barrier layer 140.
Further, in order to achieve material matching (e.g., lattice constant), in this embodiment, a matching layer may be formed between the substrate 110 and the channel layer 130.
The specific structure of the matching layer is not limited, and may be selected according to the actual application requirements, for example, the matching layer may have a one-layer structure or a two-layer structure.
For another example, in another alternative example, in conjunction with fig. 10, the matching layer may include a nucleation layer 121 and a buffer layer 123. Specifically, the nucleation layer 121 may be formed on the substrate 110, the buffer layer 123 may be formed on a side of the nucleation layer 121 away from the substrate 110, and the channel layer 130 may be formed on a side of the buffer layer 123 away from the nucleation layer 121.
For another example, in an alternative example, the matching layer may include the nucleation layer 121. Specifically, the nucleation layer 121 may be formed on the substrate 110, and the channel layer 130 may be formed on a surface of the nucleation layer 121 away from the substrate 110.
For another example, in another alternative example, the matching layer may include a buffer layer 123. Specifically, a buffer layer 123 may be formed on the substrate 110, and the channel layer 130 may be formed on a surface of the buffer layer 123 away from the substrate 110.
Optionally, in this embodiment, the material of each layered structure included in the semiconductor device 100 is not limited, and may be selected according to the actual application requirement.
For example, the material of the substrate 110 may include, but is not limited to, Si, SiC, sapphire, or other materials. The material of the nucleation layer 121 may include, but is not limited to, GaN, AlN or other nitride. The material of the buffer layer 123 may include, but is not limited to, GaN, AlN, or other nitride. The material of the channel layer 130 may include, but is not limited to, GaN, InAlN, or other semiconductor materials. The material of the barrier layer 140 may include, but is not limited to, AlGaN, InAlN, or other semiconductor materials. The passivation layer 150 may be SiN.
With reference to fig. 11, the present embodiment also provides a method for manufacturing a semiconductor device, which is used to prepare the semiconductor device 100 described above. The method for manufacturing the semiconductor device may include steps S110 to S150, which are described in detail below.
In step S110, a substrate 110 is provided, and a channel layer 130 is formed on the substrate 110.
In this embodiment, a substrate 110 may be obtained first, and the substrate 110 may be cleaned. Then, the channel layer 130 is formed on the substrate 110 after the cleaning process is completed. For example, the channel layer 130 may be formed by depositing GaN, InAlN, or other semiconductor material on the substrate 110.
A nucleation layer 121 may be formed on the substrate 110 after the cleaning process is completed, and then a buffer layer 123 may be formed on a surface of the nucleation layer 121 away from the substrate 110, and the channel layer 130 may be formed on a surface of the buffer layer 123 away from the nucleation layer 121.
Step S120, a barrier layer 140 is fabricated on a surface of the channel layer 130 away from the substrate 110.
In this embodiment, after the channel layer 130 is formed, the barrier layer 140 may be formed on a surface of the channel layer 130 away from the substrate 110 (or the buffer layer 123). For example, AlGaN, InAlN, or other semiconductor materials may be deposited on the channel layer 130 to form the barrier layer 140.
In step S130, a passivation layer 150 is formed on a surface of the barrier layer 140 away from the channel layer 130.
In this embodiment, after the barrier layer 140 is formed, the stress enhanced passivation layer 150 may be formed on a side of the barrier layer 140 away from the channel layer 130. For example, SiN may be grown on the barrier layer 140 by a high frequency PECVD process to form the passivation layer 150.
Step S140, a source trench, a drain trench and a gate trench are opened on the passivation layer 150 on the side away from the barrier layer 140, wherein the source trench, the drain trench and the gate trench are respectively used for manufacturing the source 161, the drain 163 and the gate 165 located between the source 161 and the drain 163.
In this embodiment, after the passivation layer 150 is formed, a source trench, a drain trench and a gate trench may be opened based on the passivation layer 150. The gate trench is located between the source trench and the drain trench, and a distance between the gate trench and the source trench may be smaller than a distance between the gate trench and the drain trench.
Specifically, the source trenches are used to deposit a metal material to form the source electrode 161 of the semiconductor device 100. The drain trench is used to deposit a metal material to form the drain 163 of the semiconductor device 100. The gate trenches are used to deposit a metal material to form the gate 165 of the semiconductor device 100. That is, after performing step S140, the semiconductor device manufacturing method further includes a step of fabricating the source electrode 161, the drain electrode 163, and the gate electrode 165.
In step S150, a groove structure 170 is formed on a surface of the passivation layer 150 away from the barrier layer 140, and a distance between the groove structure 170 and the gate trench is smaller than a distance between the groove structure and the drain trench.
In this embodiment, after the passivation layer 150 is formed, a groove structure 170 may be opened based on the passivation layer 150. It should be noted that, the step S150 and the step S140 do not have a specific sequence, for example, the groove structure 170 may be fabricated first, and then the source trench, the drain trench, and the gate trench may be fabricated; or the source electrode groove, the drain electrode groove and the grid electrode groove are firstly manufactured, and then the groove structure 170 is manufactured; the groove structure 170 may be formed in the same etching process as the source, drain, and gate trenches.
In this embodiment, the source trench, the drain trench, the gate trench and the groove structure 170 may be formed together by the same etching process to simplify the process, thereby further reducing the problems of high manufacturing cost and low manufacturing yield due to the complex process, and greatly improving the practical value of the manufacturing method of the semiconductor device.
The etching process is not limited, and may be selected according to practical application requirements, and for example, the etching process may include, but is not limited to, a plasma coupled etching method, a reactive ion etching method, a wet etching method, or the like.
Moreover, two or more groove structures 170 are formed on the passivation layer 150 on the side away from the barrier layer 140, and the distance between each groove structure 170 and the gate electrode 165 is smaller than the distance between each groove structure 170 and the drain electrode 163. For the specific structure and arrangement of the groove structure 170, reference may be made to the related contents of fig. 2 to 10, which are not described in detail herein.
It should be noted that, in the above steps, the deposition method of each layered structure is not limited, and for example, chemical processes such as chemical vapor deposition and electroplating, and physical processes such as physical vapor deposition (PVD or sputtering), evaporation, or spin coating may be included, but not limited thereto.
In summary, the passivation layer 150 is provided with the groove structure 170 which is located between the gate 165 and the drain 163 and the distance between the groove structure 170 and the gate 165 is smaller than the distance between the groove structure and the drain 163, so as to form a phenomenon of stress concentration at the edge position of the groove structure 170, thereby reducing the concentration of the two-dimensional electron gas (2DEG) formed at the interface between the barrier layer 140 and the channel layer 130 below the position, further reducing the electric field strength at the position, and improving the breakdown voltage of the device on the basis that the manufacturing complexity is low and the high-frequency power characteristic is not affected, thereby having a very high practical value. Secondly, the gate trench and the groove structure 170 are formed by the same etching process, so that the process can be simplified, the problems of high manufacturing cost and low manufacturing yield caused by complex process can be further reduced, and the practical value of the manufacturing method of the semiconductor device is greatly improved.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (12)
1. A semiconductor device, comprising:
a substrate;
a channel layer fabricated on the substrate;
a barrier layer manufactured on one surface of the channel layer far away from the substrate;
the passivation layer is manufactured on one surface of the barrier layer, which is far away from the channel layer;
an electrode made on the basis of the passivation layer, wherein the electrode comprises a source electrode, a drain electrode and a grid electrode positioned between the source electrode and the drain electrode;
the passivation layer is a stress enhanced passivation layer;
and at least one groove structure is formed between the grid electrode and the drain electrode based on the stress enhancement type passivation layer, and the distance between the groove structure and the grid electrode is smaller than that between the groove structure and the drain electrode.
2. The semiconductor device of claim 1, wherein the two-dimensional electron gas at the interface of the barrier layer and the channel layer corresponding to the location of the recessed structure is at least partially depleted.
3. The semiconductor device according to claim 1, wherein a cross-sectional area of a portion close to the barrier layer in the groove structure is smaller than a cross-sectional area of a portion away from the barrier layer.
4. The semiconductor device according to claim 3, wherein in the cross-sectional structure formed along the thickness direction of the stress-enhanced passivation layer, a side of the groove structure close to the gate forms a first angle with the thickness direction, a side of the groove structure far away from the gate forms a second angle with the thickness direction, and the first angle is equal to the second angle.
5. The semiconductor device according to claim 3, wherein in a cross-sectional structure formed along a thickness direction of the passivation layer, a side of the groove structure close to the gate forms a first angle with the thickness direction, a side of the groove structure away from the gate forms a second angle with the thickness direction, and the first angle is smaller than the second angle.
6. The semiconductor device according to claim 3, wherein in a cross-sectional structure formed in a thickness direction of the passivation layer, the groove structure includes a first side edge close to the gate electrode, a second side edge far from the gate electrode, and a bottom edge connected between the first side edge and the second side edge, the bottom edge is not parallel to the barrier layer, the first side edge forms a first included angle with the thickness direction, the second side edge forms a second included angle with the thickness direction, and the bottom edge forms a third included angle with the thickness direction, and the first included angle is equal to the second included angle and smaller than the third included angle.
7. The semiconductor device according to any one of claims 1 to 6, wherein the number of the groove structures is two or more, and a distance between each groove structure and the gate is smaller than a distance between each groove structure and the drain.
8. The semiconductor device according to any one of claims 1 to 6, wherein the groove structure extends from a surface of the passivation layer remote from the barrier layer to an interior of the passivation layer; or
The groove structure extends from a surface of the passivation layer away from the barrier layer to an interface of the passivation layer and the barrier layer; or
The groove structure penetrates through the passivation layer from a surface of the passivation layer far away from the barrier layer and extends to the inner part of the barrier layer.
9. A semiconductor device manufacturing method for manufacturing the semiconductor device according to any one of claims 1 to 9, the method comprising:
providing a substrate, and manufacturing a channel layer on the substrate;
manufacturing a barrier layer on one surface of the channel layer far away from the substrate;
manufacturing a stress enhancement type passivation layer on one surface of the barrier layer, which is far away from the channel layer;
opening a source electrode groove, a drain electrode groove and a grid electrode groove which are respectively used for manufacturing a source electrode, a drain electrode and a grid electrode positioned between the source electrode and the drain electrode on the basis of the surface, far away from the barrier layer, of the stress enhancement type passivation layer;
and a groove structure is arranged on the surface of the passivation layer away from the barrier layer, and the distance between the groove structure and the grid groove is smaller than the distance between the groove structure and the drain groove.
10. The method of manufacturing a semiconductor device according to claim 9, wherein the stress enhanced passivation layer is grown by a high frequency PECVD process.
11. The manufacturing method of a semiconductor device according to claim 9, wherein a cross-sectional area of a portion close to the barrier layer in the groove structure is smaller than a cross-sectional area of a portion away from the barrier layer.
12. The method for manufacturing a semiconductor device according to claim 9, wherein two or more groove structures are formed on a surface of the passivation layer away from the barrier layer, and a distance between each groove structure and the gate is smaller than a distance between each groove structure and the drain.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114566538A (en) * | 2022-03-03 | 2022-05-31 | 上海陆芯电子科技有限公司 | Epitaxial structure and semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104332498A (en) * | 2014-09-01 | 2015-02-04 | 苏州捷芯威半导体有限公司 | Oblique field plate power device and preparation method for oblique field plate power device |
| CN104412388A (en) * | 2012-05-23 | 2015-03-11 | Hrl实验室有限责任公司 | HEMT device and method of manufacturing the same |
| CN107210323A (en) * | 2015-03-30 | 2017-09-26 | 德州仪器公司 | normally-off III-nitride transistor |
| US20180026105A1 (en) * | 2013-08-01 | 2018-01-25 | Dynax Semiconductor, Inc. | Semiconductor device and method of manufacturing the same |
-
2018
- 2018-12-29 CN CN201811647961.6A patent/CN111384166A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104412388A (en) * | 2012-05-23 | 2015-03-11 | Hrl实验室有限责任公司 | HEMT device and method of manufacturing the same |
| US20180026105A1 (en) * | 2013-08-01 | 2018-01-25 | Dynax Semiconductor, Inc. | Semiconductor device and method of manufacturing the same |
| CN104332498A (en) * | 2014-09-01 | 2015-02-04 | 苏州捷芯威半导体有限公司 | Oblique field plate power device and preparation method for oblique field plate power device |
| CN107210323A (en) * | 2015-03-30 | 2017-09-26 | 德州仪器公司 | normally-off III-nitride transistor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114566538A (en) * | 2022-03-03 | 2022-05-31 | 上海陆芯电子科技有限公司 | Epitaxial structure and semiconductor device |
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Application publication date: 20200707 |