CN114566538A

CN114566538A - Epitaxial structure and semiconductor device

Info

Publication number: CN114566538A
Application number: CN202210206690.0A
Authority: CN
Inventors: 许洁; 张�杰
Original assignee: Shanghai Luxin Electronic Technology Co ltd
Current assignee: Shanghai Luxin Electronic Technology Co ltd
Priority date: 2022-03-03
Filing date: 2022-03-03
Publication date: 2022-05-31
Anticipated expiration: 2042-03-03
Also published as: CN114566538B

Abstract

The invention provides an epitaxial structure and a semiconductor device, wherein the epitaxial structure comprises: a passivation layer; the barrier layer is positioned on one side of the passivation layer; the surface of the barrier layer comprises at least one barrier layer groove, the at least one barrier layer groove is located in the structure setting area, and the opening of the at least one barrier layer groove faces the passivation layer. More electric field concentration areas can be introduced into the barrier layer grooves on the surface of the barrier layer, so that the strength of a peak electric field generated at the edge of the grid close to the drain due to an electric field concentration effect is weakened, the quantity of hot electrons which can be captured by the trap and are changed into at the edge of the grid due to the action of the peak electric field is reduced, the charge-discharge time of the trap during the switching on and off of the semiconductor device is shortened, namely, the time of opening and closing the semiconductor device is shortened, and the response speed of the device is improved.

Description

Epitaxial structure and semiconductor device

Technical Field

The invention relates to the technical field of transistors, in particular to an epitaxial structure and a semiconductor device.

Background

The gallium nitride semiconductor material has the obvious advantages of large forbidden band width, high electron saturation drift rate, high breakdown field strength, high temperature resistance and the like, has wide application prospect, and becomes a hotspot of current semiconductor industry research.

Gallium nitride High Electron Mobility Transistor (HEMT) is a semiconductor device formed by using two-dimensional electron gas at AlGaN/GaN heterojunction, and can be applied to the fields of high frequency, high voltage and high power. The gallium nitride high electron mobility transistor comprises an epitaxial layer and a passivation layer, a gate electrode, a source electrode and a drain electrode which are arranged on the epitaxial layer.

When voltage is applied to the drain electrode, an electric field with high electric field intensity is formed at the edge position of the grid electrode close to the drain electrode, electrons in a two-dimensional electron air channel corresponding to the edge position of the grid electrode close to the drain electrode can obtain more energy and become hot electrons, the hot electrons can be trapped by a deep trap energy level in a semiconductor device, more time is needed for trapping or releasing the hot electrons when the transistor is switched on and switched off, and the switching on and switching off time of the transistor is prolonged.

Disclosure of Invention

The invention provides an epitaxial structure and a semiconductor device, which are used for shortening the turn-on and turn-off time of the semiconductor device and improving the response speed of the semiconductor device.

According to an aspect of the present invention, there is provided an epitaxial structure comprising:

a passivation layer;

a barrier layer on one side of the passivation layer;

the surface of the barrier layer comprises at least one barrier layer groove, the at least one barrier layer groove is located in a structure setting area, and the opening of the at least one barrier layer groove faces the passivation layer.

Optionally, the depth of the barrier layer groove is smaller than the thickness of the barrier layer.

Optionally, an electrode layer is disposed on a side of the passivation layer away from the barrier layer, the electrode layer includes a gate, a source, and a drain, and the structure setting region is located between the gate and the drain.

Optionally, the barrier layer is located between the source electrode and the drain electrode, the gate is embedded in the passivation layer, and a surface of the gate away from the barrier layer is flush with a surface of the passivation layer away from the barrier layer.

Optionally, the epitaxial structure includes at least two barrier layer grooves, and the barrier layer grooves are arranged along a direction from the gate to the drain.

Optionally, the depth of the barrier layer groove near the gate is greater than the depth of the barrier layer groove near the drain.

Optionally, the density of the barrier layer grooves near the gate is greater than the density of the barrier layer grooves near the drain.

Optionally, the epitaxial structure further includes at least one of a nucleation layer, a buffer layer, and a channel layer on a side of the barrier layer away from the passivation layer.

Optionally, the filling material of the barrier layer groove is the same as the material of the passivation layer.

According to another aspect of the present invention, there is provided a semiconductor device comprising an epitaxial structure according to any one of the above.

The embodiment of the invention provides an epitaxial structure and a semiconductor device, wherein the epitaxial structure comprises: a passivation layer; the barrier layer is positioned on one side of the passivation layer; the barrier layer comprises at least one barrier layer groove, the at least one barrier layer groove is located in the structure setting area, and an opening of the at least one barrier layer groove faces the passivation layer. More electric field concentration areas can be introduced into at least one barrier layer groove formed in the barrier layer, so that the strength of a peak electric field generated by an electric field concentration effect at the edge of the grid close to the drain electrode is weakened, the quantity of hot electrons which can be captured by the trap and are changed into by the action of the peak electric field at the edge of the grid is reduced, the charge and discharge time of the trap during the switching on and off of the semiconductor device is shortened, the time for starting and switching off the semiconductor device is shortened, and the response speed of the device is improved.

It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present invention, nor do they necessarily limit the scope of the invention. Other features of the present invention will become apparent from the following description.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of an epitaxial structure according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of another epitaxial structure provided in an embodiment of the present invention;

fig. 3 is a schematic structural diagram of another epitaxial structure provided in an embodiment of the present invention;

fig. 4 is a distribution diagram of the electric field on the surface of the channel layer when the semiconductor device according to the embodiment of the present invention is turned on;

fig. 5 is a temperature distribution diagram of a channel layer when a semiconductor device according to an embodiment of the present invention is turned on;

FIG. 6 is a diagram illustrating the distribution of the trapped hot electrons in the buffer layer of a semiconductor device with different numbers of grooves in the barrier layer when the turn-on time is 0 second according to an embodiment of the present invention;

FIG. 7 is a graph showing the distribution of trapped hot electrons in buffer layers of a semiconductor device with different numbers of grooves in barrier layers when the semiconductor device is turned on for 0.11 us/sec according to an embodiment of the present invention;

FIG. 8 is a graph showing the distribution of trapped hot electrons in buffer layers of a semiconductor device with different numbers of grooves in barrier layers when the semiconductor device is turned on for 0.21 us/sec according to an embodiment of the present invention;

FIG. 9 is a graph of the rise time and fall time of a semiconductor device for different numbers of barrier layer recesses provided by embodiments of the present invention;

FIG. 10 is a bar graph of device rise and fall times for different numbers of barrier layer recesses provided by embodiments of the present invention;

fig. 11 is a schematic structural diagram of a double-pulse circuit diagram for measuring switching characteristics of a semiconductor device according to an embodiment of the present invention.

Detailed Description

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Fig. 1 is a schematic structural diagram of an epitaxial structure according to an embodiment of the present invention, and referring to fig. 1, the epitaxial structure includes:

a passivation layer 10;

a barrier layer 11, the barrier layer 11 being located on one side of the passivation layer 10;

the surface of the barrier layer 11 includes at least one barrier layer groove 111, the at least one barrier layer groove 111 is located in the structure defining area 112, and an opening of the at least one barrier layer groove 111 faces the passivation layer 10.

Optionally, the epitaxial structure further includes a substrate 12 and an electrode layer 13, where the substrate 12 is located on a side of the barrier layer 11 away from the passivation layer 10, and the electrode layer 13 is located on a side of the passivation layer 10 away from the barrier layer 11. An opening of the at least one barrier layer groove 111 is provided on a surface of the barrier layer 11 on a side close to the passivation layer 10 toward the passivation layer 10, i.e., the barrier layer groove 111.

Illustratively, the substrate 12 may include silicon carbide (SiC), the passivation layer 10 may include silicon nitride (SiN), the material of the barrier layer 11 may be aluminum gallium nitride (AlGaN), a higher AL composition in the barrier layer 11 is beneficial to reducing on-resistance, and Aluminum (AL) and gallium nitride (GaN) in the barrier layer 11 may be polarized, so as to prevent leakage of two-dimensional electron gas generated on the surface of the barrier layer 11 due to polarization, thereby improving the breakdown voltage of the epitaxial structure.

After the barrier layer 11 is formed, at least one barrier layer groove 111 may be etched through an etching process, in this embodiment, 15 barrier layer grooves 111 are exemplarily etched, and the size of the barrier layer groove 111 is equal to the distance between two adjacent barrier layer grooves 111. In other embodiments, the size of the barrier layer groove 111 and the distance between two adjacent barrier layer grooves 111 can be set according to requirements. The barrier layer groove 111 needs to be filled with a material, the filled material is an insulating material, and the material filled in the barrier layer groove 111 is not specifically limited in this embodiment.

When a voltage is applied to the drain, because the edge of the gate close to the drain bears an electric field concentration effect generated by biasing the gate and the drain, a peak electric field (i.e., an electric field with a larger electric field intensity) appears at the edge of the gate close to the drain in the channel, and further electrons at the edge of the gate obtain more energy due to the peak electric field and become hot electrons to be trapped by a trap (the epitaxial structure further includes a buffer layer 15 including a trap). When the epitaxial structure is applied to a semiconductor device, when the device bears large drain bias, hot electron generation transition in a channel is captured by a deep trap level, so that in the conducting process, when the drain voltage gradually drops to 0V, the device is not immediately conducted, and extra time is needed for the traps which capture the hot electrons to release the hot electrons. Similarly, when the device is turned on, the drain voltage rises from 0V to a turn-on voltage, which may be 50V for an exemplary turn-on voltage, the drain current does not saturate immediately, and trapping of hot electrons by the trap delays the time required for the drain current to saturate.

The plurality of barrier layer grooves 111 provided in this embodiment can introduce more electric field concentration regions at the lower right corner of the groove structure, and when the voltage applied to the drain is constant, the intensity of the electric field excited by the drain is constant, and when the concentration electric field region increases, the peak electric field intensity at the edge of the gate close to the drain is weakened, thereby reducing the number of hot electrons, shortening the time for the trap to trap or release the trapped hot electrons, and shortening the time for turning on and off the device. At least one extra electric field concentration area can be introduced into at least one barrier layer groove arranged on the barrier layer, the strength of a peak electric field generated by the electric field concentration effect at the edge of the grid close to the drain electrode is weakened, the quantity of hot electrons which can be captured by the trap and are changed into by the action of the peak electric field at the edge of the grid is further reduced, the charge and discharge time of the trap when the semiconductor device is switched on and switched off is further shortened, namely, the time of starting and switching off the semiconductor device is shortened, and the response speed of the device is improved.

With continued reference to fig. 1, optionally, the barrier layer recess 111 has a depth less than the thickness of the barrier layer 11.

The larger the depth of the barrier layer groove 111, the thinner the thickness of the structure setting region 112 of the barrier layer 11 becomes, resulting in an increase in the on-resistance of the barrier layer 11, which is disadvantageous for turning on and off the device, and therefore, the depth of the barrier layer groove 111 cannot be excessively large.

With continued reference to fig. 1, optionally, a side of the passivation layer 10 away from the barrier layer 11 is provided with an electrode layer 13, the electrode layer 13 includes a gate electrode 131, a source electrode 132, and a drain electrode 133, and the structure setting region 112 is located between the gate electrode 132 and the drain electrode 133.

In this embodiment, an alternative structure of the electrode layer 13 is exemplarily shown, the barrier layer 11 is located between the source electrode 132 and the drain electrode 133, the gate 131 is embedded in the passivation layer 10, and a surface of the gate 131 away from the barrier layer 11 is flush with a surface of the passivation layer 10 away from the barrier layer 11. The gate 131 includes a gate electrode 1311, a P-type channel 1312 and a field plate 1313, and the embedding of the gate 131 in the passivation layer 10 actually means that the portion of the gate 131 is embedded in the passivation layer 10, i.e., the gate electrode 1311 and the P-type channel 1312 are embedded in the passivation layer 10. The gate 131 uses Mg doped GaN as the P-type channel 1312 to deplete the channel at a gate voltage V, thereby achieving enhancement mode operation.

With continued reference to fig. 1, the epitaxial structure optionally includes at least two barrier layer recesses 111, the barrier layer recesses 111 being aligned in a direction from the gate 131 toward the drain 133. When a voltage is applied to the drain electrode 133, the electric field intensity at the edge of the gate electrode 1311 on the side of the gate electrode 1311 close to the drain electrode 133 is large, and therefore, in order to weaken the electric field at the edge of the gate electrode 1311, the structure setting region is disposed between the gate electrode 131 and the drain electrode 133, and the barrier layer recesses 111 are arranged in the direction from the gate electrode 131 toward the drain electrode 133, so that the peak value of the electric field at the edge of the gate electrode 1311 can be better weakened.

Fig. 2 is a schematic structural diagram of another epitaxial structure provided by an embodiment of the invention, and referring to fig. 2, optionally, the depth of the barrier layer groove 111 near the gate 131 is greater than the depth of the barrier layer groove 111 near the drain 133.

The depth of the barrier layer groove 111 near the gate 131 is greater than the depth of the barrier layer groove 111 near the drain 133, which can enhance the weakening effect on the electric field strength at the edge of the gate electrode 1311, further reduce the number of thermal electrons, and shorten the turn-on and turn-off time of the device.

Fig. 3 is a schematic structural diagram of another epitaxial structure according to an embodiment of the present invention, and referring to fig. 3, optionally, the density of the barrier layer recesses 111 near the gate 131 is greater than the density of the barrier layer recesses 111 near the drain 133. The barrier layer groove 111 can also enhance the weakening effect on the electric field intensity at the edge of the gate electrode 1311, and can also achieve the effects of reducing the number of hot electrons and shortening the on-time and off-time of the device.

Referring to fig. 1-3, the epitaxial structure optionally further includes at least one of a nucleation layer 14, a buffer layer 15, and a channel layer 16 on a side of the barrier layer 11 remote from the passivation layer 10.

The nucleation layer 14, the buffer layer 15, and the channel layer 16 are exemplarily illustrated to be sequentially included in the direction from the substrate 12 to the barrier layer 11 in this embodiment. The nucleation layer 14 and the buffer layer 15 are used to match the lattices of the substrate 12 and the channel layer 16, the channel layer 16 and the barrier layer 11 form a heterojunction structure, and a two-dimensional electron gas may be formed at the heterojunction interface of the channel layer 16 and the barrier layer 11. Specifically, the material of the nucleation layer 15 may be, for example, aluminum nitride (AlN); the material of the buffer layer 22 may be, for example, aluminum gallium nitride (AlGaN), and the content of Al in the buffer layer 22 may be 5%; the material of the channel layer 16 may be, for example, GaN or other semiconductor material.

With continued reference to fig. 1-3, optionally, the barrier layer recess 111 is filled with the same material as the passivation layer 10.

After the substrate 12, the nucleation layer 14, the buffer layer 15, the channel layer 16 and the barrier layer 11 are sequentially formed, after the barrier layer groove 111 is etched in the barrier layer 11, the passivation layer 10 can be continuously formed on the barrier layer groove 111 and the barrier layer 11 through deposition or other processes, and at this time, the barrier layer groove 111 is filled with the material of the passivation layer 10. Compared with the case that the barrier layer groove 111 is filled with other insulating materials different from the material of the passivation layer 10, the filling of the barrier layer groove 111 and the formation of the barrier layer 11 in one process in the present embodiment can simplify the preparation process of the epitaxial structure and improve the preparation efficiency.

The embodiment of the invention also provides a semiconductor device which comprises the epitaxial structure in any one of the embodiments. The semiconductor device has the same beneficial effects as the epitaxial structure, and the description of the embodiment is omitted here.

In fig. 1, a passivation layer 10 is exemplarily provided with a thickness of 200nm, a barrier layer 11 with a thickness of 15nm, a channel layer 16 with a thickness of 10nm, and a buffer layer 15 with a thickness of 2 um. The distance between the gate electrode 1311 and the source electrode 132 is 1um, the length of the gate electrode 1311 is 1.4um, the distance between the gate electrode 1311 and the drain electrode 133 is 6um, and the length of the field plate is 1.8 um. Fig. 4 is a distribution diagram of the electric field on the surface of the channel layer when the semiconductor device according to the embodiment of the present invention is turned on. Fig. 5 is a temperature distribution diagram of a channel layer when a semiconductor device according to an embodiment of the present invention is turned on, where the semiconductor device in fig. 4 and 5 includes an epitaxial structure as shown in fig. 1, and a dot position of abscissa X in fig. 4 and 5 is an edge side of the source 132 away from the drain 133, a direction along the abscissa X increases is a direction pointing to the drain 133 along the edge side of the source 132 away from the drain 133, and a unit of the abscissa X is um. In FIG. 4, the ordinate represents the Electric Field strength Electric Field in MV/cm, and in FIG. 5, the ordinate represents the channel layer Temperature Lattice Temperature in K. Referring to fig. 1, 4 and 5, each of fig. 4 and 5 includes four curves corresponding to 0

barrier layer grooves

111, 5

barrier layer grooves

111, 10

barrier layer grooves

111 and 15 barrier layer grooves 111 in the epitaxial structure, where the four curves correspond to the epitaxial structure, which can refer to fig. 1, except that the number of barrier layer grooves 111 is different.

As shown in fig. 4, the electric field distribution of the semiconductor device has a large field intensity at the edge of the gate electrode 1311 where X is 2.9um, i.e., where the gate electrode 1311 is close to the drain electrode 133, due to the electric field concentration effect at the edge of the gate electrode 1311. As can be seen from the comparison of the four curves, the greater the number of barrier layer grooves 111 in the four curves, the smoother the electric field curve. Therefore, the provision of the barrier layer recess 111 can increase the area of concentrated electric field, smoothen the originally steep electric field distribution, lower the peak value of the electric field at the edge of the gate electrode 1311, suppress the hot electron effect occurring at the edge of the gate electrode 1311, further reduce the energy obtained by the electrons at the edge of the gate electrode 1311, reduce the number of the electrons at the edge of the gate electrode 1311 becoming hot electrons, further shorten the time for the trap to trap and release the trapped hot electrons, and shorten the time for turning on and off the device.

In fig. 5, hot spots of the channel layer 16 appear at the edge side of the gate electrode 1311 close to the drain 133 of the gate electrode 1311, the greater the number of barrier layer grooves 111, the lower the temperature of the channel layer 16, and the very similar electric field distribution patterns of the epitaxial structures corresponding to 10

barrier layer grooves

111 and 15 barrier layer grooves 111, but the temperatures of the two are obviously different, which indicates that the increased contact area between the barrier layer 11 and the passivation layer 10 due to the barrier layer grooves 111 can effectively enhance the heat dissipation of the channel layer 16, reduce the temperature of the channel layer 16, and further facilitate prolonging the service life of the semiconductor device.

FIG. 6 is a diagram illustrating the distribution of the trapped hot electrons in the buffer layer of a semiconductor device with different numbers of grooves in the barrier layer when the turn-on time is 0 second according to an embodiment of the present invention; FIG. 7 is a diagram illustrating the distribution of hot electron trapped by the buffer layer of a semiconductor device with different numbers of recessed barrier layers when the turn-on time is 0.11 us/sec according to an embodiment of the present invention; fig. 8 is a diagram showing distribution of trapped hot electrons of BUFFER layers of a semiconductor device with different numbers of grooves of barrier layers when the turn-on time is 0.21 us/sec according to an embodiment of the present invention, each diagram includes a distribution of hot electrons of corresponding BUFFER layers (AlGaN BUFFER) when the number of grooves of the barrier layers is 0, 5, 10, and 15, 0, 0.1, 0.2, and 0.3 in the diagram indicate ratios of trapped different hot electrons (Trap occupancy), and the abscissa in fig. 6 to 8 has the same meaning as that in fig. 4. Referring to fig. 1, 6-8, under the action of a voltage of 50V applied to the drain electrode 133, electrons in the channel layer 16 between the gate electrode 131 and the drain electrode 133 obtain enough heat by the electric field of the drain electrode 133 to become hot electrons, so as to be trapped by traps in the buffer layer 15. As can be seen from fig. 6-8, the higher the number of barrier layer grooves 111 at the same time, the lower the hot electron concentration of the buffer layer 15 of the semiconductor device, indicating that the semiconductor device can release the trapped hot electrons more quickly when the device is turned on. With the time change, after the semiconductor device is opened, the more concentrated electric field regions are introduced by the barrier layer grooves 111, the more weakened the effect of the electric field applied to the edge of the gate close to the drain electrode by biasing the drain electrode 133, therefore, with the increase of the number of the barrier layer grooves 111, the number of the hot electrons trapped by the traps of the buffer layer 15 in the semiconductor device is reduced, and the trapped hot electrons are released earlier, that is, the drain electrode 133 can more easily acquire the hot electrons trapped by the traps, so that the time for turning on and off the device can be shortened.

FIG. 9 is a graph of the rise time and fall time of a semiconductor device with different numbers of barrier layer recesses, plotted on the abscissa for time in ns and on the ordinate for the gate voltage V, according to an embodiment of the present invention_GSAnd a drain voltage V_DSIn units of V. Fig. 9 includes two sets of curves, one set is a drain voltage curve 011, and the other set is a gate voltage curve 012, where each set includes four curves corresponding to barrier layer grooves with numbers of 0, 5, 10, and 15, respectively. Fig. 10 is a bar graph of device rise and fall times for different numbers of barrier layer recesses according to an embodiment of the present invention, and fig. 10 corresponds to fig. 9. FIG. 11 is a diagram of a semiconductor device switching characteristic measurement circuit according to an embodiment of the present inventionReferring to fig. 1 and fig. 9 to fig. 11, the circuit in fig. 11 includes a gate driver 01, a dc power supply 02, a resistor R1, a semiconductor device Q1, an inductor L1, and a diode Q2, wherein the semiconductor device Q1 is a semiconductor device prepared by using the epitaxial structure shown in fig. 1, in which the number of the barrier layer grooves is 0, 5, 10, and 15, respectively. The signal of the gate driver 01 is set to 5V and 0V, the dc power supply 02 is set to 50V, which is lower than the breakdown voltage of the semiconductor device Q1, the rise time (tr) is defined as the time between the voltage of the drain 133 falling to 90% (45V) and 10% (5V) of the voltage of the dc power supply 02, and the fall time (tf) is defined as the time between the voltage of the drain 133 rising to 10% (5V) and 90% (45V) of the voltage of the dc power supply 02.

In the prior art semiconductor device (i.e. the number of barrier layer grooves is 0), the rise time for turning on the device is 17.10ns, and the fall time for turning off the device is 13.33ns, and the rise time and the fall time of the semiconductor device provided with 15 barrier layer grooves in the embodiment are 16.16ns and 10.71 ns. Therefore, it can be proved that the barrier layer recess can shorten the turn-on and turn-off time of the semiconductor device and improve the response capability of the device.

It should be understood that various forms of the flows shown above, reordering, adding or deleting steps, may be used. For example, the steps described in the present invention may be executed in parallel, sequentially, or in different orders, and are not limited herein as long as the desired results of the technical solution of the present invention can be achieved.

The above-described embodiments should not be construed as limiting the scope of the invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An epitaxial structure, comprising:

a passivation layer;

a barrier layer on one side of the passivation layer;

2. The epitaxial structure of claim 1, wherein the barrier layer recess has a depth less than a thickness of the barrier layer.

3. Epitaxial structure according to claim 1, characterized in that the side of the passivation layer remote from the barrier layer is provided with an electrode layer comprising a gate electrode, a source electrode and a drain electrode, the texturing region being located between the gate electrode and the drain electrode.

4. The epitaxial structure of claim 3, wherein the barrier layer is located between the source and drain electrodes, the gate is embedded in the passivation layer, and a surface of the gate remote from the barrier layer is flush with a surface of the passivation layer remote from the barrier layer.

5. The epitaxial structure of claim 3, comprising at least two of said barrier layer grooves aligned in a direction from said gate to said drain.

6. The epitaxial structure of claim 5, wherein the barrier layer recess is deeper near the gate than near the drain.

7. The epitaxial structure of claim 5, wherein the density of barrier layer grooves near the gate is greater than the density of barrier layer grooves near the drain.

8. The epitaxial structure of claim 1, further comprising at least one of a nucleation layer, a buffer layer, and a channel layer on a side of the barrier layer remote from the passivation layer.

9. The epitaxial structure of claim 1 wherein the fill material of the barrier layer recess is the same as the material of the passivation layer.

10. A semiconductor device comprising an epitaxial structure according to any of claims 1 to 9.