CN114566538B

CN114566538B - Epitaxial structure and semiconductor device

Info

Publication number: CN114566538B
Application number: CN202210206690.0A
Authority: CN
Inventors: 许洁; 张�杰
Original assignee: Shanghai Luxin Electronic Technology Co ltd
Current assignee: Shanghai Luxin Electronic Technology Co ltd
Priority date: 2022-03-03
Filing date: 2022-03-03
Publication date: 2023-07-07
Anticipated expiration: 2042-03-03
Also published as: CN114566538A

Abstract

The invention provides an epitaxial structure and a semiconductor device, wherein the epitaxial structure comprises: a passivation layer; the barrier layer is positioned on one side of the passivation layer; the surface of the barrier layer comprises at least one barrier layer groove, the at least one barrier layer groove is located in the structure setting area, and an opening of the at least one barrier layer groove faces the passivation layer. The barrier layer groove on the surface of the barrier layer can introduce more electric field concentration areas, so that the intensity of a peak electric field generated at the edge of the grid electrode close to the drain electrode due to the electric field concentration effect is weakened, the number of hot electrons which are captured by a trap and become at the edge of the grid electrode due to the action of the peak electric field is reduced, the charge and discharge time of the trap when the semiconductor device is switched on and off is shortened, the time for switching on and off the semiconductor device is shortened, and the response speed of the device is improved.

Description

Epitaxial structure and semiconductor device

Technical Field

The present invention relates to the field of transistor technologies, and in particular, to an epitaxial structure and a semiconductor device.

Background

The gallium nitride semiconductor material has the remarkable advantages of large forbidden bandwidth, high electron saturation drift rate, high breakdown field strength, high temperature resistance and the like, has wide application prospect, and becomes a hot spot for research in the current semiconductor industry.

Gallium nitride High Electron Mobility Transistor (HEMT) is a semiconductor device formed using two-dimensional electron gas at AlGaN/GaN heterojunction, and can be applied to the fields of high frequency, high voltage and high power. The gallium nitride high electron mobility transistor comprises an epitaxial layer, and a passivation layer, a grid electrode, a source electrode and a drain electrode which are arranged on the epitaxial layer.

When a voltage is applied to the drain, an electric field with a larger electric field strength is formed at the edge position of the gate close to the drain, and the electric field can enable electrons in a two-dimensional electron gas channel corresponding to the edge position of the gate close to the drain to obtain more energy to be changed into hot electrons, and the hot electrons can be captured by deep trap energy levels in the semiconductor device, so that more time is required for capturing or releasing hot electrons when the transistor is turned on and off, and the time for turning on and off the transistor is prolonged.

Disclosure of Invention

The invention provides an epitaxial structure and a semiconductor device, which are used for shortening the turn-on and turn-off time of the semiconductor device and improving the response speed of the semiconductor device.

According to an aspect of the present invention, there is provided an epitaxial structure comprising:

a passivation layer;

a barrier layer located on one side of the passivation layer;

the surface of the barrier layer comprises at least one barrier layer groove, the at least one barrier layer groove is located in the structure setting area, and an opening of the at least one barrier layer groove faces the passivation layer.

Optionally, the depth of the barrier layer groove is smaller than the thickness of the barrier layer.

Optionally, an electrode layer is disposed on a side of the passivation layer away from the barrier layer, the electrode layer includes a gate electrode, a source electrode, and a drain electrode, and the structure setting region is located between the gate electrode and the drain electrode.

Optionally, the barrier layer is located between the source and the drain, the gate is embedded in the passivation layer, and a surface of the gate away from the barrier layer is flush with a surface of the passivation layer away from the barrier layer.

Optionally, the epitaxial structure includes at least two barrier layer recesses arranged along a direction from the gate electrode to the drain electrode.

Optionally, the depth of the barrier layer recess near the gate is greater than the depth of the barrier layer recess near the drain.

Optionally, the density of the barrier layer recesses near the gate is greater than the density of the barrier layer recesses near the drain.

Optionally, the epitaxial structure further includes at least one of a nucleation layer, a buffer layer, and a channel layer on a side of the barrier layer away from the passivation layer.

Optionally, the filling material of the barrier layer groove is the same as the material of the passivation layer.

According to another aspect of the present invention, there is provided a semiconductor device comprising the epitaxial structure of any one of the above.

The embodiment of the invention provides an epitaxial structure and a semiconductor device, wherein the epitaxial structure comprises: a passivation layer; a barrier layer located on one side of the passivation layer; the barrier layer comprises at least one barrier layer groove, the at least one barrier layer groove is located in the structure setting area, and an opening of the at least one barrier layer groove faces the passivation layer. The at least one barrier layer groove arranged on the barrier layer can introduce more electric field concentration areas, so that the intensity of a peak electric field generated at the edge of the grid electrode close to the drain electrode due to the electric field concentration effect is weakened, the number of hot electrons which are captured by a trap and become at the edge of the grid electrode due to the action of the peak electric field is reduced, the charge and discharge time of the trap when the semiconductor device is switched is further shortened, namely, the time for switching on and off the semiconductor device is shortened, and the response speed of the device is improved.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of an epitaxial structure according to an embodiment of the present invention;

fig. 2 is a schematic structural view of another epitaxial structure according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of another epitaxy structure according to an embodiment of the present invention;

FIG. 4 is a graph showing an electric field distribution of a channel layer surface when a semiconductor device is turned on according to an embodiment of the present invention;

fig. 5 is a diagram showing a temperature distribution of a channel layer when a semiconductor device is turned on according to an embodiment of the present invention;

FIG. 6 is a graph showing the thermal electron trapping profile of buffer layers of semiconductor devices with different numbers of barrier grooves at an on time of 0 seconds according to an embodiment of the present invention;

FIG. 7 is a graph showing the thermal electron trapping profile of buffer layers of semiconductor devices with different numbers of barrier grooves at an on time of 0.11us seconds according to an embodiment of the present invention;

FIG. 8 is a graph showing the thermal electron trapping profile of buffer layers of semiconductor devices with different numbers of barrier grooves at an on time of 0.21us seconds according to an embodiment of the present invention;

FIG. 9 is a graph showing rise time and fall time of a semiconductor device having different numbers of barrier layer recesses according to an embodiment of the present invention;

FIG. 10 is a bar graph of device rise time and fall time for different numbers of barrier layer recesses provided by an embodiment of the present invention;

fig. 11 is a schematic diagram of a structure of a double pulse circuit diagram for measuring switching characteristics of a semiconductor device according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Fig. 1 is a schematic structural diagram of an epitaxial structure according to an embodiment of the present invention, and referring to fig. 1, the epitaxial structure includes:

a passivation layer 10;

a barrier layer 11, the barrier layer 11 being located on one side of the passivation layer 10;

the surface of the barrier layer 11 includes at least one barrier layer groove 111, the at least one barrier layer groove 111 is located in the structure setting region 112, and an opening of the at least one barrier layer groove 111 faces the passivation layer 10.

Optionally, the epitaxial structure further comprises a substrate 12 and an electrode layer 13, the substrate 12 is located on a side of the barrier layer 11 remote from the passivation layer 10, and the electrode layer 13 is located on a side of the passivation layer 10 remote from the barrier layer 11. The opening of the at least one barrier layer recess 111 is disposed on the surface of the barrier layer 11 on the side close to the passivation layer 10 toward the passivation layer 10, i.e., the barrier layer recess 111.

For example, the substrate 12 may include silicon carbide (SiC), the passivation layer 10 may include silicon nitride (SiN), the material of the barrier layer 11 may be aluminum gallium nitride (AlGaN), and the higher AL component in the barrier layer 11 is beneficial to reduce on-resistance, and simultaneously, polarization may occur between Aluminum (AL) and gallium nitride (GaN) in the barrier layer 11, so that leakage of two-dimensional electron gas generated on the surface of the barrier layer 11 is prevented due to polarization, and thus the breakdown voltage of the epitaxial structure is improved.

After the barrier layer 11 is formed, at least one barrier layer groove 111 may be etched by an etching process, and in this embodiment, 15 barrier layer grooves 111 are etched, and the size of the barrier layer groove 111 and the pitch of two adjacent barrier layer grooves 111 are equal. In other embodiments, the size of the barrier layer grooves 111 and the spacing between two adjacent barrier layer grooves 111 may be set according to requirements. The barrier layer groove 111 needs to be filled with a material, and the filled material is only required to be an insulating material, and the material for filling the barrier layer groove 111 is not particularly limited in this embodiment.

The electrode layer 13 includes a gate electrode and a drain electrode, and when a voltage is applied to the drain electrode, a peak electric field (i.e., an electric field having a larger electric field strength) occurs in the channel at the edge of the gate electrode near the drain electrode due to the electric field concentration effect generated by biasing the gate electrode and the drain electrode by the edge of the gate electrode near the drain electrode, so that electrons at the edge of the gate electrode can obtain more energy due to the peak electric field to become hot electrons to be trapped by traps (the epitaxial structure further includes a buffer layer 15 including traps). When the epitaxial structure is applied to a semiconductor device, when the device is subjected to a large drain bias, hot electrons in the channel undergo transition and are trapped by deep trap energy levels, so that the device is not immediately turned on when the drain voltage gradually drops to 0V during the conduction process, and extra time is required for the traps which trap the hot electrons to release the hot electrons. Similarly, when the device is turned on, the drain voltage rises from 0V to an on voltage, an exemplary on voltage may be 50V, and the drain current will not saturate immediately, and trap trapping of hot electrons delays the time required for the drain current to saturate.

The plurality of barrier layer grooves 111 provided in this embodiment can introduce more electric field concentration regions at the lower right corner of the groove structure, and when the voltage applied by the drain electrode is constant, the intensity of the electric field excited by the drain electrode is constant, and when the concentration electric field region increases, the peak electric field intensity at the edge of the gate electrode near the drain electrode is weakened, so as to reduce the number of hot electrons, shorten the time for trapping or releasing the trapped hot electrons by the trap, and shorten the time for switching on and off the device. At least one barrier layer groove arranged on the barrier layer can introduce at least one extra electric field concentration area, so that the intensity of a peak electric field generated at the edge of the grid electrode close to the drain electrode due to the electric field concentration effect is weakened, the quantity of hot electrons which are captured by a trap and become the edge of the grid electrode due to the action of the peak electric field is further reduced, the charge and discharge time of the trap when the semiconductor device is switched on and off is further shortened, namely the time for switching on and off the semiconductor device is shortened, and the response speed of the device is improved.

With continued reference to fig. 1, the depth of the barrier layer recess 111 is optionally less than the thickness of the barrier layer 11.

The greater the depth of the barrier layer groove 111, the thinner the thickness of the structure setting region 112 of the barrier layer 11 will be, resulting in an increase in on-resistance of the barrier layer 11, which is detrimental to the turning on and off of the device, and therefore the depth of the barrier layer groove 111 cannot be excessively large.

With continued reference to fig. 1, optionally, an electrode layer 13 is disposed on a side of the passivation layer 10 remote from the barrier layer 11, the electrode layer 13 including a gate electrode 131, a source electrode 132, and a drain electrode 133, and the structure setting region 112 is located between the gate electrode 132 and the drain electrode 133.

An alternative structure of the electrode layer 13 is exemplarily shown in this embodiment, the barrier layer 11 is located between the source 132 and the drain 133, the gate 131 is embedded in the passivation layer 10, and the surface of the gate 131 remote from the barrier layer 11 is flush with the surface of the passivation layer 10 remote from the barrier layer 11. The gate electrode 131 includes a gate electrode 1311, a P-type channel 1312, and a field plate 1313, and the portion of the gate electrode 131 embedded in the passivation layer 10 that actually means the gate electrode 131 is embedded in the passivation layer 10, i.e., the gate electrode 1311 and the P-type channel 1312 are embedded in the passivation layer 10. The gate 131 uses Mg doped GaN as the P-type channel 1312 to deplete the channel at a gate voltage V, thereby achieving enhanced operation.

With continued reference to fig. 1, the epitaxial structure optionally includes at least two barrier layer recesses 111, the barrier layer recesses 111 being aligned in a direction from the gate 131 toward the drain 133. When a voltage is applied to the drain electrode 133, the electric field intensity at the edge of the gate electrode 1311 on the side of the gate electrode 1311 near the drain electrode 133 is large, and therefore, in order to weaken the electric field at the edge of the gate electrode 1311, a structure setting region is provided between the gate electrode 131 and the drain electrode 133, and the barrier layer grooves 111 are arranged in the direction from the gate electrode 131 toward the drain electrode 133, the peak of the electric field at the edge of the gate electrode 1311 can be weakened better.

Fig. 2 is a schematic structural diagram of another epitaxial structure according to an embodiment of the present invention, and referring to fig. 2, alternatively, the depth of the barrier layer recess 111 near the gate 131 is greater than the depth of the barrier layer recess 111 near the drain 133.

The depth of the barrier layer groove 111 near the gate 131 is greater than the depth of the barrier layer groove 111 near the drain 133, so that the weakening effect on the electric field intensity at the edge of the gate electrode 1311 can be enhanced, the number of hot electrons can be further reduced, and the time for turning on and off the device can be shortened.

Fig. 3 is a schematic structural diagram of another epitaxial structure according to an embodiment of the present invention, and referring to fig. 3, optionally, the density of the barrier layer grooves 111 near the gate 131 is greater than the density of the barrier layer grooves 111 near the drain 133. The barrier layer grooves 111 are arranged in such a way that the weakening effect on the electric field intensity at the edge of the gate electrode 1311 can be enhanced, and the effects of reducing the number of hot electrons and shortening the device on time and the device off time can be achieved.

Referring to fig. 1-3, optionally, the epitaxial structure further comprises at least one of a nucleation layer 14, a buffer layer 15 and a channel layer 16 on a side of the barrier layer 11 remote from the passivation layer 10.

The present embodiment exemplarily shows that the nucleation layer 14, the buffer layer 15, and the channel layer 16 are sequentially included in the direction from the substrate 12 to the barrier layer 11. The nucleation layer 14 and the buffer layer 15 are used to lattice match the substrate 12 and the channel layer 16, the channel layer 16 and the barrier layer 11 form a heterojunction structure, and the heterojunction interface of the channel layer 16 and the barrier layer 11 can form a two-dimensional electron gas. Specifically, the material of the nucleation layer 15 may be, for example, aluminum nitride (AlN); the material of the buffer layer 22 may be, for example, aluminum gallium nitride (AlGaN), and the content of Al in the buffer layer 22 may be 5%; the material of the channel layer 16 may be GaN or other semiconductor material, for example.

With continued reference to fig. 1-3, the barrier layer recess 111 may optionally be filled with the same material as the passivation layer 10.

After the substrate 12, the nucleation layer 14, the buffer layer 15, the channel layer 16, and the barrier layer 11 are sequentially formed, after the barrier layer 11 is etched with the barrier layer groove 111, the passivation layer 10 may be continuously formed on the barrier layer groove 111 and the barrier layer 11 through deposition or other processes, and at this time, the material of the passivation layer 10 is filled in the barrier layer groove 111. Compared with the filling of other insulating materials different from the passivation layer 10 material in the barrier layer groove 111, the filling of the barrier layer groove 111 and the formation of the barrier layer 11 in one process in this embodiment can simplify the preparation process of the epitaxial structure and improve the preparation efficiency.

The embodiment of the invention also provides a semiconductor device, which comprises the epitaxial structure in any embodiment. The semiconductor device has the same beneficial effects as the epitaxial structure, and the embodiment is not described here again.

In fig. 1, the passivation layer 10 is exemplarily provided to have a thickness of 200nm, the barrier layer 11 to have a thickness of 15nm, the channel layer 16 to have a thickness of 10nm, and the buffer layer 15 to have a thickness of 2um. The spacing between the gate electrode 1311 and the source 132 is 1um, the length of the gate electrode 1311 is 1.4um, the spacing between the gate electrode 1311 and the drain 133 is 6um, and the length of the field plate is 1.8um. Fig. 4 is a diagram showing an electric field distribution of a channel layer surface when a semiconductor device according to an embodiment of the present invention is turned on. Fig. 5 is a temperature distribution diagram of a channel layer when the semiconductor device is turned on, where the epitaxial structures included in the semiconductor device in fig. 4 and fig. 5 are shown in fig. 1, and the dot positions of the abscissa X in fig. 4 and fig. 5 are the edge sides of the source 132 away from the drain 133, the increasing direction along the abscissa X is the direction along the edge sides of the source 132 away from the drain 133 toward the drain 133, and the unit of the abscissa X is um. The ordinate in FIG. 4 represents the Electric Field strength, MV/cm, and the ordinate in FIG. 5 represents the channel layer temperature Lattice Temperature, K. Referring to fig. 1, 4 and 5, four curves are included in fig. 4 and 5, and are curves corresponding to 0 number of

barrier layer grooves

111, 5 number of

barrier layer grooves

111, 10 number of

barrier layer grooves

111 and 15 number of barrier layer grooves 111 in the epitaxial structure, respectively, wherein the epitaxial structure corresponding to the four curves may refer to fig. 1, and the difference is only that the number of barrier layer grooves 111 is different.

As shown in fig. 4, the electric field intensity of x=2.9 um, i.e., the side of the gate electrode 1311 near the edge of the gate electrode 1311 of the drain 133 in the electric field profile of the semiconductor device is large due to the electric field concentration effect on the side of the gate electrode 1311 edge. As can be seen from comparison of the four curves, the greater the number of barrier layer grooves 111 in the four curves, the smoother the curve of the electric field. Therefore, the provision of the barrier layer recess 111 can increase the region where the electric field is concentrated, smooth the originally steep electric field distribution, lower the peak value of the electric field at the edge side of the gate electrode 1311, suppress the hot electron effect occurring at the edge side of the gate electrode 1311, further reduce the energy obtained by electrons at the edge side of the gate electrode 1311, reduce the number of electrons at the edge side of the gate electrode 1311 to become hot electrons, further shorten the time for trapping and releasing the trapped hot electrons, and shorten the time for turning on and off the device.

In fig. 5, the hot spot of the channel layer 16 appears on the edge side of the gate electrode 1311, which is close to the drain electrode 133, of the gate electrode 1311, the more the number of the barrier layer grooves 111, the lower the temperature of the channel layer 16, and the electric field distribution diagram of the epitaxial structure corresponding to the 10 barrier layer grooves 111 and the 15 barrier layer grooves 111 are very similar, but the temperatures of the two are obviously different, which means that the increased contact area between the barrier layer 11 and the passivation layer 10 can effectively enhance the heat dissipation of the channel layer 16, reduce the temperature of the channel layer 16, and further be beneficial to prolonging the service life of the semiconductor device.

FIG. 6 is a graph showing the thermal electron trapping profile of buffer layers of semiconductor devices with different numbers of barrier grooves at an on time of 0 seconds according to an embodiment of the present invention; FIG. 7 is a graph showing the thermal electron trapping profile of buffer layers of semiconductor devices with different numbers of barrier grooves at an on time of 0.11us seconds according to an embodiment of the present invention; fig. 8 is a graph of thermal electron trapping profiles of BUFFER layers (AlGaN BUFFER) of semiconductor devices having different numbers of barrier grooves at an on time of 0.21us seconds, each of which includes thermal electron trapping profiles of corresponding BUFFER layers (AlGaN BUFFER) having numbers of barrier grooves of 0, 5, 10, and 15, wherein 0, 0.1, 0.2, and 0.3 represent the ratio (Trap occupancy) of the trapped different thermal electrons, and the meanings of the abscissa in fig. 6 to 8 are the same as those in fig. 4. Referring to fig. 1 and 6 to 8, electrons in the channel layer 16 between the gate electrode 131 and the drain electrode 133 are sufficiently heated by the electric field of the drain electrode 133 to become hot electrons by the application of a voltage of 50V to the drain electrode 133, and thus are trapped by traps in the buffer layer 15. As can be seen from fig. 6-8, at the same time, the lower the hot electron concentration of the semiconductor device buffer layer 15, the greater the number of barrier layer recesses 111, indicating that the semiconductor device can release the trapped hot electrons faster when the device is turned on. After the semiconductor device is turned on, the more the concentrated electric field region is introduced by the barrier layer grooves 111, the more the effect of the electric field applied to the gate electrode near the drain edge by the bias of the drain electrode 133 can be weakened, so as the number of the barrier layer grooves 111 increases, the hot electrons trapped by the traps of the buffer layer 15 in the semiconductor device are reduced, and the trapped hot electrons are released earlier, i.e., the drain electrode 133 is easier to acquire the hot electrons trapped by the traps, so that the time for turning on and off the device can be shortened.

FIG. 9 is a graph showing rise time and fall time of semiconductor devices with different numbers of barrier grooves, wherein the abscissa represents time, the unit ns, and the ordinate represents gate voltage V _GS And drain voltage V _DS The unit is V. Fig. 9 includes two sets of curves, one set is a drain voltage curve 011 and the other set is a gate voltage curve 012, each set of curves including four curves corresponding to the number of barrier layer grooves being 0, 5, 10, and 15, respectively. Fig. 10 is a bar chart of rise time and fall time of devices with different numbers of grooves of barrier layers according to an embodiment of the present invention, and fig. 10 corresponds to fig. 9. Fig. 11 is a schematic structural diagram of a double pulse circuit diagram for measuring switching characteristics of a semiconductor device according to an embodiment of the present invention, and referring to fig. 1, 9-11, the circuit in fig. 11 includes a gate driver 01, a dc power supply 02, a resistor R1, a semiconductor device Q1, an inductor L1, and a diode Q2, where the semiconductor device Q1 is a semiconductor device fabricated using the epitaxial structure shown in fig. 1 with the number of barrier grooves being 0, 5, 10, and 15, respectively. The signal of the gate driver 01 is set to 5V and 0V, the dc power supply 02 is set to 50V, and is lower than the breakdown voltage of the semiconductor device Q1, the rise time (tr) is defined as the time when the voltage of the drain 133 falls between 90% (45V) and 10% (5V) of the voltage of the dc power supply 02, and the fall time (tf) is defined as the time when the voltage of the drain 133 rises between 10% (5V) and 90% (45V) of the voltage of the dc power supply 02.

In the prior art, the rise time of the semiconductor device (i.e. the number of the barrier layer grooves is 0) is 17.10ns, the fall time of the semiconductor device is 13.33ns, and the rise time of the semiconductor device with 15 barrier layer grooves provided in the embodiment is 16.16ns, and the fall time is 10.71ns. Therefore, the barrier layer groove can be proved to shorten the opening and closing time of the semiconductor device and improve the response capability of the device.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.

The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims

1. An epitaxial structure, comprising:

a passivation layer;

a barrier layer located on one side of the passivation layer;

the surface of the barrier layer comprises at least one barrier layer groove, the at least one barrier layer groove is positioned in the structure setting area, and an opening of the at least one barrier layer groove faces the passivation layer;

the density of the barrier layer grooves near the gate is greater than the density of the barrier layer grooves near the drain;

an electrode layer is arranged on one side, far away from the barrier layer, of the passivation layer, the electrode layer comprises a grid electrode, a source electrode and a drain electrode, and the structure setting area is located between the grid electrode and the drain electrode.

2. The epitaxial structure of claim 1, wherein the barrier layer recess has a depth less than a thickness of the barrier layer.

3. The epitaxial structure of claim 1, wherein the barrier layer is located between the source and the drain, the gate is embedded in the passivation layer, and a surface of the gate remote from the barrier layer is flush with a surface of the passivation layer remote from the barrier layer.

4. The epitaxial structure of claim 1, wherein the barrier layer recesses are aligned in a direction from the gate electrode toward the drain electrode.

5. The epitaxial structure of claim 4, wherein a depth of the barrier layer recess proximate the gate is greater than a depth of the barrier layer recess proximate the drain.

6. The epitaxial structure of claim 1, further comprising at least one of a nucleation layer, a buffer layer, and a channel layer on a side of the barrier layer remote from the passivation layer.

7. The epitaxial structure of claim 1, wherein a filling material of the barrier layer recess is the same as a material of the passivation layer.

8. A semiconductor device comprising the epitaxial structure of any one of claims 1-7.