CN109103104A - Semiconductor devices and preparation method thereof - Google Patents
Semiconductor devices and preparation method thereof Download PDFInfo
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- CN109103104A CN109103104A CN201810803338.9A CN201810803338A CN109103104A CN 109103104 A CN109103104 A CN 109103104A CN 201810803338 A CN201810803338 A CN 201810803338A CN 109103104 A CN109103104 A CN 109103104A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 114
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 86
- 239000002184 metal Substances 0.000 claims abstract description 86
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 229910002601 GaN Inorganic materials 0.000 claims description 26
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims description 23
- 239000010936 titanium Substances 0.000 claims description 20
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 18
- 229910052719 titanium Inorganic materials 0.000 claims description 18
- 239000011248 coating agent Substances 0.000 claims description 15
- 238000000576 coating method Methods 0.000 claims description 15
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 11
- 150000004767 nitrides Chemical class 0.000 claims description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 10
- 230000005533 two-dimensional electron gas Effects 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 description 11
- 238000000151 deposition Methods 0.000 description 8
- 239000004615 ingredient Substances 0.000 description 6
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 238000009616 inductively coupled plasma Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229960000909 sulfur hexafluoride Drugs 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention relates to technical field of semiconductors, a kind of semiconductor devices and preparation method thereof is provided.The semiconductor devices includes: semiconductor substrate；First medium layer and the second dielectric layer being set on the semiconductor substrate；The gate metal layer being set in the second dielectric layer；And it is set to source electrode, drain and gate in the gate metal layer；Wherein, the source electrode and the drain electrode with the semiconductor substrate through the gate metal layer and the dielectric layer to connect respectively；The grid protrudes into the semiconductor substrate and including first grid portion interconnected and second gate portion, the bottom in the first grid portion is connect by the gate metal layer with the semiconductor substrate, and the bottom in the second gate portion is connect by the grid category layer and the second dielectric layer with the semiconductor substrate.Semiconductor devices of the invention can obtain better device property.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of semiconductor devices and a kind of systems of semiconductor devices
Make method.
Background technique
AlGaN (aluminum gallium nitride)/GaN (gallium nitride) HEMT (High Electron Mobility Transistor,
High electron mobility transistor) in the semiconductor devices such as device, it can generally use MIS (Metal-Insulator-
Semiconductor, metal-insulator semiconductor) structure reduces gate leakage currents, but the introducing of insulating layer can be led
Cause the decline of grid-control ability；And conductivity gate structure is used, although output electric current will increase, gate edge can have peak value
Electric field causes leakage current to rise.It is, therefore, desirable to provide a kind of semiconductor devices for being able to solve problem above and its production side
Method.
Summary of the invention
To solve the above problems, the present invention provides the half of a kind of double-gate structure that MIS structure is combined with Schottky junction structure
Conductor device and preparation method thereof can obtain better device property.
A kind of semiconductor devices provided in an embodiment of the present invention, comprising: semiconductor substrate；It is set to the semiconductor substrate
On dielectric layer, the dielectric layer includes the first medium layer set gradually from bottom to up and second dielectric layer；It is set to described
Gate metal layer in second dielectric layer；And it is set to source electrode, drain and gate in the gate metal layer；Wherein, institute
Source electrode and the drain electrode are stated through the gate metal layer and the dielectric layer, so that the bottom of the source electrode and the drain electrode
Bottom connect respectively with the semiconductor substrate；The grid protrudes into the semiconductor substrate and including interconnected
One grid portion and second gate portion, the bottom in the first grid portion connect by the gate metal layer with the semiconductor substrate (with
Form Schottky junction structure), the bottom in the second gate portion is partly led by the grid category layer and the second dielectric layer with described
Structure base board connects (form MIS structure).
The present invention in one embodiment, the semiconductor substrate includes: silicon substrate, and is set to silicon lining
The nitride buffer layer of bottom surface and the aluminum gallium nitride layer for being set to the nitride buffer layer surface.
The present invention in one embodiment, the grid protrudes into the aluminum gallium nitride layer, the bottom in the first grid portion
Portion is connect to form Schottky junction structure with the aluminum gallium nitride layer by the gate metal layer, and the bottom in the second gate portion is logical
It crosses the gate metal layer and the second dielectric layer is connect with the aluminum gallium nitride layer to form MIS structure.
The present invention in one embodiment, the silicon substrate be P (111) type silicon substrate.
The present invention in one embodiment, be formed with two between the nitride buffer layer and the aluminum gallium nitride layer
Dimensional electron gas channel.
The present invention in one embodiment, the source electrode and/or it is described drain electrode be made of metal ohmic contact, it is described
Metal ohmic contact successively includes: the first titanium coating, aluminum metal layer, the second titanium coating and titanium nitride layer from bottom to up.
The present invention in one embodiment, the grid is made of the metal ohmic contact, the gate metal
The material of layer is titanium nitride, and the material of the dielectric layer is silicon nitride, silica or hafnium oxide.
On the other hand, a kind of semiconductor devices provided in an embodiment of the present invention, comprising: semiconductor substrate, the semiconductor
Two-dimensional electron gas channel is formed in substrate；First medium layer is arranged on the semiconductor substrate, and first grid contact hole
Through the first medium layer and extend into the semiconductor-based intralamellar part；Second dielectric layer is arranged in the first medium layer
Go up and extend in the first grid contact hole bottom for covering the first grid contact hole, and second grid contact hole
Through the second dielectric layer and the first medium layer and extend into the semiconductor-based intralamellar part and the second medium
Layer does not cover the bottom of the second grid contact hole, and the second grid contact hole is connected with the first grid contact hole
It is logical；Gate metal layer is arranged in the second dielectric layer and extends in the first grid contact hole with covering positioned at institute
It states the second dielectric layer of the bottom of first grid contact hole and extends into the second grid contact hole to cover
The bottom of second grid contact hole is stated, source contact openings and drain contact hole run through the gate metal layer, the second medium
Layer and the first medium layer；Grid, is arranged in the gate metal layer and the filling first grid contact hole and described
Second grid contact hole；Source electrode and drain electrode is arranged in the gate metal layer and fills the source contact openings and institute respectively
State drain contact hole.
The present invention in one embodiment, the width of the first grid contact hole and the second grid contact hole
Width ratio be 1:1.
Another aspect, a kind of production method of semiconductor devices provided in an embodiment of the present invention, comprising steps of in semiconductor
First medium layer is formed on substrate, wherein having Two-dimensional electron gas channel in the semiconductor substrate；Etch the first medium
Layer and the semiconductor substrate are to form first grid contact hole, wherein the first grid contact hole runs through the first medium
Layer simultaneously extends into the semiconductor-based intralamellar part；Second dielectric layer is formed on the first medium layer and makes described second to be situated between
Matter layer extends in the first grid contact hole bottom for covering the first grid contact hole；Etch the second medium
Layer, the first medium layer and the semiconductor substrate are to form second grid contact hole, wherein the second grid contact hole
Through the second dielectric layer and the first medium layer and the inside for extending into the semiconductor substrate；In the second medium
Gate metal layer is formed on layer and extends to the gate metal layer in the first grid contact hole with covering positioned at described
It the second dielectric layer of the bottom of first grid contact hole and extends in the second grid contact hole described in covering
The bottom of second grid contact hole；The gate metal layer, the second dielectric layer and the first medium layer are etched to be formed
Source contact openings and drain contact hole；Ohmic contact metal layer is formed in the gate metal layer and makes the Ohmic contact
Metal layer is filled to the first grid contact hole, the second grid contact hole, the source contact openings and the drain electrode and is connect
Contact hole；The ohmic contact metal layer and the gate metal layer are etched to form the corresponding first grid contact hole and described
The drain electrode of the grid of second grid contact hole, the source electrode of the corresponding source contact openings and the corresponding drain contact hole, thus
The semiconductor devices is made.
In embodiments of the present invention, it is redesigned by structure to semiconductor devices, obtains a kind of MIS structure and Xiao Te
The semiconductor devices for the double-gate structure that based structures combine can obtain better device property.
Detailed description of the invention
Figure 1A is the partial profile structure of the active region of semiconductor devices in one embodiment of the invention.
Figure 1B is the schematic diagram of the section structure of grid in one embodiment of the invention.
Fig. 2A is the obtained device active region of step 1 of the production method of semiconductor devices in one embodiment of the invention
The partial profile structure in domain.
Fig. 2 B is the obtained device active region of step 2 of the production method of semiconductor devices in one embodiment of the invention
The partial profile structure in domain.
Fig. 2 C is the obtained device active region of step 3 of the production method of semiconductor devices in one embodiment of the invention
The partial profile structure in domain.
Fig. 2 D is the obtained device active region of step 4 of the production method of semiconductor devices in one embodiment of the invention
The partial profile structure in domain.
Fig. 2 E is the obtained device active region of step 5 of the production method of semiconductor devices in one embodiment of the invention
The partial profile structure in domain.
Fig. 2 F is the obtained device active region of step 6 of the production method of semiconductor devices in one embodiment of the invention
The partial profile structure in domain.
Fig. 2 G is the obtained device active region of step 7 of the production method of semiconductor devices in one embodiment of the invention
The partial profile structure in domain.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
As shown in Figure 1A, a kind of semiconductor devices 100 that one embodiment of the present of invention provides, comprising: semiconductor substrate
110；Dielectric layer 120a, the 120b being set on semiconductor substrate 110；The gate metal layer 130 being set on dielectric layer 120b；
And it is set to source electrode 140, drain electrode 150 and grid 160 in gate metal layer 130.
Wherein, source electrode 140 and drain electrode 150 for example run through gate metal layer 130 and dielectric layer 120a, 120b, so that source
The bottom of pole 140 and the bottom of drain electrode 150 are connect with semiconductor substrate 110 respectively.
As shown in Figure 1B, grid 160 for example protrudes into semiconductor substrate 110 and including grid portion 161 interconnected and grid portion
163.The bottom 1611 in grid portion 161 is for example connect only by gate metal layer 130 with semiconductor substrate 110, to constitute Xiao Te
In other words based structures are provided only with gate metal layer 130 between the bottom 1611 and semiconductor substrate 110 in grid portion 161.Grid
The bottom 1631 in portion 163 is for example connect only by gate metal layer 130 and dielectric layer 120b with semiconductor substrate 110, with structure
At MIS structure, in other words, gate metal layer 130 is provided only between the bottom 1631 and semiconductor substrate 110 in grid portion 163
With dielectric layer 120b.Grid portion 161 and grid portion 163 are for example an integral molding structure.
The bottom 1611 in grid portion 161 protrudes into bottom 1631 of the depth of semiconductor substrate 110 for example than grid portion 163 and protrudes into half
The depth of conductor substrate 110 is big, and the bottom 1611 in grid portion 161 and the bottom 1631 in grid portion 163 are for example collectively formed such as figure as a result,
The ladder-like shape of left low and right high shown in 1.Certainly, in some other embodiment, it is also possible to the bottom 1611 in grid portion 161
The depth for protruding into semiconductor substrate 110 is smaller than the depth that semiconductor substrate 110 is protruded into the bottom 1631 in grid portion 163, as a result, Fig. 1
In the shape that is collectively formed of the bottom 1611 in grid portion 161 and the bottom 1631 in grid portion 163 will become the ladder-like of right low left high
Shape.
Further, in some other embodiment, it can also be that the bottom 1611 in grid portion 161 only passes through gate metal layer
130 and dielectric layer 120b is connect with semiconductor substrate 110, to form MIS structure.The bottom 1631 in grid portion 163 only passes through grid
Metal layer 130 is connect with semiconductor substrate 110, to form Schottky junction structure.
Specifically, semiconductor substrate 110 for example, silicon substrate 111, and it is set to the nitridation on 111 surface of silicon substrate
Gallium buffer layer 113 and the aluminum gallium nitride layer 115 for being set to 113 surface of nitride buffer layer.
Grid 160 for example protrudes into aluminum gallium nitride layer 115 as a result, but grid 160 does not run through aluminum gallium nitride layer 115, grid portion
161 bottom 1611 is for example only connect with aluminum gallium nitride layer 115 by gate metal layer 130 to form Schottky junction structure, grid portion
163 bottom 1631 is for example only connect by gate metal layer 130 and dielectric layer 120b with aluminum gallium nitride layer 115 to form MIS
Structure.
Silicon substrate 111 is, for example, P (111) type silicon substrate.
The thickness of nitride buffer layer 113 is greater than 3 microns.
Two-dimensional electron gas channel (2DEG) 117 is for example formed between nitride buffer layer 113 and aluminum gallium nitride layer 115.
Specifically, source electrode 140, drain electrode 150 and/or grid 160 are for example made of metal ohmic contact, the Ohmic contact
Metal for example successively includes: the first titanium coating, aluminum metal layer, the second titanium coating and titanium nitride layer from bottom to up.Wherein, institute
The ingredient for stating the first titanium coating and second titanium coating is titanium (Ti), and the ingredient of the aluminum metal layer is aluminium (Al), institute
The ingredient for stating titanium nitride layer is titanium nitride (TiN).
The material of gate metal layer 130 is, for example, titanium nitride (TiN), and the thickness of gate metal layer 130 is, for example, 200 to receive
Rice.The material of dielectric layer 120a, 120b are, for example, silicon nitride.Herein it is noted that the material example of dielectric layer 120a, 120b
Material of the dielectric layer of semiconductor devices 100, such as silica, hafnium oxide etc. are suitable as known to can also be other
High-k (high dielectric) material.
In addition, the embodiment of the present invention also provides the production method of above-mentioned semiconductor device 100.As shown in Fig. 2A to 2G, it is
The partial structurtes diagrammatic cross-section in obtained device active region domain in each step of the production method of semiconductor devices 100.
Specifically, the production method of the semiconductor devices 100 specifically includes that
Step 1: as shown in Figure 2 A, can be for example using LPCVD (Low after being cleaned to semiconductor substrate 110
Pressure Chemical Vapor Deposition, low-pressure chemical vapor deposition) one layer of dielectric layer 120a of deposition is (for example,
Si3N4, silicon nitride medium layer), for being passivated 110 surface of semiconductor substrate, its surface state is eliminated, to improve finally formed half
The reliability of conductor device 100.
Step 2: as shown in Figure 2 B, preparing gate contact hole GH1.The corresponding grid of lithographic definition gate contact hole GH1 connects
Contact hole region GHZ1, then for example, by using sulfur fluoride (SF6) and chlorine (Cl2) be gas source ICP (Inductively
Coupled Plasma, plasma inductive coupling) lithographic method etching grid contact hole GH1, it etches away and is formed in step 1
Whole dielectric layer 120a and segment thickness positioned at gate contact bore region GHZ1 aluminum gallium nitride layer 115.Wherein, photoetching
Program include gluing, exposure and imaging.Gate contact hole GH1 is through dielectric layer 120a and extends into semiconductor substrate 110
It is internal.
Step 3: as shown in Figure 2 C, one layer of dielectric layer 120b (for example, Si of redeposition3N4, silicon nitride medium layer).Specifically
Ground, dielectric layer 120b are formed on dielectric layer 120a, and dielectric layer 120b is extended in the GH1 of gate contact hole and connect with covering grid
The bottom of contact hole GH1.
Step 4: as shown in Figure 2 D, preparing gate contact hole GH2.The corresponding grid of lithographic definition gate contact hole GH2 connects
Then contact hole region GHZ2 uses sulfur fluoride and chlorine for the ICP lithographic method etching grid contact hole GH2 of gas source, etching
Fall the aluminum gallium nitride layer 115 of whole dielectric layer 120a, 120b and segment thickness positioned at gate contact bore region GHZ2.Its
In, gate contact hole GH2 runs through dielectric layer 120a and dielectric layer 120b and the inside for extending into semiconductor substrate 110.Grid connects
Contact hole GH2 is connected with gate contact hole GH1.Preferably, the width of the width of gate contact hole GH1 and gate contact hole GH2
Ratio be 1:1, it is, of course, also possible to be other suitable ratio values, such as 1:2,1:3,2:1 etc..
Step 5: as shown in Figure 2 E, one layer of gate metal, such as titanium nitride (TiN) are deposited, to form semiconductor devices 100
Gate metal layer 130.Specifically, gate metal layer 130 is formed on dielectric layer 120b and extends gate metal layer 130
To cover the dielectric layer 120b for the bottom for being located at gate contact hole GH1 and extend to gate contact in gate contact hole GH1
The bottom of the second grid contact hole is covered in the GH2 of hole.
Step 6: as shown in Figure 2 F, source contact openings SH and drain contact hole DH preparation.Lithographic definition source contact porose area
After domain SHZ and drain contact bore region DHZ, sulfur fluoride is used to etch away for the ICP lithographic method of gas source positioned at source contact
Bore region SHZ and gate metal layer 130, dielectric layer 120b and dielectric layer 120a under drain contact bore region DHZ are with shape
At source contact openings SH and drain contact hole DH, guarantee that etching stopping in aluminum gallium nitride layer 115, is avoided to aluminum gallium nitride layer 115
It causes compared with macrolesion, so that there are sufficient concentrations of electronics in 117 channel of Two-dimensional electron gas channel, maintains the high current of device special
Property.
Step 7: as shown in Figure 2 G, PVD (Physical Vapor Deposition, physical vapour deposition (PVD)) deposit ohmic
Metal is contacted, specifically, deposit ohmic contact metal forms ohmic contact metal layer and makes described in gate metal layer 130
Ohmic contact metal layer is filled to gate contact hole GH1, gate contact hole GH2, source contact openings SH and drain contact hole DH；So
Pass through lithographic definition source metal electrode region SZ, drain metal electrode region DZ and gate metal electrode region GZ afterwards；Later
Etch away deposited respectively in step 7 and step 5 be located at source metal electrode region SZ, drain metal electrode region DZ and grid
Pole metal electrode region GZ whole metal ohmic contacts and gate metal between region two-by-two, finally obtain as shown in Figure 2 G
Source electrode 140, drain electrode 150 and grid 160.Wherein, the metal ohmic contact for example successively includes: the first titanium from bottom to up
Belong to layer, aluminum metal layer, the second titanium coating and titanium nitride layer.Wherein, first titanium coating and second titanium coating
Ingredient be titanium (Ti), the ingredient of the aluminum metal layer is aluminium (Al), and the ingredient of the titanium nitride layer is titanium nitride (TiN),
When depositing the metal ohmic contact, it is sequentially depositing the first titanium coating, aluminum metal layer, the second titanium coating and titanium nitride layer,
And first titanium coating, the aluminum metal layer, second titanium coating and the titanium nitride layer deposition thickness for example
Respectively 200 angstroms, 1200 angstroms, 200 angstroms and 200 angstroms.
The deposition of metal ohmic contact can need to make each for example, by using the mode of magnetron sputtering, to keep Ohmic contact good
A contact hole namely gate contact hole GH1, gate contact hole GH2, source contact openings SH and drain contact hole DH clean few impurity,
Therefore, step 7 for example can also include removal step, specifically, such as in the preceding hydrofluoric acid (HF) of metal ohmic contact deposition
Each contact hole is cleaned, it will be in nitrogen (N after metal ohmic contact deposition2) short annealings of 850 DEG C, 45s is carried out under environment
(RTS)。
Further, before step 1, it such as further comprises the steps of: and to form semiconductor substrate 110.Specifically, in silicon substrate
Be sequentially depositing nitride buffer layer 113 and aluminum gallium nitride layer 115 on 111, nitride buffer layer 113 and aluminum gallium nitride layer 115 it
Between formed Two-dimensional electron gas channel 117, ultimately form semiconductor substrate 110.Gallium nitride is third generation semiconductor material with wide forbidden band,
With the characteristics such as big forbidden bandwidth, high electron saturation velocities, high breakdown electric field, higher heat-conductivity, corrosion-resistant and radiation resistance,
And there is stronger advantage under high pressure, high frequency, high temperature, high-power and Flouride-resistani acid phesphatase environmental condition, to be research short wavelength light
The optimal material of electronic device and high voltagehigh frequency rate high power device；Wherein, big forbidden bandwidth is 3.4 electron-volts, high electronics
Saturation rate is 2e7 centimeters per second, and high breakdown electric field is 1e10~-3e10 volts per cm.
By the above process, the semiconductor devices 100 of a complete double-gate structure completes.It is so without being limited thereto, at it
In his embodiment, also changes or increase other steps, to complete semiconductor devices 100.
In conclusion the embodiment of the present invention is redesigned by structure to semiconductor devices, obtain a kind of MIS structure with
The semiconductor devices 100 for the double-gate structure that Schottky junction structure combines, can obtain better device property；In addition, of the invention
Technique and condition used in embodiment be it is compatible with CMOS technology, strong operability has coordinated device performance well
Contradiction between process complexity.Therefore, the semiconductor devices 100 and its system for the double-gate structure that the embodiment of the present invention is proposed
Make method and provides reference well and reference, semiconductor for the design of enhanced semiconductor device high reliability, volume production scheme
Device 100 can be applied in the technical fields such as power electronic element, filter, radio communication element, have good application
Prospect.
In several embodiments provided herein, it should be understood that disclosed system, device and/or method, it can
To realize by another way.For example, the apparatus embodiments described above are merely exemplary, for example, the unit/
The division of module, only a kind of logical function partition, there may be another division manner in actual implementation, such as multichannel unit
Or module can be combined or can be integrated into another system, or some features can be ignored or not executed.Another point, institute
Display or the mutual coupling, direct-coupling or communication connection discussed can be through some interfaces, device or unit
Indirect coupling or communication connection can be electrical property, mechanical or other forms.
The units/modules as illustrated by the separation member may or may not be physically separated, as
The component that units/modules are shown may or may not be physical unit, it can and it is in one place, or can also be with
It is distributed on multi-channel network unit.Some or all of units/modules therein can be selected to realize according to the actual needs
The purpose of this embodiment scheme.
Finally, it should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
Present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: it still may be used
To modify the technical solutions described in the foregoing embodiments or equivalent replacement of some of the technical features；
And these are modified or replaceed, technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution spirit and
Range.
Claims (10)
1. a kind of semiconductor devices characterized by comprising
Semiconductor substrate；
The dielectric layer being set on the semiconductor substrate, the dielectric layer include that the first medium layer set gradually and second are situated between
Matter layer；
The gate metal layer being set in the second dielectric layer；And
Source electrode, the drain and gate being set in the gate metal layer；
Wherein, the source electrode and the drain electrode run through the gate metal layer and the dielectric layer, so that the bottom of the source electrode
Portion and the bottom of the drain electrode are connect with the semiconductor substrate respectively；
The grid protrudes into the semiconductor substrate and including first grid portion interconnected and second gate portion, the first grid
The bottom in portion is connect by the gate metal layer with the semiconductor substrate, and the bottom in the second gate portion passes through the grid
Belong to layer and the second dielectric layer is connect with the semiconductor substrate.
2. semiconductor devices as described in claim 1, which is characterized in that the semiconductor substrate includes: silicon substrate, Yi Jishe
It is placed in the nitride buffer layer of the surface of silicon and is set to the aluminum gallium nitride layer on the nitride buffer layer surface.
3. semiconductor devices as claimed in claim 2, which is characterized in that the grid protrudes into the aluminum gallium nitride layer, described
The bottom in first grid portion is connect to form Schottky junction structure with the aluminum gallium nitride layer by the gate metal layer, and described second
The bottom in grid portion is connect by the gate metal layer and the second dielectric layer with the aluminum gallium nitride layer exhausted to form metal-
Edge body-semiconductor (MIS) structure.
4. semiconductor devices as claimed in claim 2, which is characterized in that the silicon substrate is P (111) type silicon substrate.
5. semiconductor devices as claimed in claim 2, which is characterized in that the nitride buffer layer and the aluminum gallium nitride layer
Between be formed with Two-dimensional electron gas channel.
6. semiconductor devices as described in claim 1, which is characterized in that the source electrode and/or the drain electrode are by Ohmic contact
Metal composition, the metal ohmic contact successively includes: the first titanium coating, aluminum metal layer, the second titanium coating from bottom to up
And titanium nitride layer.
7. semiconductor devices as claimed in claim 6, which is characterized in that the grid is made of the metal ohmic contact,
The material of the gate metal layer is titanium nitride, and the material of the dielectric layer is silicon nitride, silica or hafnium oxide.
8. a kind of semiconductor devices characterized by comprising
Semiconductor substrate is formed with Two-dimensional electron gas channel in the semiconductor substrate；
First medium layer is arranged on the semiconductor substrate, and first grid contact hole through the first medium layer and prolongs
Protrude into the semiconductor-based intralamellar part；
Second dielectric layer is arranged on the first medium layer and extends in the first grid contact hole to cover described the
The bottom in one gate contact hole, and second grid contact hole through the second dielectric layer and the first medium layer and extends into
The semiconductor-based intralamellar part and the second dielectric layer do not cover the bottom of the second grid contact hole, and described second
Gate contact hole is connected with the first grid contact hole；
Gate metal layer is arranged in the second dielectric layer and extends in the first grid contact hole with covering positioned at institute
It states the second dielectric layer of the bottom of first grid contact hole and extends into the second grid contact hole to cover
The bottom of second grid contact hole is stated, source contact openings and drain contact hole run through the gate metal layer, the second medium
Layer and the first medium layer；
Grid is arranged in the gate metal layer and fills the first grid contact hole and the second grid contact hole；
Source electrode and drain electrode is arranged in the gate metal layer and fills the source contact openings and the drain contact respectively
Hole.
9. semiconductor devices as claimed in claim 8, which is characterized in that the width of the first grid contact hole and described the
The ratio of the width in two gate contact holes is 1:1.
10. a kind of production method of semiconductor devices, which is characterized in that comprising steps of
First medium layer is formed on a semiconductor substrate, wherein having Two-dimensional electron gas channel in the semiconductor substrate；
The first medium layer and the semiconductor substrate are etched to form first grid contact hole, wherein the first grid connects
Contact hole is through the first medium layer and extends into the semiconductor-based intralamellar part；
Second dielectric layer is formed on the first medium layer and the second dielectric layer is made to extend to the first grid contact
The bottom of the first grid contact hole is covered in hole；
The second dielectric layer, the first medium layer and the semiconductor substrate are etched to form second grid contact hole,
Described in second grid contact hole through the second dielectric layer and the first medium layer and extend into the semiconductor substrate
Inside；
Gate metal layer is formed in the second dielectric layer and the gate metal layer is made to extend to the first grid contact
To cover the second dielectric layer for the bottom for being located at the first grid contact hole and extend to the second grid in hole
The bottom of the second grid contact hole is covered in contact hole；
The gate metal layer, the second dielectric layer and the first medium layer is etched to connect to form source contact openings and drain electrode
Contact hole；
Ohmic contact metal layer is formed in the gate metal layer and fills the ohmic contact metal layer to described first
Gate contact hole, the second grid contact hole, the source contact openings and the drain contact hole；
The ohmic contact metal layer and the gate metal layer are etched to form the corresponding first grid contact hole and described
The drain electrode of the grid of second grid contact hole, the source electrode of the corresponding source contact openings and the corresponding drain contact hole, thus
The semiconductor devices is made.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810803338.9A CN109103104A (en) | 2018-07-20 | 2018-07-20 | Semiconductor devices and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810803338.9A CN109103104A (en) | 2018-07-20 | 2018-07-20 | Semiconductor devices and preparation method thereof |
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| CN109103104A true CN109103104A (en) | 2018-12-28 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111508840A (en) * | 2020-06-16 | 2020-08-07 | 浙江集迈科微电子有限公司 | Stepped GaN gate device and preparation method thereof |
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2018
- 2018-07-20 CN CN201810803338.9A patent/CN109103104A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111508840A (en) * | 2020-06-16 | 2020-08-07 | 浙江集迈科微电子有限公司 | Stepped GaN gate device and preparation method thereof |
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