CN109037330A - Semiconductor devices and preparation method thereof - Google Patents
Semiconductor devices and preparation method thereof Download PDFInfo
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- CN109037330A CN109037330A CN201810803203.2A CN201810803203A CN109037330A CN 109037330 A CN109037330 A CN 109037330A CN 201810803203 A CN201810803203 A CN 201810803203A CN 109037330 A CN109037330 A CN 109037330A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 91
- 238000002360 preparation method Methods 0.000 title abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 230000005533 two-dimensional electron gas Effects 0.000 claims abstract description 11
- 229910002601 GaN Inorganic materials 0.000 claims description 86
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 77
- 229910052751 metal Inorganic materials 0.000 claims description 55
- 239000002184 metal Substances 0.000 claims description 55
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 239000010936 titanium Substances 0.000 claims description 13
- 150000004767 nitrides Chemical class 0.000 claims description 12
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 229910052719 titanium Inorganic materials 0.000 claims description 11
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 10
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 230000005684 electric field Effects 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000009977 dual effect Effects 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 229910052733 gallium Inorganic materials 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 229910052749 magnesium Inorganic materials 0.000 description 2
- 239000011777 magnesium Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The present invention relates to technical field of semiconductors, a kind of semiconductor devices and preparation method thereof is provided.The semiconductor devices includes: semiconductor substrate, and inside is formed with Two-dimensional electron gas channel；Source electrode and drain electrode is arranged on the semiconductor substrate and bottom is connected with the semiconductor substrate respectively；Grid, it is arranged on the semiconductor substrate and bottom is connected by a multilayered structure with the semiconductor substrate, wherein, the multilayered structure includes first area and second area arranged side by side, the width of the first area is equal to the width of the second area, and the doping concentration of the first area is different from the doping concentration of the second area.Semiconductor devices of the invention can obtain better devices switch characteristic.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of semiconductor devices and a kind of systems of semiconductor devices
Make method.
Background technique
For P-type grid electrode semiconductor devices due to technical maturity, device stability is good, is very suitable to realize enhanced.But grid
The design parameter (such as doping concentration, gate, the work function of gate metal) of pole is special for the ON state and OFF state electricity of device
The influence of property is all vital.For example, threshold voltage and output electric current are all by magnesium doping concentration and the grid gold of grid
Belong to the influence of work function.One inappropriate gate parameters will cause threshold voltage it is low and output electric current it is small, cause device respectively
The problem of safety and output power；Secondly as channel electricity of the grid to channel electric field action, under OFF state, below grid
Field size is also influenced by parameters such as gate dopant concentrations；A series of reliability can be caused in view of the big electric field of OFF state lower channel
Problem (hot carrier, electronics capture, defect generation etc.), therefore reliability of the design of gate parameters to device under the bias of direction
Also there is direct relation.It is, therefore, desirable to provide one kind can optimised devices structure, improve p-type dopes gate structure semiconductor device
Semiconductor devices of on-state characteristic of part and preparation method thereof.
Summary of the invention
To solve the above problems, the present invention provides semiconductor devices and its production side of a kind of grid dual area doped structure
Method with optimised devices structure, can improve the on-state characteristic of the semiconductor devices of p-type dopes gate structure.
A kind of semiconductor devices provided in an embodiment of the present invention, comprising: semiconductor substrate, inside are formed with two-dimensional electron gas
Channel；Source electrode and drain electrode is arranged on the semiconductor substrate and bottom is connected with the semiconductor substrate respectively；Grid,
It is arranged on the semiconductor substrate and bottom is connected by a multilayered structure with the semiconductor substrate, wherein is described
Multilayered structure includes first area and second area arranged side by side, and the width of the first area is equal to the second area
Width, the doping concentration of the first area are different from the doping concentration of the second area.
The present invention in one embodiment, the first area and the second area include from the bottom to top successively
The silicon dioxide layer and titanium nitride layer of setting；Wherein, the first area further includes the first p-type epitaxial layer of gallium nitride, and described
Two regions further include the second p-type epitaxial layer of gallium nitride, outside the first p-type epitaxial layer of gallium nitride and the second p-type gallium nitride
Prolong layer and runs through the silicon dioxide layer to be connected with the semiconductor substrate, the first p-type epitaxial layer of gallium nitride and institute
The doping concentration for stating the second p-type epitaxial layer of gallium nitride is different.
On the other hand, a kind of semiconductor devices provided in an embodiment of the present invention, comprising: semiconductor substrate；Dielectric layer, setting
In on the semiconductor substrate；First p-type epitaxial layer of gallium nitride and the second p-type epitaxial layer of gallium nitride, are set to the semiconductor
The first aperture and the second aperture are filled on substrate and respectively, wherein first aperture and second aperture run through described
Dielectric layer；Gate metal layer is set to the dielectric layer, the first p-type epitaxial layer of gallium nitride and the second p-type gallium nitride
On epitaxial layer；Source electrode and drain electrode is set in the gate metal layer and fills source contact openings and drain contact hole, institute respectively
It states source contact openings and the drain contact hole runs through the gate metal layer and the dielectric layer；And grid, it is set to
In the gate metal layer, and projection of the grid on the semiconductor substrate at least covers first aperture and described
Second aperture region；Wherein, outside the doping concentration of the first p-type epitaxial layer of gallium nitride and the second p-type gallium nitride
The doping concentration for prolonging layer is different
The present invention in one embodiment, the doping concentration of the first p-type epitaxial layer of gallium nitride is greater than described the
The doping concentration of two p-type epitaxial layer of gallium nitride.
The present invention in one embodiment, first aperture is connected with second aperture.
The present invention in one embodiment, the dielectric layer is made of silica, and the gate metal layer is by nitrogen
Change titanium composition, the source electrode, drain electrode and/or the grid are made of metal ohmic contact.
The present invention in one embodiment, the metal ohmic contact include from the bottom to top successively include: the first titanium
Metal layer, aluminum metal layer, the second titanium coating and titanium nitride layer.
The present invention in one embodiment, the semiconductor substrate includes: silicon substrate, and is set to silicon lining
The nitride buffer layer of bottom surface and the aluminum gallium nitride layer for being set to the nitride buffer layer surface；The nitride buffer layer
Two-dimensional electron gas channel is additionally provided between the aluminum gallium nitride layer.
The present invention in one embodiment, the source electrode and it is described drain electrode one of between person and the grid also shape
At there is the first clearance hole, the other of the source electrode and the drain electrode are also formed with the second clearance hole between the grid,
First clearance hole and second clearance hole run through the gate metal layer and the dielectric layer, first clearance hole
Width be less than second clearance hole width, first aperture relative to second aperture closer to described first every
From hole, the doping concentration of the first p-type epitaxial layer of gallium nitride is greater than the doping concentration of the second p-type epitaxial layer of gallium nitride.
Another aspect, a kind of production method of semiconductor devices provided in an embodiment of the present invention, comprising steps of in semiconductor
Dielectric layer is formed on substrate, wherein being formed with Two-dimensional electron gas channel in the semiconductor substrate；The dielectric layer is etched with shape
It at the first aperture, and grows and obtains the first p-type epitaxial layer of gallium nitride, wherein first aperture runs through the dielectric layer, described
First p-type epitaxial layer of gallium nitride fills first aperture；The dielectric layer is etched to form the second aperture, and grows and obtains the
Two p-type epitaxial layer of gallium nitride, wherein second aperture runs through the dielectric layer, the second p-type epitaxial layer of gallium nitride filling
Second aperture；On the dielectric layer, the first p-type epitaxial layer of gallium nitride and the second p-type epitaxial layer of gallium nitride
Form gate metal layer；The gate metal layer and the dielectric layer are etched to form source contact openings and drain contact hole；?
Ohmic contact metal layer is formed in the gate metal layer and make the ohmic contact metal layer fill the source contact openings and
The drain contact hole；The ohmic contact metal layer, the gate metal layer and the dielectric layer are etched to form corresponding institute
State the source electrode of source contact openings, the drain electrode of the corresponding drain contact hole, corresponding first aperture and second aperture
Grid, so that the semiconductor devices be made.
In embodiments of the present invention, the present invention optimizes device architecture, grid dual area doped structure is proposed, in reality
While now improving threshold voltage, High Output Current is mentioned.
Detailed description of the invention
Fig. 1 is the partial profile structure of the active region of semiconductor devices in one embodiment of the invention.
Fig. 2A is the obtained device active region of step 1 of the production method of semiconductor devices in one embodiment of the invention
The partial profile structure in domain.
Fig. 2 B is the obtained device active region of step 2 of the production method of semiconductor devices in one embodiment of the invention
The partial profile structure in domain.
Fig. 2 C is the obtained device active region of step 3 of the production method of semiconductor devices in one embodiment of the invention
The partial profile structure in domain.
Fig. 2 D is the obtained device active region of step 4 of the production method of semiconductor devices in one embodiment of the invention
The partial profile structure in domain.
Fig. 2 E is the obtained device active region of step 5 of the production method of semiconductor devices in one embodiment of the invention
The partial profile structure in domain.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
As shown in Figure 1, a kind of semiconductor devices 100 that one embodiment of the present of invention provides, specifically includes that semiconductor-based
Plate 110, dielectric layer 120, the first p-type epitaxial layer of gallium nitride 130a, the second p-type epitaxial layer of gallium nitride 130b, gate metal layer
140, source electrode 150a, drain electrode 150b and grid 150c.
Wherein, dielectric layer 120 is set on semiconductor substrate 110.
First p-type epitaxial layer of gallium nitride 130a and the second p-type epitaxial layer of gallium nitride 130b are for example set to semiconductor substrate
The first aperture GH1 and the second aperture GH2 are filled on 110 and respectively, wherein the first aperture GH1 and the second aperture GH2 run through
Dielectric layer 120.
Gate metal layer 140 is for example set to dielectric layer 120, the first p-type epitaxial layer of gallium nitride 130a and the nitridation of the second p-type
On gallium epitaxial layer 130b.
Source electrode 150a and drain electrode 150b is for example set in gate metal layer 140 and fills source contact openings SH and leakage respectively
Pole contact hole DH, source contact openings SH and drain contact hole DH run through gate metal layer 140 and dielectric layer 120.Source electrode 150a
It is for example connected respectively with semiconductor substrate 110 with the bottom of drain electrode 150b.
Grid 150c is set in gate metal layer 140, and projection of the grid 150c on semiconductor substrate 110 is at least
Cover the first aperture GH1 and the second region aperture GH2.Specifically, as shown in Figure 1, the bottom of grid 150c for example passes through
Gate metal layer 140, the second p-type epitaxial layer of gallium nitride 130b, the first p-type epitaxy of gallium nitride positioned at grid 150c bottom part down
The multilayered structure that layer 130a and dielectric layer 120 form is connected with semiconductor substrate 110, wherein the multilayered structure includes simultaneously
The first area Z1 and second area Z2 of setting are arranged, the width of first area Z1 is equal to the width of second area Z2, first area
The doping concentration of Z1 is different from the doping concentration of second area Z2, such as the doping concentration of first area Z1 is 4 × 1019cm-3,
The width of first area Z1 is 1 μm；The doping concentration of second area Z2 is 1 × 1017cm-3, the width of second area Z2 is 1 μm.
First area Z1 and second area Z2 includes the dielectric layer 120 set gradually from the bottom to top and gate metal layer 140, the firstth area
Domain Z1 further includes that the first p-type epitaxial layer of gallium nitride 130a, second area Z2 further includes the second p-type epitaxial layer of gallium nitride 130b,
In, the second p-type epitaxial layer of gallium nitride 130b of the first p-type epitaxial layer of gallium nitride 130a and second area Z2 of first area Z1 are equal
Through dielectric layer 120 to be connected with semiconductor substrate 110, outside the first p-type epitaxial layer of gallium nitride 130a and the second p-type gallium nitride
The doping concentration for prolonging layer 130b is different.
Wherein, the doping concentration of the first p-type epitaxial layer of gallium nitride 130a is for example with the second p-type epitaxial layer of gallium nitride 130b's
Doping concentration is different.First p-type epitaxial layer of gallium nitride 130a and the second p-type epitaxial layer of gallium nitride 130b is, for example, to use magnesium conduct
What dopant was grown.
The doping concentration of first p-type epitaxial layer of gallium nitride 130a is greater than mixing for the second p-type epitaxial layer of gallium nitride 130b
Miscellaneous concentration.Specifically, the doping concentration of the first p-type epitaxial layer of gallium nitride 130a and the second p-type epitaxial layer of gallium nitride 130b is for example
Respectively 4 × 1019cm-3With 1 × 1017cm-3
First aperture GH1 is for example connected with the second aperture GH2.
Dielectric layer 120 is for example made of silica, and gate metal layer 140 is for example made of titanium nitride, source electrode 150a, leakage
Pole 150b and/or grid 150c are for example made of metal ohmic contact, and metal ohmic contact for example including successively wrapping from the bottom to top
It includes: the first titanium coating (Ti), aluminum metal layer (Al), the second titanium coating (Ti) and titanium nitride layer (TiN).
Semiconductor substrate 110 includes: silicon substrate 111, and is set to the nitride buffer layer 113 on 111 surface of silicon substrate
With the aluminum gallium nitride layer 115 for being set to 113 surface of nitride buffer layer；Between nitride buffer layer 113 and aluminum gallium nitride layer 115
It is additionally provided with Two-dimensional electron gas channel 117.
The first clearance hole PH1 is also formed between source electrode 150a and grid 150c, between the 150b and grid 150c that drains also
It is formed with the second clearance hole PH2, the first clearance hole PH1 and the second clearance hole PH2 and runs through gate metal layer 140 and dielectric layer
Width of the width of 120, the first clearance hole PH1 less than the second clearance hole PH2, the first aperture GH1 relative to the second aperture GH2 more
Close to the first clearance hole PH1.In some other embodiment, it can also be and be also formed with the between drain electrode 150b and grid 150c
One clearance hole PH1 is also formed with the second clearance hole PH2 between source electrode 150a and grid 150c.
Optionally, the ratio of the width of the width of the first aperture GH1 and the second aperture GH2 is 1:1, it is, of course, also possible to be
Other suitable ratio values, such as 1:2,1:3,2:1 etc..Certainly, the embodiment of the present invention is not limited thereto system, other one
In a little embodiments, the first aperture GH1 and the second aperture GH2 can also be and be spaced apart from each other setting.
Silicon substrate 111 is, for example, P (111) type silicon substrate.
The thickness of nitride buffer layer 113 is greater than 3 microns.
In addition, the embodiment of the present invention also provides the production method of above-mentioned semiconductor device 100.Such as Fig. 2A to 2E and Fig. 1
It is shown, it is the partial structurtes section in obtained device active region domain in each step of the production method of semiconductor devices 100
Schematic diagram.Specifically, the production method of semiconductor devices 100 can include:
Step 1: as shown in Figure 2 A, dielectric layer 120 is formed on semiconductor substrate 110, wherein shape in semiconductor substrate 110
At there is Two-dimensional electron gas channel 117.Specifically, PECVD (Plasma Enhanced Chemical Vapor Deposition,
Plasma enhanced chemical vapor deposition) deposit layer of silicon dioxide is to form dielectric layer 120, for being passivated semiconductor substrate
Its surface state is eliminated on 110 surfaces, to improve the reliability of finally formed semiconductor devices 100.
Further, before step 1, it such as further comprises the steps of: and to form semiconductor substrate 110.Specifically, in silicon substrate
Be sequentially depositing nitride buffer layer 113 and aluminum gallium nitride layer 115 on 111, nitride buffer layer 113 and aluminum gallium nitride layer 115 it
Between formed Two-dimensional electron gas channel 117, ultimately form semiconductor substrate 110.Gallium nitride is third generation semiconductor material with wide forbidden band,
With the characteristics such as big forbidden bandwidth, high electron saturation velocities, high breakdown electric field, higher heat-conductivity, corrosion-resistant and radiation resistance,
And there is stronger advantage under high pressure, high frequency, high temperature, high-power and Flouride-resistani acid phesphatase environmental condition, to be research short wavelength light
The optimal material of electronic device and high voltagehigh frequency rate high power device；Wherein, big forbidden bandwidth is 3.4 electron-volts, high electronics
Saturation rate is 2e7 centimeters per second, and high breakdown electric field is 1e10~-3e10 volts per cm.
Step 2: as shown in Figure 2 B, etching media layer 120 obtains the nitridation of the first p-type to form the first aperture GH1, and grow
Gallium epitaxial layer 130a, wherein the first aperture GH1 runs through dielectric layer 120, and the first p-type epitaxial layer of gallium nitride 130a filling first is opened
Hole GH1.Specifically, such as dry etching dielectric layer 120 forms the first aperture GH1, such as uses MOCVD (Metal-organic
Chemical Vapor Deposition, metallo-organic compound chemical gaseous phase deposition) grow to obtain the first p-type gallium nitride
Epitaxial layer 130a.
Step 3: as shown in Figure 2 C, etching the first p-type epitaxial layer of gallium nitride 130a and dielectric layer 120 to form the second aperture
GH2, and grow and obtain the second p-type epitaxial layer of gallium nitride 130b, wherein the second aperture GH2 runs through dielectric layer 120, the second p-type nitrogen
Change gallium epitaxial layer 130b and fills the second aperture GH2.Specifically, dry etching forms the second aperture GH2, and MOCVD grows to obtain the
Two p-type epitaxial layer of gallium nitride 130b.The doping concentration of first p-type epitaxial layer of gallium nitride 130a is greater than the second p-type epitaxy of gallium nitride
The doping concentration of layer 130b.
Step 4: as shown in Figure 2 D, outside dielectric layer 120, the first p-type epitaxial layer of gallium nitride 130a and the second p-type gallium nitride
Prolong and forms gate metal layer 140 on layer 130b.Specifically, in dielectric layer 120, the first p-type epitaxial layer of gallium nitride 130a and the 2nd P
The upper surface of type epitaxial layer of gallium nitride 130b deposits one layer of titanium nitride metal to form gate metal layer 140.
Step 5: as shown in Figure 2 E, etching gate metal layer 140 and dielectric layer 120 to form source contact openings SH and drain electrode
Contact hole DH；Ohmic contact metal layer 150 is formed in gate metal layer 140 and ohmic contact metal layer 150 is made to fill source electrode
Contact hole SH and drain contact hole DH.Specifically, etch gate metal layer 140 and dielectric layer 120 formed source contact openings SH and
Drain contact hole DH guarantees that etching stopping in aluminum gallium nitride layer 115, avoids causing to aluminum gallium nitride layer 115 compared with macrolesion, so that
There are sufficient concentrations of electronics in 117 channel of Two-dimensional electron gas channel, maintain the large current characteristic of device.Later, PVD
(Physical Vapor Deposition, physical vapour deposition (PVD)) deposit ohmic contacts metal, that is, being sequentially depositing the first titanium
Metal layer, aluminum metal layer, the second titanium coating and titanium nitride layer are to form ohmic contact metal layer 150.Specifically, the first titanium
Belong to layer, aluminum metal layer, the second titanium coating and titanium nitride layer deposition thickness be for example respectively 200 angstroms, 1200 angstroms, 200 angstroms and
200 angstroms.
Step 6: as shown in Figure 1, etching ohmic contact metal layer 150, gate metal layer 140 and dielectric layer 120 are to form
The source electrode 150a of corresponding source contact openings SH, the drain electrode 150b of corresponding drain contact hole DH, corresponding first aperture GH1 and second are opened
The grid 150c of hole GH2, so that semiconductor devices 100 be made.
By the above process, the semiconductor devices 100 of a complete grid dual area doped structure completes.It is so unlimited
In this, in other embodiments, also changes or increase other steps, to complete semiconductor devices 100.
In addition, it is noted that above-mentioned source electrode and drain electrode can be interchanged, so that one of source electrode and drain electrode can claim
Be the first source/drain, the another of source electrode and drain electrode can be referred to as the second source/drain；Correspondingly, above-mentioned source contact openings and
One of drain contact hole can be referred to as the first source drain contact hole, and above-mentioned source contact openings and the another of drain contact hole can
To be referred to as the second source drain contact hole.
In conclusion the embodiment of the present invention is optimized by the structure to semiconductor devices, a kind of grid two-region is obtained
The semiconductor devices 100 of domain doped structure with optimised devices structure, can improve the semiconductor devices of p-type dopes gate structure
On-state characteristic can be realized low current leakage by the way that grid is highly doped, and make threshold voltage positively biased；The low-doped pn-junction of grid
Potential barrier is lower, and when grid positively biased is conducive to hole injection, attracts electronics and then forms output electric current, under OFF state, dual area is mixed
Miscellaneous structure also has field plate effect, makes field distribution in two edges of regions of grid, slows down the reliability as caused by big electric field and ask
Topic.
In several embodiments provided herein, it should be understood that disclosed system, device and/or method, it can
To realize by another way.For example, the apparatus embodiments described above are merely exemplary, for example, the unit/
The division of module, only a kind of logical function partition, there may be another division manner in actual implementation, such as multichannel unit
Or module can be combined or can be integrated into another system, or some features can be ignored or not executed.Another point, institute
Display or the mutual coupling, direct-coupling or communication connection discussed can be through some interfaces, device or unit
Indirect coupling or communication connection can be electrical property, mechanical or other forms.
The units/modules as illustrated by the separation member may or may not be physically separated, as
The component that units/modules are shown may or may not be physical unit, it can and it is in one place, or can also be with
It is distributed on multi-channel network unit.Some or all of units/modules therein can be selected to realize according to the actual needs
The purpose of this embodiment scheme.
Finally, it should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
Present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: it still may be used
To modify the technical solutions described in the foregoing embodiments or equivalent replacement of some of the technical features；
And these are modified or replaceed, technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution spirit and
Range.
Claims (10)
1. a kind of semiconductor devices characterized by comprising
Semiconductor substrate, inside are formed with Two-dimensional electron gas channel；
Source electrode and drain electrode, setting are connected on the semiconductor substrate and respectively with the semiconductor substrate；
Grid is arranged on the semiconductor substrate and is connected by a multilayered structure with the semiconductor substrate,
In, the multilayered structure includes first area and second area arranged side by side, and the width of the first area is equal to described the
The width in two regions, the doping concentration of the first area are different from the doping concentration of the second area.
2. semiconductor devices as described in claim 1, which is characterized in that the first area and the second area include
The silicon dioxide layer and titanium nitride layer set gradually from the bottom to top；Wherein, the first area further includes outside the first p-type gallium nitride
Prolong layer, the second area further includes the second p-type epitaxial layer of gallium nitride, the first p-type epitaxial layer of gallium nitride and the 2nd P
Type epitaxial layer of gallium nitride runs through the silicon dioxide layer to be connected with the semiconductor substrate, the first p-type gallium nitride
Epitaxial layer is different from the doping concentration of the second p-type epitaxial layer of gallium nitride.
3. a kind of semiconductor devices characterized by comprising
Semiconductor substrate；
Dielectric layer is set on the semiconductor substrate；
First p-type epitaxial layer of gallium nitride and the second p-type epitaxial layer of gallium nitride are set on the semiconductor substrate and fill out respectively
Fill the first aperture and the second aperture, wherein first aperture and second aperture run through the dielectric layer；
Gate metal layer is set to outside the dielectric layer, the first p-type epitaxial layer of gallium nitride and the second p-type gallium nitride
Prolong on layer；
Source electrode and drain electrode is set in the gate metal layer and fills source contact openings and drain contact hole, the source respectively
Pole contact hole and the drain contact hole run through the gate metal layer and the dielectric layer；And
Grid is set in the gate metal layer, and projection of the grid on the semiconductor substrate at least covers institute
State the first aperture and second aperture region；
Wherein, the doping concentration of the doping concentration of the first p-type epitaxial layer of gallium nitride and the second p-type epitaxial layer of gallium nitride
It is different.
4. semiconductor devices as claimed in claim 3, which is characterized in that the doping of the first p-type epitaxial layer of gallium nitride is dense
Degree is greater than the doping concentration of the second p-type epitaxial layer of gallium nitride.
5. semiconductor devices as claimed in claim 3, which is characterized in that first aperture is connected with second aperture
It is logical.
6. semiconductor devices as claimed in claim 3, which is characterized in that the dielectric layer is made of silica, the grid
Pole metal layer is made of titanium nitride.
7. semiconductor devices as claimed in claim 3, which is characterized in that the source electrode, drain electrode and/or the grid are by ohm
Metal composition is contacted, the metal ohmic contact including successively including: the first titanium coating, aluminum metal layer, second from the bottom to top
Titanium coating and titanium nitride layer.
8. semiconductor devices as claimed in claim 3, which is characterized in that the semiconductor substrate includes: silicon substrate, Yi Jishe
It is placed in the nitride buffer layer of the surface of silicon and is set to the aluminum gallium nitride layer on the nitride buffer layer surface；It is described
Two-dimensional electron gas channel is additionally provided between nitride buffer layer and the aluminum gallium nitride layer.
9. semiconductor devices as claimed in claim 3, which is characterized in that one of the source electrode and the drain electrode person and described
The first clearance hole is also formed between grid, the other of the source electrode and the drain electrode are also formed between the grid
Second clearance hole, first clearance hole and second clearance hole run through the gate metal layer and the dielectric layer, institute
The width for stating the first clearance hole is less than the width of second clearance hole, and first aperture is more leaned on relative to second aperture
The doping concentration of nearly first clearance hole, the first p-type epitaxial layer of gallium nitride is greater than the second p-type epitaxial layer of gallium nitride
Doping concentration.
10. a kind of production method of semiconductor devices, which is characterized in that comprising steps of
Dielectric layer is formed on a semiconductor substrate, wherein being formed with Two-dimensional electron gas channel in the semiconductor substrate；
The dielectric layer is etched to form the first aperture, and grows and obtains the first p-type epitaxial layer of gallium nitride, wherein described first
Aperture runs through the dielectric layer, and the first p-type epitaxial layer of gallium nitride fills first aperture；
The dielectric layer is etched to form the second aperture, and grows and obtains the second p-type epitaxial layer of gallium nitride, wherein described second
Aperture runs through the dielectric layer, and the second p-type epitaxial layer of gallium nitride fills second aperture；
Grid gold is formed on the dielectric layer, the first p-type epitaxial layer of gallium nitride and the second p-type epitaxial layer of gallium nitride
Belong to layer；
The gate metal layer and the dielectric layer are etched to form source contact openings and drain contact hole；
Ohmic contact metal layer is formed in the gate metal layer and the ohmic contact metal layer is made to fill the source electrode connects
Contact hole and the drain contact hole；
The ohmic contact metal layer, the gate metal layer and the dielectric layer are etched to form the corresponding source contact openings
Source electrode, the corresponding drain contact hole drain electrode, corresponding first aperture and second aperture grid, to be made
The semiconductor devices.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2022068835A1 (en) * | 2020-09-30 | 2022-04-07 | 华为技术有限公司 | High electron mobility transistor hemt device, wafer, packaging device, and electronic device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2022068835A1 (en) * | 2020-09-30 | 2022-04-07 | 华为技术有限公司 | High electron mobility transistor hemt device, wafer, packaging device, and electronic device |
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Application publication date: 20181218 |