CN107623031A - A kind of process and MIS HEMT of improvement MIS HEMT voltage endurances - Google Patents
A kind of process and MIS HEMT of improvement MIS HEMT voltage endurances Download PDFInfo
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- CN107623031A CN107623031A CN201710650844.4A CN201710650844A CN107623031A CN 107623031 A CN107623031 A CN 107623031A CN 201710650844 A CN201710650844 A CN 201710650844A CN 107623031 A CN107623031 A CN 107623031A
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Abstract
The process and MIS HEMT, the process of a kind of improvement MIS HEMT voltage endurances comprise the following steps：The wafer completed to cleaning, deposit Si3N4Dielectric layer；Prepare gate window；Deposit gate dielectric layer and gate metal；Prepare source window and drain electrode window；Deposit ohmic contacting metal, and define source metal electrode region, drain metal electrode region and gate metal electrode region；Field plate spacer medium layer is prepared in device surface；Field plate is prepared in field plate spacer medium layer surface；Sealer is prepared, and perforate is carried out to the protective layer, to open source metal electrode region, drain metal electrode region and gate metal electrode region.The present invention by introducing field plate between the gate and the drain, Electric Field Distribution in the raceway groove that changes its course, and reduces the peak value electric field between grid and drain electrode, so as to reach improvement and lift the pressure-resistant purposes of MIS HEMT.
Description
Technical field
The present invention relates to the manufacture craft of semiconductor devices, and in particular to a kind of work of improvement MIS-HEMT voltage endurances
Process and MIS-HEMT.
Background technology
Iii-v wide bandgap compound semiconductor material using gallium nitride GaN as representative, there is high breakdown electric field, high electricity
The characteristics such as son is satisfied, high drift speed and high heat conductance, therefore it is highly suitable for preparing the electric power of high-power, high speed and big voltage
Electronic device.AlGaN/GaN MIS-HEMT as the wherein most type of device of attraction, on the one hand have benefited from GaN and
Extremely strong piezoelectricity and spontaneous polarization effect between AlGaN so that high electron concentration and height are formed between GaN/AlGaN
The two-dimensional electron gas (2-DEG) of electron mobility, electron concentration is up to 1012-1013cm-2, electron mobility may be up to
2000cm2/V；On the other hand, AlGaN/GaN MIS-HEMT device technologies are simple, are suitably based on kinds of platform and are developed,
Construction cycle is short, and cost is low, is adapted to the selection of volume production scheme.
Currently, the GaN wafers used are the mode epitaxial growths for using MOCVD or MBE, and growth technique is immature,
Epitaxy defect is larger, and this causes the pressure-resistant Distance Theory of the reality of HEMT device is pressure-resistant to also have larger gap.At present, for
The problem of AlGaN/GaN devices are longitudinally pressure-resistant, it can typically be optimized by the deposition of epi dopant or high resistant film layer；And laterally
Pressure-resistant problem can typically be improved using the distance between grid (Gate) and drain electrode (Drain) is expanded, and this is undoubtedly increased
The area of device, it is unfavorable for the application of high density integrated circuit；In addition, longitudinally perpendicular device architecture can be also used sometimes, will
Device it is total it is pressure-resistant be converted into the vertical pressure-resistant of device, so as to by changing film layer structure and the thickness of material improve device
Resistance to pressure, can so ensure the miniaturization of the lateral dimension of device, but this technical matters requires higher, repeats
Rate is relatively low, is not suitable for scale of mass production.
Therefore, need badly at present exploitation it is a kind of be adapted to existing platform can be obviously improved AlGaN/GaN MIS-HEMT pressure-resistant
Technical solution, so as to lift the reliability of MIS-HEMT devices, accelerate the commercialization of device.
The content of the invention
In view of the above-mentioned problems, the application provides a kind of process and MIS-HEMT of improvement MIS-HEMT voltage endurances.
According in a first aspect, provide a kind of process of improvement MIS-HEMT voltage endurances in a kind of embodiment, including
Following steps：
The wafer completed to cleaning, deposit Si3N4Dielectric layer；
Prepare gate window；
Deposit gate dielectric layer and gate metal；
Prepare source window and drain electrode window；
Deposit ohmic contacting metal, and define source metal electrode region, drain metal electrode region and grid gold
Belong to electrode zone；
Field plate spacer medium layer is prepared in device surface；
Field plate is prepared in field plate spacer medium layer surface；
Sealer is prepared, and perforate is carried out to the protective layer, to open source metal electrode region, drain metal
Electrode zone and gate metal electrode region.
In one embodiment, it is described to prepare field plate in field plate spacer medium layer surface, including：
In field plate spacer medium layer surface deposited metal, Metal field plate is formed, the metal is Al；
The Metal field plate is etched by gold-tinted, to form default shape, wherein the default shape includes metal
Field plate extends to the size in drain metal electrode region.
In one embodiment, the preparation gate window, including：
Define area of grid；
Etch away whole Si in the area of grid being defined3N4Dielectric layer, whole GaN caps and part AlGaN potential barriers
Layer, to form gate window.
In one embodiment, the deposition gate dielectric layer and gate metal, including：
Deposit Si3N4, to form gate dielectric layer；
Depositing TiN, to form gate metal.
In one embodiment, it is described prepare source window and drain electrode window, including：
Source region and drain region are defined respectively；
Etch away the whole gate metals being defined in source region and drain region, whole gate dielectric layers and whole
Si3N4Dielectric layer, etching stopping is on the surface of GaN cap.
In one embodiment, it is described to prepare field plate spacer medium layer in device surface, including：Deposited in device surface
Si3N4, as isolating for field plate and metal electrode region.
In one embodiment, it is described to prepare sealer, and perforate is carried out to the protective layer, including：
It is sequentially depositing TEOS, Si3N4And TEOS, to form sealer；
Opening area is defined, source metal electrode region, drain metal electrode region and grid are opened by etching
Metal electrode region, wherein gate metal electrode region are brought out Mesa platforms.
According to second aspect, a kind of MIS-HEMT is provided in a kind of embodiment, it passes through described in any of the above-described embodiment
Process manufactures to obtain.
According to the process and MIS-HEMT of the improvement MIS-HEMT voltage endurances of above-described embodiment, by grid
Field plate is introduced between drain electrode, Electric Field Distribution in the raceway groove that changes its course, the peak value electric field between grid and drain electrode is reduced, so as to reach
Improve and lift the pressure-resistant purposes of MIS-HEMT.
Brief description of the drawings
Fig. 1 is a kind of flow chart of the process of the improvement MIS-HEMT voltage endurances of embodiment；
Fig. 2 is in a kind of process of the improvement MIS-HEMT voltage endurances of embodiment, shows post-depositional Si3N4It is situated between
The device profile map of matter layer；
Fig. 3 is in a kind of process of the improvement MIS-HEMT voltage endurances of embodiment, shows prepared grid
The device profile map of window；
Fig. 4 is in a kind of process of the improvement MIS-HEMT voltage endurances of embodiment, and the grid that displaying deposition is formed are situated between
The device profile map of matter layer and gate metal；
Fig. 5 is in a kind of process of the improvement MIS-HEMT voltage endurances of embodiment, shows prepared source electrode
The device profile map of window and drain electrode window；
Fig. 6 is in a kind of process of the improvement MIS-HEMT voltage endurances of embodiment, is defined after showing deposited metal
Source electrode, the device profile map in drain and gate metal electrode region gone out；
Fig. 7 be a kind of embodiment improvements MIS-HEMT voltage endurances process in, show prepared by field plate every
From the device profile map of dielectric layer；
Fig. 8 is in a kind of process of the improvement MIS-HEMT voltage endurances of embodiment, shows prepared field plate
Device profile map；
Fig. 9 is that displaying prepares sealer in a kind of process of the improvement MIS-HEMT voltage endurances of embodiment
And the device profile map after perforate, the sectional views of MIS-HEMT devices can also be regarded as；
Figure 10 is a kind of top view of the MIS-HEMT devices of embodiment.
Embodiment
The present invention is described in further detail below by embodiment combination accompanying drawing.Wherein different embodiment party
Similar component employs associated similar element numbers in formula.In the following embodiments, many detailed descriptions be for
The application is better understood.However, those skilled in the art can be without lifting an eyebrow recognize, which part
Feature is dispensed in varied situations, or can be substituted by other elements, material, method.In some situations
Under, the related certain operations of the application do not show or described in the description, and this is the core in order to avoid the application
Part is flooded by excessive description, and to those skilled in the art, be described in detail these associative operations be not must
Want, they can completely understand associative operation at the general technology knowledge of description and this area in specification.
In addition, feature described in this description, operation or feature can combine to form respectively in any suitable way
Kind embodiment.Meanwhile each step in method description or action can also can be aobvious and easy according to those skilled in the art institute
The mode carry out order exchange or adjustment seen.Therefore, the various orders in specification and drawings are intended merely to clearly describe a certain
Individual embodiment, necessary order is not meant to be, wherein some sequentially must comply with unless otherwise indicated.
It is herein part institute serialization number itself, such as " first ", " second " etc., is only used for distinguishing described object,
Without any order or art-recognized meanings.And " connection ", " connection " described in the application, unless otherwise instructed, include directly and
It is indirectly connected with (connection).
First some the proprietary english nouns occurred in the present invention are illustrated.
HEMT：Full name High Electron Mobility Transistor, HEMT；
CMOS：Full name Complementary Metal Oxide Semiconductor, compensated semiconductor's metal oxidation
Thing semiconductor；
GaN：Gallium nitride, a kind of wide bandgap semiconductor compound, be third generation semiconductor representative, be especially suitable for big work(
The making of rate and microwave device；
PVD：Full name Physical Vapor Deposition, physical vapour deposition (PVD), are the most frequently used in semiconductor technology
Metal deposit mode；
LPCVD：Full name Low Pressure Chemical Vapor Deposition, low-pressure chemical vapor deposition, it is
One of major way that high quality dielectric film deposits in semiconductor technology；
MOCVD：Full name Metal-organic Chemical Vapor Deposition, metallo-organic compound chemistry
Gaseous phase deposition, a kind of new vapour phase epitaxy growing technology to grow up on the basis of vapor phase epitaxial growth (VPE), mainly
Growth for compound semiconductors such as GaN/SiC；
PECVD：Full name Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical
Vapour deposition, it is one of major way that high quality dielectric film deposits in semiconductor technology, is mainly used in last part technology sheath
Deposition；
RIE:Full name Reactive Ion Etching, reactive ion etching, a kind of microelectronics dry corrosion process.
ICP：Full name Inductively Coupled Plasma, plasma inductive, a kind of microelectronics dry method are rotten
Etching technique.
MIS：Full name Metal-Insulator-Semiconductor, metal-insulator semiconductor knot, it is semiconductor
One of most important device architecture in device.
Below by some embodiments, and with reference to accompanying drawing, the present invention will be described.
Fig. 1 is refer to, a kind of process of improvement MIS-HEMT voltage endurances is provided in an embodiment, it includes step
Rapid S10~S80.
Step S10：The wafer completed to cleaning, deposit Si3N4Dielectric layer.In one embodiment, it can pass through LPCVD's
Mode deposits Si3N4Dielectric layer, Si3N4Dielectric layer can eliminate surface state with passivated surface, improve the reliability of device.Such as
Shown in Fig. 2, post-depositional Si is illustrated3N4Dielectric layer.
Step S20：Prepare grid (Gate) window.In one embodiment, step S20 can specifically include：First define grid
Polar region domain, area of grid is defined for example with gold-tinted；Whole Si in the area of grid being defined are etched away again3N4Dielectric layer,
Whole GaN caps and part AlGaN potential barrier, to form gate window, such as it can successively use SF6And Cl2For gas source
ICP lithographic methods etch gate window.MIS-HEMT devices can be regulated and controled by the thickness for adjusting remaining AlGaN potential barrier
The threshold voltage size of part.As shown in Fig. 3, prepared gate window is illustrated.
Step S30：Deposit gate dielectric layer and gate metal.In one embodiment, step S30 can include：Using for example
LPCVD mode deposits Si3N4, to form gate dielectric layer, its thickness can be adjusted according to the needs to grid control ability
It is whole, generally no greater than 50nm；The depositing TiN by the way of PVD, to form gate metal, it is mainly used in doing in Gate metals
The part of high work function, also it is used for preventing the Al metals of subsequent deposition from diffusing into AlGaN or GaN in pyroprocess in addition
In epitaxial layer.As shown in figure 4, illustrate gate dielectric layer and gate metal that deposition is formed.
Step S40：Prepare source window and drain electrode window.In one embodiment, step S40 can include：Define respectively
Source region and drain region, defined for example with gold-tinted；Such as SF is used again6Etched away for the ICP modes of gas source
Whole gate metals, whole gate dielectric layers and the whole Si being defined in source region and drain region3N4Dielectric layer, etch-stop
Only on the surface of GaN cap, avoid to AlGaN compared with macrolesion, so as to sufficient concentrations of electronics in 2DEG raceway grooves be present, maintain
The large current characteristic of device.As shown in Fig. 5, prepared source window and drain electrode window are illustrated.
Step S50：Deposit ohmic contacting metal, and define source electrode (Source) metal electrode region, drain electrode
(Drain) metal electrode region and grid (Gate) metal electrode region.Metal structure can be Ti/Al/Ti/TiN, thickness
For 200A/1200A/200A/200A.Metal deposition can be by the way of magnetron sputtering, to make Ohmic contact good, metal
HF cleaning contact holes can be carried out before deposit, will be in N after Metal deposition2850 DEG C, 45s short annealing are carried out under atmosphere
(RTS).As shown in fig. 6, illustrate deposited metal, the source metal electrode region that defines, drain metal electrode region and
Gate metal electrode region.
Step S60：Field plate spacer medium layer is prepared in device surface.In one embodiment, step S60 can include：Adopt
With such as PECVD mode Si is deposited in device surface3N4, can be with as isolating for field plate and metal electrode region, after deposition
Unnecessary dielectric layer is removed by gold-tinted etching.The effect of this field plate spacer medium layer in addition to it can isolate 2 layers of metal,
It may further be used to passive metal grid metal surface, suppressor grid electric leakage and current collapse effect.As shown in fig. 7, illustrate prepared
Field plate spacer medium layer.
Step S70：Field plate (Field Plate) is prepared in field plate spacer medium layer surface.This step is the core of the present invention
Heart step.In one embodiment, step S70 can include：Sunk by the way of such as PVD in field plate spacer medium layer surface
Product metal, forms Metal field plate, metal can be Al；The Metal field plate is etched by gold-tinted, to form default shape,
Wherein default shape includes the size that Metal field plate extends to drain metal electrode region.Drain electrode gold is extended to by adjustment
Belong to the field plate size of electrode zone, optimal value can be adjusted to by device is pressure-resistant.As shown in figure 8, illustrate prepared field
Plate.
Step S80：Prepare sealer, and perforate carried out to the protective layer, with open source metal electrode region,
Drain metal electrode region and gate metal electrode region.In one embodiment, step S80 can include：Using for example
PECVD mode is sequentially depositing TEOS, Si3N4And TEOS, its thickness can be followed successively by 6000A, 3000A and 2000A, to be formed
Sealer；Gold-tinted defines opening area, for example, by RIE etching mode, etches to open source metal electrode area
Domain, drain metal electrode region and gate metal electrode region, interconnect and test for device etc., wherein gate metal is electric
Polar region domain is brought out Mesa platforms.As shown in figure 9, illustrating the shape after PAD perforates, wherein Gate PAD is brought out
Mesa, therefore this section can not see Gate PAD perforate, Source PAD and Drain PAD perforate then clearly exist
It is demonstrated out on this section.
By above steps, one completely the high withstand voltage AlGaN/GaN MIS-HEMT containing grid field plate complete,
Multilayer wiring can be carried out as needed below.As can be seen that it merely add a field plate metal in the manufacturing process of whole device
The step of deposition and etching, processing step is simple, and cost is low, is the good technical scheme for solving the pressure-resistant problem of device.Separately
Outside, the technique and condition that this patent uses are that Si CMOS technologies are compatible, workable, have coordinated device well
Contradiction between energy and process complexity.
The process of improvement MIS-HEMT voltage endurances proposed by the present invention, by adding between Gate and Drain
Enter Metal field plate (Field Plate), change Electric Field Distribution in raceway groove, reduce the peak value electric field between Gate and Drain, from
And reaching improves and is lifted the pressure-resistant purpose of MIS-HEMT devices.Only needed in device fabrication processes on original Process ba- sis
Increasing step field plate metal deposition and etching technics can realize.The design of special construction, technique platform compatibility are not needed
Height, it is particularly suitable for MIS-HEMT volume production exploitation.Meanwhile the MIS-HEMT based on this structure can be by adjusting the chi of field plate
Pressure-resistant effect that is very little, being optimal device, without the size of horizontal expansion device, be advantageous to answering for device High Density Integration
With.
The invention also discloses a kind of MIS-HEMT, and it can pass through the process disclosed in as above any embodiment
Manufacture obtains.
Fig. 9 and Figure 10 are refer to, a kind of GaN MIS-HEMT disclosed by the invention, there can be following structure.Fig. 9 is shown
MIS-HEMT longitudinal profile structure.GaN and AlGaN film layers are grown in by way of MOCVD on 6 inches of Si substrates.
GaN cushions, AlGaN barrier layers and GaN cap structure are included in GaN HEMT devices.2-DEG thin layers are formed at AlGaN/
GaN interface, in GaN film layers；GaN cap is used for passivating material surface, can significantly inhibit current collapse effect simultaneously
Reduce surface leakage；Si3N4Film layer also functions to passivation, is mainly used to eliminate the surface state of material, improves the stabilization of device
Property and reliability.The presence of field plate has been obviously improved the pressure-resistant performance of device；And the preparation of field plate only needs to increase on original base
A single metal is added to deposit and etch, process compatible type is good, simple and easy, is especially suitable for the exploitation of enterprise's batch production technique；Together
When, lateral device dimensions need not increase, and greatly save the area occupied of device, meet very much high density, miniaturization integrates
The growth requirement of circuit.Figure 10 is the top view of MIS-HEMT devices, it can be seen that the shape of device and PAD layouts, lead to
Cross and draw Gate PAD outside Mesa platforms, grid VIA perforates is not influenceed by existing for Field Plate.
Use above specific case is illustrated to the present invention, is only intended to help and is understood the present invention, not limiting
The system present invention.For those skilled in the art, according to the thought of the present invention, some letters can also be made
It is single to deduce, deform or replace.
Claims (8)
1. a kind of process of improvement MIS-HEMT voltage endurances, its feature exist, comprised the following steps：
The wafer completed to cleaning, deposit Si3N4Dielectric layer；
Prepare gate window；
Deposit gate dielectric layer and gate metal；
Prepare source window and drain electrode window；
Deposit ohmic contacting metal, and define source metal electrode region, drain metal electrode region and gate metal electrode
Region；
Field plate spacer medium layer is prepared in device surface；
Field plate is prepared in field plate spacer medium layer surface；
Sealer is prepared, and perforate is carried out to the protective layer, to open source metal electrode region, drain metal electrode area
Domain and gate metal electrode region.
2. as claimed in claim 1 improve MIS-HEMT voltage endurances process, it is characterised in that it is described field plate every
Field plate is prepared from dielectric layer surface, including：
In field plate spacer medium layer surface deposited metal, Metal field plate is formed, the metal is Al；
The Metal field plate is etched by gold-tinted, to form default shape, wherein the default shape includes Metal field plate
Extend to the size in drain metal electrode region.
3. improve the process of MIS-HEMT voltage endurances as claimed in claim 1, it is characterised in that described to prepare grid
Window, including：
Define area of grid；
Etch away whole Si in the area of grid being defined3N4Dielectric layer, whole GaN caps and part AlGaN potential barrier, with
Form gate window.
4. improve the process of MIS-HEMT voltage endurances as claimed in claim 1, it is characterised in that the deposition grid are situated between
Matter layer and gate metal, including：
Deposit Si3N4, to form gate dielectric layer；
Depositing TiN, to form gate metal.
5. improve the process of MIS-HEMT voltage endurances as claimed in claim 1, it is characterised in that described to prepare source electrode
Window and drain electrode window, including：
Source region and drain region are defined respectively；
Etch away the whole gate metals being defined in source region and drain region, whole gate dielectric layers and whole Si3N4Medium
Layer, etching stopping is on the surface of GaN cap.
6. improve the process of MIS-HEMT voltage endurances as claimed in claim 1, it is characterised in that described in device table
Face prepares field plate spacer medium layer, including：Si is deposited in device surface3N4, as isolating for field plate and metal electrode region.
7. improve the process of MIS-HEMT voltage endurances as claimed in claim 1, it is characterised in that the preparation surface
Protective layer, and perforate is carried out to the protective layer, including：
It is sequentially depositing TEOS, Si3N4And TEOS, to form sealer；
Opening area is defined, source metal electrode region, drain metal electrode region and gate metal electricity are opened by etching
Polar region domain, wherein gate metal electrode region are brought out Mesa platforms.
8. a kind of MIS-HEMT, it manufactures to obtain by process as claimed in any of claims 1 to 7 in one of claims.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108987277A (en) * | 2018-06-04 | 2018-12-11 | 北京大学深圳研究生院 | A kind of enhancement type high electron mobility transistor and preparation method thereof |
| CN109103249A (en) * | 2018-04-04 | 2018-12-28 | 北京大学 | A kind of high current GaN high electron mobility transistor optimizing plane figure and structure |
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| US9024324B2 (en) * | 2012-09-05 | 2015-05-05 | Freescale Semiconductor, Inc. | GaN dual field plate device with single field plate metal |
| CN105244377A (en) * | 2015-10-29 | 2016-01-13 | 杭州士兰微电子股份有限公司 | Silicon substrate based HEMT device and manufacturing method thereof |
| CN106531807A (en) * | 2015-09-14 | 2017-03-22 | 株式会社东芝 | Semiconductor device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9024324B2 (en) * | 2012-09-05 | 2015-05-05 | Freescale Semiconductor, Inc. | GaN dual field plate device with single field plate metal |
| CN106531807A (en) * | 2015-09-14 | 2017-03-22 | 株式会社东芝 | Semiconductor device |
| CN105244377A (en) * | 2015-10-29 | 2016-01-13 | 杭州士兰微电子股份有限公司 | Silicon substrate based HEMT device and manufacturing method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109103249A (en) * | 2018-04-04 | 2018-12-28 | 北京大学 | A kind of high current GaN high electron mobility transistor optimizing plane figure and structure |
| CN108987277A (en) * | 2018-06-04 | 2018-12-11 | 北京大学深圳研究生院 | A kind of enhancement type high electron mobility transistor and preparation method thereof |
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