CN115547990A - Anti-irradiation gallium nitride based field effect transistor and preparation method thereof - Google Patents
Anti-irradiation gallium nitride based field effect transistor and preparation method thereof Download PDFInfo
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 43
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 42
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 238000002353 field-effect transistor method Methods 0.000 title description 2
- 238000002161 passivation Methods 0.000 claims abstract description 217
- 239000004065 semiconductor Substances 0.000 claims abstract description 59
- 230000005855 radiation Effects 0.000 claims abstract description 36
- 230000005669 field effect Effects 0.000 claims abstract description 32
- 239000000463 material Substances 0.000 claims description 76
- 229910052751 metal Inorganic materials 0.000 claims description 27
- 239000002184 metal Substances 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 26
- 238000000151 deposition Methods 0.000 claims description 17
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 6
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims description 5
- 238000000231 atomic layer deposition Methods 0.000 claims description 5
- 229910052758 niobium Inorganic materials 0.000 claims description 5
- 239000010955 niobium Substances 0.000 claims description 5
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 claims description 5
- 238000005240 physical vapour deposition Methods 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 239000002245 particle Substances 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 263
- 238000010586 diagram Methods 0.000 description 11
- 239000000758 substrate Substances 0.000 description 11
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 10
- 239000002131 composite material Substances 0.000 description 10
- 239000010936 titanium Substances 0.000 description 10
- 229910052719 titanium Inorganic materials 0.000 description 10
- 230000000873 masking effect Effects 0.000 description 9
- 229910052782 aluminium Inorganic materials 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- 230000003471 anti-radiation Effects 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
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- 238000005530 etching Methods 0.000 description 6
- 230000008020 evaporation Effects 0.000 description 5
- 238000001704 evaporation Methods 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 230000001276 controlling effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
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- 230000005533 two-dimensional electron gas Effects 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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Abstract
The present disclosure provides an anti-irradiation gallium nitride based field effect transistor and a preparation method thereof. The anti-irradiation gallium nitride-based field effect transistor comprises: the semiconductor device comprises a semiconductor layer structure with a channel, a source electrode, a drain electrode and a grid electrode which are arranged on the semiconductor layer structure, a passivation base layer which is arranged on the semiconductor layer structure and is positioned between the source electrode and the drain electrode, a passivation shielding layer which is positioned on the passivation base layer and the grid electrode, a first grid field plate which is arranged in the passivation shielding layer and is positioned on the grid electrode, and a second grid field plate which is arranged in the passivation shielding layer and is arranged at an interval with the first grid field plate. Through further setting up passivation shielding layer on the passivation basic unit and setting up first gate field board and the second gate field board that is located the grid in passivation shielding layer, can block the impact of radiation particle to semiconductor layer structure, effectively improve the radiation resistance ability of device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an anti-irradiation gallium nitride based field effect transistor and a preparation method thereof.
Background
Third-generation semiconductors such as gallium nitride have excellent physical properties such as a wide band gap, high breakdown field strength, high electron mobility, and high stability, and are attracting attention in power electronic applications.
The conventional commercial gallium nitride-based power device has low radiation resistance and cannot meet the requirements in environments with high radiation, such as aerospace and the like, so that the application range of the gallium nitride-based power device is limited.
Disclosure of Invention
Based on this, in order to improve the radiation resistance of the field effect transistor, it is necessary to provide a radiation-resistant gallium nitride-based field effect transistor.
According to some embodiments of the present disclosure, there is provided an irradiation-resistant gallium nitride-based field effect transistor, including:
a semiconductor layer structure having a channel therein;
a source, a drain, and a gate disposed on the semiconductor layer structure;
a passivation base layer disposed on the semiconductor layer structure and between the source and the drain;
a passivation shielding layer located on the passivation base layer and the gate electrode;
the first grid field plate is arranged in the passivation shielding layer and positioned on the grid electrode;
the second gate field plate is arranged in the passivation shielding layer and positioned on the first gate field plate, and the first gate field plate and the second gate field plate are arranged at intervals.
In one embodiment, the passivation base layer includes a first sub-passivation layer and a second sub-passivation layer which are made of different materials, the first sub-passivation layer is stacked on the semiconductor layer structure, the second sub-passivation layer is stacked on the first sub-passivation layer, the thickness of the first sub-passivation layer is 2nm to 20nm, and the thickness of the second sub-passivation layer is 20nm to 100nm.
In one embodiment, the material of the first sub-passivation layer comprises aluminum oxide, and the material of the second sub-passivation layer comprises aluminum nitride.
In one embodiment, the material of the passivation shield layer comprises silicon nitride.
In one embodiment, the first gate field plate shields the gate electrode, and the first gate field plate has a larger radial extent than the gate electrode.
In one embodiment, the second gate field plate shields the first gate field plate, and the second gate field plate has a larger extent in the radial direction than the first gate field plate.
In one embodiment, the thickness of the first grid field plate is 50 nm-200 nm; and/or
The thickness of the second grid field plate is 50 nm-200 nm.
In one embodiment, the source substrate further comprises a source field plate disposed on the source electrode, the source field plate having an extension portion that extends above the passivation shield layer and shields the second gate field plate.
In one embodiment, the device further comprises a radiation-resistant layer arranged above the passivation shielding layer.
In one embodiment, the radiation-resistant layer includes a plurality of metal layers stacked together, and the plurality of metal layers includes a zirconium metal layer and a niobium metal layer.
According to still other embodiments of the present disclosure, a method for manufacturing an anti-radiation gallium nitride-based field effect transistor includes the following steps:
providing a semiconductor layer structure with a channel;
forming a source electrode and a drain electrode on the semiconductor layer structure;
preparing a passivation base layer between the source electrode and the drain electrode, and depositing a passivation shielding material on the passivation base layer to prepare a passivation shielding layer;
preparing a grid electrode on the semiconductor layer structure, wherein the grid electrode is shielded by the passivation shielding layer; and
and preparing a first gate field plate and a second gate field plate in the passivation shielding layer above the grid, wherein the first gate field plate and the second gate field plate are spaced by the passivation shielding material.
In one embodiment, the passivation base layer includes a first sub-passivation layer and a second sub-passivation layer, which are made of different materials, the first sub-passivation layer is stacked on the semiconductor layer structure, the second sub-passivation layer is stacked on the first sub-passivation layer, a method for preparing the first sub-passivation layer is an atomic layer deposition method, a method for preparing the second sub-passivation layer is a physical vapor deposition method, and a method for depositing the passivation shielding material is a chemical vapor deposition method.
The irradiation-resistant gallium nitride-based field effect transistor in at least one embodiment includes a passivation base layer, a passivation shielding layer, and a first gate field plate and a second gate field plate disposed on the passivation shielding layer. Through further setting up passivation shielding layer on the passivation basic unit and setting up first gate field board and the second gate field board that is located the grid in passivation shielding layer, can block the impact of radiation particle to semiconductor layer structure, effectively improve the radiation resistance ability of device.
In addition, the passivation shielding layer additionally arranged on the grid electrode in the irradiation enhanced field effect transistor can effectively improve the passivation effect of the field effect transistor, and further reduce current collapse. The first grid field plate and the second grid field plate which are arranged in the passivation layer and spaced from each other can also effectively regulate and control a peak electric field, and the breakdown voltage of the device is improved.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical solutions of the present invention more clearly understood and to implement them in accordance with the contents of the description, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain drawings of other embodiments based on these drawings without any creative effort.
Fig. 1 shows a schematic structural diagram of an irradiation-resistant gallium nitride-based field effect transistor in an embodiment of the present disclosure;
fig. 2 is a schematic diagram illustrating a process for manufacturing an anti-radiation gan-based fet according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of the device structure of step S1 in FIG. 2;
FIG. 4 is a schematic diagram of the device structure of step S2 in FIG. 2;
FIG. 5 is a schematic diagram of the device structure of step S3 in FIG. 2;
FIG. 6 shows a schematic diagram of the device structure of step S4 in FIG. 2;
FIG. 7 is a schematic diagram of the device structure of step S5 in FIG. 2;
FIG. 8 is a schematic diagram of the device structure of step S6 in FIG. 2;
fig. 9 shows a schematic diagram of the device structure of step S7 in fig. 2;
FIG. 10 is a schematic diagram of the device structure of step S8 in FIG. 2;
wherein the reference symbols and their meanings are as follows:
110. a semiconductor layer structure; 111. a substrate; 112. a channel layer; 113. a barrier layer; 114. a gate dielectric layer; 121. a source electrode; 122. a drain electrode; 123. a gate electrode; 130. passivating the base layer; 131. a first sub-passivation layer; 132. a second sub-passivation layer; 140. passivating the shielding layer; 150. a first gate field plate; 160. a second gate field plate; 170. a source field plate; 171. an extension portion; 180. and a radiation-resistant layer.
Detailed Description
In order that the invention may be more fully understood, reference will now be made to the following description. Preferred embodiments of the present invention are presented herein. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. As used herein, "plurality" includes two and more than two items. As used herein, "above a certain number" should be understood to mean a certain number and a range greater than a certain number.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
According to one embodiment of the present disclosure, an irradiation-resistant gallium nitride-based field effect transistor includes:
a semiconductor layer structure having a channel therein;
a source, a drain, and a gate disposed on the semiconductor layer structure;
a passivation base layer disposed on the semiconductor layer structure and between the source and the drain;
a passivation shielding layer located on the passivation base layer and the gate electrode;
the first grid field plate is arranged in the passivation shielding layer and positioned on the grid electrode;
the second grid field plate is arranged in the passivation shielding layer and positioned on the first grid field plate, and the first grid field plate and the second grid field plate are arranged at intervals.
In order to facilitate understanding of the anti-radiation gallium nitride based fet in this embodiment, reference is made to fig. 1, which is a schematic structural diagram of an anti-radiation gallium nitride based fet. Comprising a semiconductor layer structure 110, a source electrode 121, a drain electrode 122, a gate electrode 123, a passivation base layer 130, a passivation shield layer 140, a first gate field plate 150 and a second gate field plate 160. The source electrode 121, the drain electrode 122 and the gate electrode 123 are disposed on the semiconductor layer structure 110. The passivation base layer 130 is disposed between the source electrode 121 and the drain electrode 122, and the passivation shielding layer 140 is disposed on the passivation base layer 130 and the gate electrode 123. The first gate field plate 150 and the second gate field plate 160 are located in the passivation shield layer 140 with the first gate field plate 150 and the second gate field plate 160 spaced apart.
In some specific examples of this embodiment, the semiconductor layer structure 110 is a gallium nitride-based layer structure. The gallium nitride-based layer structure includes a substrate 111, and a channel layer 112, a barrier layer 113, and a gate dielectric layer 114 sequentially stacked on the substrate 111. At this time, a channel in the gallium nitride based layer structure is formed between the channel layer 112 and the barrier layer 113. The gate dielectric layer 114 serves to insulate the spacer barrier layer 113 from the gate electrode 123. The gallium nitride-based field effect transistor is formed by using a gallium nitride material as a semiconductor substrate. The gallium nitride based layer structure may be a functional layer formed by epitaxial growth on a substrate 111.
It is understood that the semiconductor layer structure 110 constitutes the main functional structure of the anti-radiation gallium nitride-based field effect transistor in this embodiment, and the structure thereof corresponds to a specific field effect transistor type. In some specific examples, the radiation-resistant gan-based fets are High Electron Mobility Transistors (HEMTs).
Alternatively, the substrate 111 in the semiconductor layer structure 110 may be sapphire, gallium nitride, silicon, or silicon carbide.
It is understood that the channel in the semiconductor layer structure 110 is used for connecting the source electrode 121 and the drain electrode 122, and the gate electrode 123 is used for controlling the on and off of the channel. The semiconductor layer structure 110 may refer to a field effect transistor structure that is generally used in the conventional art. For example, the channel may be a two-dimensional electron gas formed between heterojunctions.
In some specific examples of this embodiment, the material of the source electrode 121 and the drain electrode 122 may be metal. Alternatively, the metal may be an elemental metal or an alloy. For example, the material of the source electrode 121 and the drain electrode 122 includes one or more of titanium, aluminum, nickel, and gold.
In some specific examples of this embodiment, the material in the passivation base layer 130 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, and aluminum oxynitride.
In some specific examples of this embodiment, the passivation base layer 130 includes a first sub-passivation layer 131 and a second sub-passivation layer 132 having different materials, the first sub-passivation layer 131 is stacked on the semiconductor layer structure 110, and the second sub-passivation layer 132 is stacked on the first sub-passivation layer 131. By providing the first and second sub-passivation layers 131 and 132 disposed in a stacked manner, the function of the passivation base layer 130 can be optimized.
In some specific examples of this embodiment, the thickness of the first sub-passivation layer 131 is 2nm to 20nm.
In some specific examples of this embodiment, the thickness of the second sub-passivation layer 132 is 20nm to 100nm.
In some specific examples of this embodiment, the material of the first sub-passivation layer 131 includes aluminum oxide, and the material of the second sub-passivation layer 132 includes aluminum nitride. The alumina having a thickness of 2nm to 20nm may be formed by an atomic layer deposition method, and the aluminum nitride having a thickness of 20nm to 100nm may be formed by a physical vapor deposition method.
In some specific examples of this embodiment, the gate 123 is thicker than the passivation base layer 130. The portion of the gate 123 near the top end protrudes from the passivation base layer 130, and a passivation shielding material is disposed around the portion of the gate 123. With this arrangement, the first gate field plate 150 and the passivation base layer 130 are separated by the passivation material, so as to improve the ability of the first gate field plate 150 to control the peak electric field.
In some specific examples of this embodiment, the material of the passivation shield layer 140 includes silicon nitride. The silicon nitride may be formed by chemical vapor deposition.
In some specific examples of this embodiment, the passivation masking layer 140 has a thickness of 2 μm to 10 μm.
In some specific examples of this embodiment, the first gate field plate 150 shields the gate electrode 123, and the extent of the first gate field plate 150 in the radial direction is larger than the extent of the gate electrode 123 in the radial direction. The first gate field plate 150 has a portion protruding from the gate electrode 123 in the radial direction, so as to perform a more effective function of regulating the peak electric field.
In some specific examples of this embodiment, the material of the first gate field plate 150 is a metal. The first gate field plate 150 can be a composite layer including multiple stacked metal layers, e.g., the first gate field plate 150 is a titanium/aluminum/titanium composite layer.
In some specific examples of this embodiment, the first gate field plate 150 has a thickness of 50nm to 200nm.
In some specific examples of this embodiment, the second gate field plate 160 shields the first gate field plate 150, and the extent of the second gate field plate 160 in the radial direction is larger than the extent of the first gate field plate 150 in the radial direction. The second gate field plate 160 has a portion protruding from the first gate field plate 150 in the radial direction to further enhance the ability to manipulate the peak electric field.
In some specific examples of this embodiment, the thickness of the second gate field plate 160 is between 50nm and 200nm.
In some specific examples of this embodiment, a source field plate 170 is further included and disposed on the source electrode 121 to further optimize the device performance of the fet.
In some specific examples of this embodiment, further comprising an extension 171, the extension 171 extends above the passivation shielding layer 140 and shields the second gate field plate 160. The extension portion 171 is arranged when the source field plate 170 is formed, so that the capability of regulating and controlling a peak electric field can be further improved, and meanwhile, the anti-irradiation capability of the device can be improved.
The first gate field plate 150 and the second gate field plate 160 can improve the radiation resistance of the device inside the passivation shielding layer 140. In some specific examples of the embodiment, the passivation shielding layer 140 further includes a radiation-resistant layer 180 disposed above the passivation shielding layer 140, and the radiation-resistant layer 180 can further improve the radiation resistance of the device from the outside of the passivation shielding layer 140.
In some specific examples of this embodiment, the radiation-resistant layer 180 includes a plurality of metal layers including a zirconium metal layer and a niobium metal layer, which are stacked.
The irradiation-resistant gan-based fet in at least one of the above embodiments includes the passivation base layer 130, the passivation shielding layer 140, and the first gate field plate 150 and the second gate field plate 160 disposed on the passivation shielding layer 140. By further providing the passivation shielding layer 140 on the passivation base layer 130 and providing the first gate field plate 150 and the second gate field plate 160 on the gate 123 in the passivation shielding layer 140, the impact of radiation particles on the semiconductor layer structure 110 can be blocked, and the radiation resistance of the device can be effectively improved.
In addition, the passivation shielding layer 140 additionally arranged on the gate 123 in the radiation enhanced field effect transistor can also effectively improve the passivation effect of the field effect transistor, and further reduce current collapse. The first gate field plate 150 and the second gate field plate 160 arranged in the passivation layer at intervals can also effectively regulate and control a peak electric field, and the breakdown voltage of the device is improved.
According to another embodiment of the present disclosure, a method for manufacturing an anti-radiation gallium nitride-based field effect transistor includes the following steps:
providing a semiconductor layer structure 110 having a channel;
forming a source electrode 121 and a drain electrode 122 on the semiconductor layer structure 110;
preparing a passivation base layer 130 between the source electrode 121 and the drain electrode 122, and depositing a passivation shielding material shielding the passivation base layer 130 on the passivation base layer 130 to prepare a passivation shielding layer 140;
forming a gate electrode 123 on the semiconductor layer structure 110, wherein the passivation shielding layer 140 also shields the gate electrode 123; and
a first gate field plate 150 and a second gate field plate 160 are formed in the passivation shield layer 140 over the gate 123, with a passivation shield material spacing between the first gate field plate 150 and the second gate field plate 160.
In order to facilitate understanding of the method for manufacturing the radiation-resistant gallium nitride-based field effect transistor according to this embodiment, reference is made to fig. 2, which may specifically include the following steps S1 to S8.
Referring to fig. 3, step S1 provides a semiconductor layer structure 110 having a channel.
It is understood that the channel in the semiconductor layer structure 110 is used for communicating the source electrode 121 and the drain electrode 122 which are formed subsequently, and the gate electrode 123 which is formed subsequently is used for controlling the on and off of the channel. The semiconductor layer structure 110 may refer to a field effect transistor structure that is generally used in the conventional art.
In some specific examples of this embodiment, the semiconductor layer structure 110 is a gallium nitride-based layer structure. It is understood that the fet is a gallium nitride based fet in this case. The gallium nitride based layer structure may include a substrate 111, and a channel layer 112, a barrier layer 113, and a gate dielectric layer 114 sequentially stacked on the substrate 111. At this time, a channel in the gallium nitride based layer structure is formed between the channel layer 112 and the barrier layer 113. The gate dielectric layer 114 serves to insulate the spacer barrier layer 113 from the subsequently formed gate electrode 123.
Alternatively, the substrate 111 in the semiconductor layer structure 110 may be sapphire, gallium nitride, silicon, or silicon carbide.
It is understood that the semiconductor layer structure 110 has a predetermined source electrode 121 region, a predetermined drain electrode 122 region and a predetermined gate electrode 123 region, which are respectively used for forming the source electrode 121, the drain electrode 122 and the gate electrode 123 in the subsequent manufacturing process.
It is understood that the semiconductor layer structure 110 may be prepared by sequentially depositing corresponding material layers on the substrate 111. The semiconductor layer structure 110 may be provided by preparing or pre-fabricating the semiconductor layer structure 110.
Referring to fig. 4, in step S2, a source electrode 121 and a drain electrode 122 are formed on the semiconductor layer structure 110.
It is understood that the source electrode 121 and the drain electrode 122 are respectively formed at both sides of the channel in the semiconductor layer structure 110.
In some specific examples of this embodiment, the material of the source electrode 121 and the drain electrode 122 may be metal. Alternatively, the metal may be an elemental metal or an alloy. For example, the material of the source electrode 121 and the drain electrode 122 includes one or more of titanium, aluminum, nickel, and gold.
In some specific examples of the embodiment, the step of forming the source electrode 121 and the drain electrode 122 on the semiconductor layer structure 110 includes: a mask is formed and exposed to light and developed to expose the source and drain electrode 121 and 122 regions on the semiconductor layer structure 110, and the material of the source and drain electrodes 121 and 122 is deposited on the source and drain electrode 121 and 122 regions.
In some specific examples of this embodiment, the material of the source electrode 121 and the drain electrode 122 includes a metal. The step of depositing the material of the source electrode 121 and the drain electrode 122 on the source electrode 121 region and the drain electrode 122 region includes: a metal material is deposited on the source 121 and drain 122 regions and annealed to form ohmic contacts.
In some specific examples of this embodiment, the material of the source electrode 121 and the drain electrode 122 is deposited on the source electrode 121 region and the drain electrode 122 region by evaporation.
Referring to fig. 5, in step S3, a passivation base layer 130 is formed between the source electrode 121 and the drain electrode 122.
The passivation base layer 130 is disposed between the source electrode 121 and the drain electrode 122, and the passivation base layer 130 is a structure commonly found in semiconductor devices and used for reducing current collapse.
In some specific examples of this embodiment, the material in the passivation base layer 130 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, and aluminum oxynitride.
In some specific examples of this embodiment, the passivation base layer 130 includes a first sub-passivation layer 131 and a second sub-passivation layer 132, the first sub-passivation layer 131 is stacked on the semiconductor layer structure 110, and the second sub-passivation layer 132 is stacked on the first sub-passivation layer 131.
On the other hand, the effect of the passivation base layer 130 can be further optimized through improvement of the manufacturing process, so that the first sub-passivation layer 131 and the second sub-passivation layer 132 arranged in a stacked manner have better performance and higher thickness. Alternatively, the first sub-passivation layer 131 may be formed by an atomic layer deposition method, and the second sub-passivation layer 132 may be formed by a physical vapor deposition method. The first sub-passivation layer 131 formed by the atomic layer deposition method has a high film quality, but can be prepared with a limited thickness, and the second sub-passivation layer 132 can be prepared to have a thicker thickness by the physical vapor deposition method, so as to increase the thickness of the passivation base layer 130. Therefore, by combining two deposition methods to separately prepare the first sub-passivation layer 131 and the second sub-passivation layer 132, the performance of the device can be significantly improved.
In some specific examples of this embodiment, the material of the first sub-passivation layer 131 may include aluminum oxide, and the material of the second sub-passivation layer 132 may include aluminum nitride.
In some specific examples of this embodiment, the second sub-passivation layer 132 has a thickness greater than that of the first sub-passivation layer 131. Optionally, the thickness of the first sub-passivation layer 131 is 2nm to 20nm, and the thickness of the second sub-passivation layer 132 is 20nm to 100nm.
Referring to fig. 6, in step S4, a passivation mask layer 140 is formed on the passivation base layer 130.
The passivation shielding layer 140 is made of a passivation shielding material, and the passivation shielding layer 140 may be formed by depositing the passivation shielding material on the passivation base layer 130 when the passivation shielding layer 140 is prepared.
In some specific examples of this embodiment, the passivation masking material is deposited in a manner selected from chemical vapor deposition methods by which thicker thicknesses of the passivation masking material can be produced.
In some specific examples of this embodiment, the passivation masking material comprises silicon nitride.
Optionally, the thickness of the passivation shielding material deposited in step S4 is 100nm to 500nm.
Referring to fig. 7, in step S5, a gate electrode 123 is formed on the semiconductor layer structure 110.
The passivation shielding layer 140 also shields the gate electrode 123. Optionally, the gate 123 is embedded in the passivation base layer 130 and the passivation shield layer 140.
In this embodiment, the gate electrode 123 may be prepared after depositing the passivation masking material. Optionally, the step of preparing the gate electrode 123 on the semiconductor layer structure 110 includes: the passivation shielding material and the passivation base layer 130 on the region of the gate electrode 123 of the semiconductor layer structure 110 are etched to form an etch hole exposing the region of the gate electrode 123, and the gate electrode 123 is prepared in the etch hole on the region of the gate electrode 123. Alternatively, the manner of etching the passivation masking material and the passivation base layer 130 is dry etching.
In some specific examples of this embodiment, the step of preparing the gate electrode 123 on the gate electrode 123 region comprises: gate 123 material is deposited in the region of gate 123. The gate electrode 123 material may be metal, and the deposition of the gate electrode 123 material may be evaporation.
In some specific examples of this embodiment, the control fabricated gate 123 is thicker than the thickness of the passivation base layer 130. The gate 123 is thicker than the passivation base layer 130, so that the portion of the gate 123 near the top end protrudes out of the passivation base layer 130, and the periphery of the portion of the gate 123 is provided with a passivation shielding material.
In step S6, a first gate field plate 150 and a second gate field plate 160 are respectively formed on the passivation shielding layer 140 above the gate electrode 123.
Wherein the first gate field plate 150 and the second gate field plate 160 are spaced apart, and the first gate field plate 150 and the second gate field plate 160 are spaced apart by a passivation material.
In this embodiment, step S6 further comprises step S6.1 and step S6.2, as follows.
Referring to fig. 8, in step S6.1, a first gate field plate 150 is prepared in the passivation shielding layer 140 over the gate 123.
In some embodiments of this embodiment, the step of preparing the first gate field plate 150 in the passivation shield layer 140 over the gate 123 includes: the passivation shield layer 140 is etched to form a first field plate region over the gate 123 that is wider than the area of the gate 123, in which the first field plate 150 is fabricated. It is understood that the first gate field plate 150 formed at this time has a larger extent in the radial direction than the gate electrode 123.
In some specific examples of this embodiment, the first gate field plate 150 is disposed in contact with the gate electrode 123. At this time, the etching hole above the gate 123 may be widened directly by etching to form a first field plate region having a wider area than the gate 123 region.
In other specific examples of this embodiment, the first gate field plate 150 is disposed in contact with the gate 123 or spaced apart from the gate 123 with a passivation shielding material. At this time, a passivation shielding material may also be deposited in the etching hole formed by etching the passivation shielding layer 140, and then the passivation shielding material is etched back along the first field plate region to form a first field plate region wider than the gate 123 region. Alternatively, the thickness of the passivation masking material deposited in this step may be between 100nm and 500nm.
In some specific examples of this embodiment, the material of the first gate field plate 150 is a metal. The first gate field plate 150 can be a composite layer including multiple stacked metal layers, e.g., the first gate field plate 150 is a titanium/aluminum/titanium composite layer. Alternatively, the first gate field plate 150 is prepared by depositing the material of the first gate field plate 150 in the first field plate region. The material of the first gate field plate 150 is deposited by evaporation.
In some specific examples of this embodiment, the thickness of the first gate field plate 150 is between 50nm and 200nm.
Referring to fig. 9, in step S6.2, a second gate field plate 160 is formed in the passivation shield layer 140 over the gate 123.
In some embodiments of this embodiment, the step of preparing the second gate field plate 160 in the passivation shield layer 140 over the gate 123 includes: a passivation shield material is deposited on the first gate field plate 150 and the passivation shield material is etched to form a second field plate region over the first gate field plate 150 that is wider than the first field plate region, in which the second gate field plate 160 is fabricated. It is understood that the second gate field plate 160 is formed at this time to have a larger extent in the radial direction than the first gate field plate 150, and the second gate field plate 160 has a portion protruding from the first gate field plate 150 in the radial direction.
Optionally, a passivation shielding material is deposited in the etch holes on the first gate field plate 150 and then etched back along the second field plate region to form a second field plate region wider than the first field plate region. Alternatively, the thickness of the passivation masking material deposited in this step may be between 100nm and 500nm.
In some specific examples of this embodiment, the material of the second gate field plate 160 is a metal. The second gate field plate 160 can be a composite layer including multiple stacked metal layers, for example, the second gate field plate 160 is a titanium/aluminum/titanium composite layer. Alternatively, the second gate field plate 160 is prepared by depositing the material of the second gate field plate 160 in the second field plate region. The material of the second gate field plate 160 is deposited by evaporation.
In some specific examples of this embodiment, the thickness of the second gate field plate 160 is between 50nm and 200nm.
By steps S6.1 and S6.2, the first gate field plate 150 and the second gate field plate 160 spaced with a passivating shielding material can be completed.
In some specific examples of this embodiment, after forming the second gate field plate 160, there is further included the step of depositing a passivation masking material on the second gate field plate 160 to mask the second gate field plate 160.
It will be appreciated that the above fabrication process involves multiple etching of the passivation mask layer 140 and depositing the passivation mask material again, and the final passivation mask material forms the passivation mask layer 140 in the fet. The total thickness of the passivation shielding layer 140 may be 2 μm to 10 μm.
Optionally, after preparing the second gate field plate 160, a step of forming a source field plate 170 may also be included.
Referring to fig. 10, in step S7, a source field plate 170 is prepared on the source electrode 121.
In some specific examples of this embodiment, the passivation shielding layer 140 also shields the source electrode 121, and in the step of forming the source field plate 170, a portion of the passivation shielding layer 140 on the source electrode 121 is etched away, and then the source field plate 170 is formed on the source electrode 121.
In some specific examples of this embodiment, the material of the source field plate 170 is a metal. The source field plate 170 may be a composite layer including multiple stacked metal layers, for example, the source field plate 170 is a titanium/aluminum/titanium composite layer. Alternatively, the source field plate 170 is prepared by depositing the material of the source field plate 170 on the source field plate 170. The material of the source field plate 170 is deposited by evaporation.
In some specific examples of this embodiment, in preparing the source field plate 170, a step of depositing the material of the source field plate 170 together over the passivation shielding layer 140 to form an extension layer of the source field plate 170 shielding the second gate field plate 160 is further included. Optionally, the extension layer of the source field plate 170 has a wider extent than the second gate field plate 160, and the outer edge of the extension layer of the source field plate 170 protrudes beyond the outer edge of the second gate field plate 160.
Optionally, after the source field plate 170 is prepared, a step of forming the radiation-resistant layer 180 on the passivation shielding layer 140 is further included.
Step S8, a radiation-resistant layer 180 is formed on the passivation layer 140.
In some specific examples of this embodiment, the material of the radiation-resistant layer 180 includes a metal. Alternatively, the radiation-resistant layer 180 may be a composite layer including a plurality of metal layers stacked, for example, the radiation-resistant layer 180 is a zirconium/niobium composite layer. Optionally, in the radiation-resistant layer 180, the thickness of the zirconium metal layer is 50nm to 200nm, and the thickness of the niobium metal layer is 50nm to 200nm.
Through steps S1 to S8, the preparation of the anti-radiation gallium nitride based field effect transistor as in fig. 1 can be completed.
Another embodiment of the present disclosure provides an anti-irradiation gallium nitride based field effect transistor, which is prepared by the preparation method of the anti-irradiation gallium nitride based field effect transistor in any one of the above embodiments.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above examples only show some embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. An anti-irradiation gallium nitride based field effect transistor, comprising:
a semiconductor layer structure having a channel therein;
a source, a drain, and a gate disposed on the semiconductor layer structure;
a passivation base layer disposed on the semiconductor layer structure and between the source and the drain;
a passivation shielding layer on the passivation base layer and the gate electrode;
the first grid field plate is arranged in the passivation shielding layer and positioned on the grid electrode;
the second grid field plate is arranged in the passivation shielding layer and positioned on the first grid field plate, and the first grid field plate and the second grid field plate are arranged at intervals.
2. The radiation-resistant gallium nitride-based field effect transistor according to claim 1, wherein the passivation base layer comprises a first sub-passivation layer and a second sub-passivation layer of different materials, the first sub-passivation layer is stacked on the semiconductor layer structure, the second sub-passivation layer is stacked on the first sub-passivation layer, the first sub-passivation layer has a thickness of 2nm to 20nm, and the second sub-passivation layer has a thickness of 20nm to 100nm.
3. The radiation resistant gallium nitride based field effect transistor of claim 2, wherein the material of the first sub-passivation layer comprises aluminum oxide and the material of the second sub-passivation layer comprises aluminum nitride; and/or the presence of a gas in the gas,
the material of the passivation shielding layer comprises silicon nitride.
4. The radiation-resistant gallium nitride-based field effect transistor according to any one of claims 1 to 3, wherein the first gate field plate shields the gate, and the first gate field plate has a larger radial extent than the gate; and/or
The second gate field plate shields the first gate field plate, and the radial range of the second gate field plate is larger than that of the first gate field plate.
5. The radiation-resistant gallium nitride-based field effect transistor according to any one of claims 1 to 3, wherein the thickness of the first gate field plate is 50nm to 200nm; and/or
The thickness of the second grid field plate is 50 nm-200 nm.
6. The radiation resistant gallium nitride based field effect transistor of any one of claims 1 to 3, further comprising a source field plate disposed on the source electrode, the source field plate having an extension portion that extends above the passivation shield layer and shields the second gate field plate.
7. The radiation-resistant gallium nitride-based field effect transistor according to any one of claims 1 to 3, further comprising a radiation-resistant layer disposed over the passivation shield layer.
8. The radiation-resistant GaN-based FET of claim 7, wherein the radiation-resistant layer comprises a plurality of metal layers arranged in a stack, the plurality of metal layers comprising a zirconium metal layer and a niobium metal layer.
9. A method for preparing an irradiation-resistant gallium nitride-based field effect transistor according to any one of claims 1 to 8, comprising the steps of:
providing a semiconductor layer structure with a channel;
forming a source electrode and a drain electrode on the semiconductor layer structure;
preparing a passivation base layer between the source electrode and the drain electrode, and depositing a passivation shielding material on the passivation base layer to prepare a passivation shielding layer;
preparing a grid electrode on the semiconductor layer structure, wherein the grid electrode is shielded by the passivation shielding layer; and
and preparing a first gate field plate and a second gate field plate in the passivation shielding layer above the grid, wherein the first gate field plate and the second gate field plate are spaced by the passivation shielding material.
10. The method according to claim 9, wherein the passivation base layer includes a first sub-passivation layer and a second sub-passivation layer of different materials, the first sub-passivation layer is stacked on the semiconductor layer structure, the second sub-passivation layer is stacked on the first sub-passivation layer, the method for preparing the first sub-passivation layer is an atomic layer deposition method, the method for preparing the second sub-passivation layer is a physical vapor deposition method, and the method for depositing the passivation shielding material is a chemical vapor deposition method.
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