CN112397577B - Semiconductor device structure and manufacturing method thereof - Google Patents
Semiconductor device structure and manufacturing method thereof Download PDFInfo
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- CN112397577B CN112397577B CN201910750969.3A CN201910750969A CN112397577B CN 112397577 B CN112397577 B CN 112397577B CN 201910750969 A CN201910750969 A CN 201910750969A CN 112397577 B CN112397577 B CN 112397577B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 77
- 239000002184 metal Substances 0.000 claims abstract description 77
- 238000000034 method Methods 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 230000007423 decrease Effects 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 230000008569 process Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 4
- 230000006978 adaptation Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The present disclosure provides a semiconductor device structure, comprising: a conductive region; a dielectric layer formed on the conductive region; the metal structure is formed on the dielectric layer; the ohmic contact structure is formed in the dielectric layer, the first surface is connected with the conductive area, the second surface is connected with the metal structure, the length of the second surface in a first direction is smaller than that of the first surface in the first direction, and the first direction is the shortest distance connecting line direction between the second surface of the ohmic contact structure and the second surface of an adjacent ohmic contact structure on the same layer. The embodiment of the disclosure can simultaneously have lower ohmic contact resistance and larger spacing between adjacent metal structures on the same layer, and effectively prevent the metal structures in the conductive areas or between the conductive areas from being shorted.
Description
Technical Field
The disclosure relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device structure and a manufacturing method thereof.
Background
As advanced manufacturing processes are advanced, transistor dimensions continue to shrink, channel lengths become shorter and corresponding ohmic contact structures (contacts) become larger and larger. In order to increase the operating current and speed of transistors, it is necessary to reduce the resistance of the ohmic contact structures, which is typically achieved by increasing the length of the ohmic contact structures in semiconductor fabrication techniques.
However, since the design rule prescribes that the size of the surface (the lower surface of the metal structure) of the metal structure, which is connected with the ohmic contact structure, must be larger than the size of the surface (the upper surface of the ohmic contact structure) of the ohmic contact structure, the increase of the length of the ohmic contact structure inevitably leads to the corresponding increase of the length of the metal structure, the difficulty of the metal interconnection process is increased, and the short circuit of the metal interconnection line in or between devices is easily caused, thus forming a new process difficulty.
It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
It is an object of the present disclosure to provide a semiconductor device structure for overcoming, at least to some extent, the problem of easy shorting of metal structures within or between conductive regions due to limitations and drawbacks of the related art.
According to a first aspect of embodiments of the present disclosure, there is provided a semiconductor device structure comprising:
A conductive region;
a dielectric layer formed on the conductive region;
The metal structure is formed on the dielectric layer;
The ohmic contact structure is formed in the dielectric layer, the first surface is connected with the conductive area, the second surface is connected with the metal structure, the length of the second surface in the first direction is smaller than that of the first surface in the first direction, and the first direction is the shortest distance connecting line direction between the second surface of the ohmic contact structure and the second surface of the adjacent ohmic contact structure on the same layer.
In one exemplary embodiment of the present disclosure, the length of the ohmic contact structure in the first direction continuously decreases or stepwise decreases from the first surface toward the second surface.
In one exemplary embodiment of the present disclosure, the conductive region is an active region of a semiconductor structure or a metal structure.
In one exemplary embodiment of the present disclosure, an ohmic contact structure includes a first portion and a second portion, the first portion being located over the second portion, a length of the first portion in a first direction being less than a length of the second portion in the first direction.
In one exemplary embodiment of the present disclosure, the first portion and/or the second portion is rectangular or trapezoidal in cross-section perpendicular to the first surface and the second surface in the first direction.
In an exemplary embodiment of the present disclosure, the material of the ohmic contact structure is the same as the material of the metal structure, or the material of the ohmic contact structure is tungsten, and the material of the metal structure is copper.
According to one aspect of the present disclosure, there is provided a method of fabricating a semiconductor device structure, comprising:
Providing a conductive region;
an ohmic contact structure positioned in the dielectric layer is manufactured on the conductive area, the first surface of the ohmic contact structure is connected with the conductive area, the second surface is horizontal to the surface of the dielectric layer, the length of the second surface in the first direction is smaller than that of the first surface in the first direction, the first direction is the shortest distance connecting line direction between the second surface of the ohmic contact structure and the second surface of the adjacent ohmic contact structure, and the distance between the second surface and the adjacent ohmic contact structure is larger than that between the first surface and the adjacent ohmic contact structure;
and manufacturing a metal structure connected with the second surface on the dielectric layer.
In one exemplary embodiment of the present disclosure, fabricating an ohmic contact structure in a dielectric layer on a conductive region includes:
Manufacturing a dielectric layer on the conductive region;
Etching a trapezoid groove in the dielectric layer, wherein the first surface of the trapezoid groove is connected with the conductive area, the second surface is horizontal to the surface of the dielectric layer, and the length of the second surface in the first direction is smaller than that of the first surface in the first direction;
Filling the trapezoid groove with a first metal.
In one exemplary embodiment of the present disclosure, fabricating an ohmic contact structure in a dielectric layer on a conductive region includes:
And sequentially stacking and manufacturing a first sub-structure to an N-th sub-structure on the conductive area, wherein the sub-structure comprises a sub-dielectric layer and a sub-ohmic contact structure formed in the sub-dielectric layer, the first surface and the second surface of the sub-ohmic contact structure are respectively horizontal to the first surface and the second surface of the sub-dielectric layer, and the length of each plane of the N-th sub-ohmic contact structure and the first surface in a first direction is larger than the length of each plane of the n+1-th sub-ohmic contact structure and the first surface in the first direction, wherein N is more than or equal to 2, N is less than or equal to 1, N.
In one exemplary embodiment of the present disclosure, n=2, fabricating the sub-structures 1-N times over the conductive region includes:
Manufacturing a first sub-dielectric layer on the conductive area;
Etching a first groove in the first sub-dielectric layer;
filling the second groove with a first metal to form a first sub-ohmic contact structure and a first sub-structure simultaneously;
manufacturing a second sub-medium layer on the first sub-structure;
etching a second groove in the second sub-medium layer, wherein the lengths of the second groove and each plane of the first surface level in the first direction are smaller than those of the first groove and each plane of the first surface level in the first direction;
the second groove is filled with the first metal to form a second sub-ohmic contact structure and a second sub-structure simultaneously.
In one exemplary embodiment of the present disclosure, each plane of the nth sub-ohmic contact structure horizontal to the first surface is rectangular or trapezoidal in cross section perpendicular to the first surface and the second surface in the first direction.
In an exemplary embodiment of the present disclosure, the first metal is the same material as the metal structure, or the first metal is tungsten and the metal structure is copper.
In one exemplary embodiment of the present disclosure, the conductive region is an active region of a semiconductor structure or a metal structure.
According to the semiconductor device structure provided by the embodiment of the disclosure, through arranging the ohmic contact structure with the larger lower surface and the smaller upper surface connected with the metal structure, the distance between the metal structure and the adjacent metal structure on the same layer can be reduced under the condition that the design rule is not violated and the resistance of the ohmic contact structure is ensured as low as possible, and the metal structure short circuit in the conductive area or between the conductive areas is effectively avoided.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.
Fig. 1 is a schematic structural view of a semiconductor device structure in an exemplary embodiment of the present disclosure.
Fig. 2 is a flow chart of the fabrication of a semiconductor interposer structure in an embodiment of the present disclosure.
Fig. 3 is a schematic top view of a semiconductor device structure in an exemplary embodiment of the present disclosure.
Fig. 4 is a schematic structural view of a semiconductor device structure in one embodiment of the present disclosure.
Fig. 5A to 5I are schematic views of the manufacturing method of the structure shown in fig. 4.
Fig. 6 is a schematic structural diagram of a semiconductor device structure in one embodiment of the present disclosure.
Fig. 7A to 7L are schematic views of the manufacturing method of the structure shown in fig. 6.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the present disclosure. However, those skilled in the art will recognize that the aspects of the present disclosure may be practiced with one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
Furthermore, the drawings are only schematic illustrations of the present disclosure, in which the same reference numerals denote the same or similar parts, and thus a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities.
The following describes example embodiments of the present disclosure in detail with reference to the accompanying drawings.
Fig. 1 is a schematic structural view of a semiconductor device structure in an exemplary embodiment of the present disclosure.
Referring to fig. 1, a semiconductor device structure 100 may include:
A conductive region 1;
A dielectric layer 2 formed on the conductive region 1;
a metal structure 3 formed on the dielectric layer 2;
The ohmic contact structure 4 is formed in the dielectric layer 2, the first surface 41 is connected to the conductive region 1, the second surface 42 is connected to the metal structure 3, and the length of the second surface 42 in the first direction α is smaller than the length of the first surface 41 in the first direction α, where the first direction α is the shortest distance between the second surface 42 of the ohmic contact structure 4 and the second surface of an adjacent ohmic contact structure.
It will be appreciated that the morphology of the ohmic contact structure between the first surface and the second surface may be varied, for example, as mentioned in connection with the subsequent embodiments of the present disclosure, and thus the structure between the first surface and the second surface is not drawn in detail in fig. 1.
The metal structure 3 in the semiconductor device structure 100 may be, for example, a metal interconnect or a metal pad, and the material of the ohmic contact structure 4 and the material of the metal structure 3 may be the same or different (for example, the material of the ohmic contact structure 4 may be tungsten, and the material of the metal structure 3 may be copper). The conductive region 1 may be an active region of a semiconductor structure or a metal structure, which is not particularly limited by the present disclosure.
Fig. 2 is a schematic diagram of a process flow for fabricating the semiconductor device structure 100 shown in fig. 1.
Referring to fig. 2, a method 200 of fabrication may include, for example:
step S1, providing a conductive area 1;
Step S2, manufacturing a dielectric layer 2 and an ohmic contact structure 4 positioned in the dielectric layer 2 on the conductive region 1, wherein the first surface 41 of the ohmic contact structure 4 is connected with the conductive region 1, the second surface 42 is level with the surface of the dielectric layer 2, and the length of the second surface 42 of the ohmic contact structure 4 in the first direction alpha is smaller than the length of the first surface 41 in the first direction alpha;
In step S3, a metal structure 3 is formed on the dielectric layer 2 and connected to the second surface 42.
Fig. 3 is a top view of the semiconductor device structure 100 shown in fig. 1. For ease of illustration, the metal structure 3, dielectric layer 2 in the figures are shown in semi-transparent form.
Referring to fig. 3, since the design rule specifies that the surface of the metal structure that is in contact with the ohmic contact structure (e.g., the lower surface of the metal structure) must be larger than the size of the surface of the ohmic contact structure that is in contact with the metal structure (e.g., the upper surface of the ohmic contact structure) by a certain amount (the value has a fixed range), in the two ohmic contact structures adjacent to each other in the same layer, since the length of the contact surface (second surface) of the ohmic contact structure 4 with the metal structure 3 is reduced, the length of the surface of the metal structure 3 that is in contact with the ohmic contact structure 4 in the first direction α can be greatly reduced, and since the metal structure 3 is generally thin, the length of each plane of the metal structure 3 that is horizontal to the first surface in the first direction α is also correspondingly reduced, and short-circuiting with the adjacent metal structure (within or between devices) in the same layer can be avoided; meanwhile, since the ohmic contact structure 4 has a larger semiconductor contact area (first surface), the resistance of the whole ohmic contact structure 4 is lower, and the technical improvement purpose of contact low resistance is not violated. As can be seen from fig. 3, the first direction α is the shortest pitch line direction of the second surfaces of the adjacent two ohmic contact structures.
In various embodiments, the ohmic contact structure 4 may have various shapes, and will be described below by way of specific embodiments.
Fig. 4 is a schematic diagram of a semiconductor device structure 400 in one embodiment of the present disclosure.
Referring to fig. 4, in some embodiments, the length of the ohmic contact structure 4 in the first direction α continuously decreases from the first surface 41 toward the second surface 42, i.e., the ohmic contact structure 4 has a trapezoidal cross section perpendicular to the first surface 41 and the second surface 42 in the first direction α.
In the embodiment shown in fig. 4, when the ohmic contact structure 4 is located at the source or drain of the transistor, the gate of the transistor may be directly in front of or directly behind the viewing orientation of the pattern shown in fig. 4.
Fig. 5A to 5I are schematic views illustrating a manufacturing process of the semiconductor device structure in the embodiment shown in fig. 4.
As shown in fig. 5A, a dielectric layer 2 may first be fabricated on a conductive region (active layer) 1. The dielectric layer 2 may be formed by CVD (chemical vapor deposition ), for example, which is not limited by the present disclosure.
Referring to fig. 5B, after coating the photoresist 21 on the dielectric layer 2, an exposure and development process is performed.
Referring to fig. 5C, etching of dielectric layer 2 begins by cleaning photoresist locating contact 22.
Referring to fig. 5D, a trapezoid recess 23 is formed by wet etching or dry etching, the trapezoid recess 23 having an opening at a position corresponding to the contact window 22 in fig. 5C and a bottom surface at a position corresponding to the opening of the conductive region 1, the bottom surface having a length in the first direction α longer than that of the opening in the first direction α. In the above-described process, the trapezoid recess 23 may be formed by controlling the etching rotation speed in the dry etching to change from low to high from the contact window 22 to the direction of the conductive region 1, or by controlling the etching direction of the plasma etching process, or by controlling the concentration change in the wet etching, or the like. The present disclosure is not limited to a specific manufacturing process of the trapezoidal groove 23.
Referring to fig. 5E, after cleaning the photoresist 21 in fig. 5D, the trapezoid recess 23 may be filled with a first metal through a general metal filling process to form the ohmic contact structure 4 and the corresponding first surface 41 and second surface 42 thereof. Wherein the first metal may be tungsten, for example.
Referring to fig. 5F, a metal layer 31 is formed on the upper surface of the dielectric layer 2 (i.e., the second surface 42 of the ohmic contact structure 4), for example, by PVD (Physical Vapor Deposition ), and the target is, for example, copper. In some embodiments, the material of the ohmic contact structure 4 may be the same as that of the metal layer 31. The disclosure is not limited thereto.
Referring to fig. 5G, a photoresist 32 is coated on the metal layer 31, and exposure development is performed.
Referring to fig. 5H, after cleaning portions of the photoresist 32, the metal layer to be cleaned is exposed.
Referring to fig. 5I, after removing the excess portion of the metal layer, metal structure 3 is formed, and then photoresist 32 overlying metal structure 3 may be removed, forming the structure shown in fig. 4.
In some embodiments, the length of the ohmic contact structure 4 in the first direction α decreases stepwise from the first surface 41 to the second surface 42, i.e., the ohmic contact structure 4 has a stepped shape in a cross-section perpendicular to the first surface 41 and the second surface 42 in the first direction.
Fig. 6 is a schematic diagram of a semiconductor device structure in another embodiment of the present disclosure.
Referring to fig. 6, a semiconductor device structure 600 may be composed of N sub-structures (N is equal to 2 in fig. 6), and first to nth sub-structures are sequentially stacked in a conductive region from bottom to top (e.g., from a substrate close to an active layer to a substrate far from the active layer), each sub-structure including a sub-dielectric layer and a sub-ohmic contact structure formed in the sub-dielectric layer, a first surface and a second surface of the sub-ohmic contact structure being respectively horizontal to a lower surface and an upper surface of the sub-dielectric layer, and each plane of the nth sub-ohmic contact structure being horizontal to the first surface has a length in the first direction α greater than a length in the first direction α of each plane of the (n+1) th sub-ohmic contact structure, wherein N is greater than or equal to 2, N is ∈ [1, N ].
Referring to fig. 6, the cross-sectional shapes of the respective sub-structures perpendicular to the first and second surfaces, which refer to the lower and upper surfaces of the respective sub-structures ("steps") in fig. 6, may be the same or different, and may be, for example, rectangular, trapezoidal, etc. The embodiment shown in fig. 6 is n=2, i.e. comprises a first substructure and a second substructure, the cross-sectional shape of the first substructure and the second substructure perpendicular to the first surface 41 and the second surface 42 of the ohmic contact structure 4 in the first direction α is rectangular, and the length of each plane parallel to the upper surface of the conductive region 1 in the first direction α in the first substructure is greater than the length of each plane parallel to the upper surface of the conductive region 1 in the first direction α in the second substructure. It is understood that in other embodiments of the present disclosure, the cross-sectional shape of each sub-structure perpendicular to the first surface and the second surface in the first direction α may be other, which is not particularly limited by the present disclosure.
Fig. 7A to 7L are schematic views of a manufacturing flow of the semiconductor device structure in the embodiment shown in fig. 6.
First, a first dielectric layer 21 of a first substructure is fabricated over the conductive region 1, as shown in fig. 7A. Then, after the photoresist 22 is coated, exposed and developed, and the photoresist is cleaned as shown in fig. 7B, the first contact window 23 is exposed, as shown in fig. 7C.
Referring to fig. 7D, the first recess 24 is etched. The cross-sectional shape of the first groove 24 may be rectangular, for example.
Referring to fig. 7E, the first recess 24 is filled with a first metal to form a first sub-ohmic contact structure 25, and the first sub-ohmic contact structure 25 and the first dielectric layer 21 together form a first sub-structure.
Referring to fig. 7F, a second dielectric layer 26 is formed on the first substructure, and after exposure development, photoresist cleaning, and etching, a second recess 27 is formed, as shown in fig. 7G.
Referring to fig. 7H, the second recess 27 is filled with the first metal to form a second sub-ohmic contact structure 28, and the second sub-ohmic contact structure 28 and the second dielectric layer 26 together form a second sub-structure.
Since the first sub-ohmic contact structure 25 and the second sub-ohmic contact structure 28 together constitute an ohmic contact structure, and the first dielectric layer 21 and the second dielectric layer 26 together constitute a dielectric layer, the dielectric layer is directly denoted as 2 and the ohmic contact structure is denoted as 4, which are not distinguished in the following figures.
Referring to fig. 7I, a metal layer 31 is deposited on the upper surfaces of the dielectric layer 2 and the ohmic contact structure 4.
After the photoresist 32 is coated/exposed and developed as shown in fig. 7J, the photoresist 32 is cleaned as shown in fig. 7K, and the exposed portions are etched as shown in fig. 7L, the remaining photoresist is cleaned away, thereby forming the semiconductor device structure as shown in fig. 7.
Since the above processes are similar to those shown in fig. 5A to 5I, the disclosure is not repeated here.
Similar to the above process, when more sub-structures need to be manufactured, the sub-structures need to be sequentially stacked according to the above process, and a person skilled in the art can adjust parameters such as the number of the sub-structures, the shape of the cross section perpendicular to the first surface and the second surface in the first direction, and the length of each cross section in the first direction according to actual needs.
According to the semiconductor device structure, through the arrangement of the ohmic contact structure with the larger lower surface and the smaller upper surface connected with the metal structure, the distance between the metal structure and the adjacent metal structure on the same layer can be reduced under the conditions that the design rule is not violated and the lower resistance of the ohmic contact structure is guaranteed as much as possible, and the metal structure short circuit in the conductive area or between the conductive areas is effectively avoided.
It should be noted that although in the above detailed description several modules or units of a device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit in accordance with embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into a plurality of modules or units to be embodied.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (10)
1. A semiconductor device structure, comprising:
A conductive region;
A dielectric layer formed on the conductive region;
the metal structure is formed on the dielectric layer;
The ohmic contact structure is formed in the dielectric layer, the first surface is connected with the conductive region, the second surface is connected with the metal structure, the length of the second surface in the first direction is smaller than that of the first surface in the first direction, the first direction is the shortest interval connecting direction between the second surface of the ohmic contact structure and the second surface of an adjacent ohmic contact structure, the first substructure to the N substructure are sequentially stacked on the conductive region, the substructure comprises a sub-dielectric layer and a sub-ohmic contact structure formed in the sub-dielectric layer, the lengths of the first surface and the second surface of the sub-ohmic contact structure in the first direction are respectively equal to that of the first surface and the second surface of the sub-dielectric layer, and the lengths of planes parallel to the first surface in the n+1th sub-ohmic contact structure in the first direction are respectively larger than that of planes parallel to the first surface in the first direction, wherein N is more than or equal to 2, N E [1, N ].
2. The semiconductor device structure of claim 1, wherein a length of each plane of the ohmic contact structure parallel to the first surface in the first direction continuously decreases or stepwise decreases from the first surface to the second surface.
3. The semiconductor device structure of claim 1, wherein the conductive region is an active region of a semiconductor structure or a metal structure.
4. The semiconductor device structure of claim 1, wherein a material of the ohmic contact structure is the same as a material of the metal structure, or wherein a material of the ohmic contact structure is tungsten and a material of the metal structure is copper.
5. A method of fabricating a semiconductor device structure, comprising:
Providing a conductive region;
An ohmic contact structure positioned in a dielectric layer is manufactured on the conductive region, a first surface of the ohmic contact structure is connected with the conductive region, a second surface of the ohmic contact structure is horizontal to the surface of the dielectric layer, the length of the second surface in a first direction is smaller than that of the first surface in the first direction, the first direction is the shortest distance connecting line direction between the second surface of the ohmic contact structure and the second surface of an adjacent ohmic contact structure on the same layer, and the distance between the second surface and the adjacent ohmic contact structure on the same layer is larger than that between the first surface and the adjacent ohmic contact structure on the same layer;
Manufacturing a metal structure connected with the second surface on the dielectric layer;
The manufacturing the ohmic contact structure in the dielectric layer on the conductive region comprises the following steps:
and sequentially stacking and manufacturing first to N-th substructures on the conductive region, wherein the substructures comprise a sub-dielectric layer and sub-ohmic contact structures formed in the sub-dielectric layer, the first surface and the second surface of the sub-ohmic contact structures are respectively horizontal to the first surface and the second surface of the sub-dielectric layer, and the lengths of planes parallel to the first surface in the N-th sub-ohmic contact structures in the first direction are larger than the lengths of planes parallel to the first surface in the n+1-th sub-ohmic contact structures in the first direction, wherein N is more than or equal to 2, N E [1, N ].
6. The method of claim 5, wherein fabricating an ohmic contact structure in a dielectric layer on the conductive region comprises:
Manufacturing the dielectric layer on the conductive region;
etching a groove with the same shape and size as the ohmic contact structure in the dielectric layer;
And filling the groove with a first metal.
7. The method of claim 5, wherein n=2, and wherein fabricating the sub-structure 1 to the sub-structure N on the conductive region N times comprises:
manufacturing a first sub-dielectric layer on the conductive area;
etching a first groove in the first sub-dielectric layer;
Filling the first groove with first metal to form a first sub-ohmic contact structure and a first sub-structure simultaneously;
Manufacturing a second sub-medium layer on the first sub-structure;
Etching a second groove in the second sub-medium layer, wherein the lengths of the second groove and each plane of the first surface level in the first direction are smaller than the lengths of the first groove and each plane of the first surface level in the first direction;
and filling the second groove with the first metal to form a second sub-ohmic contact structure and a second sub-structure simultaneously.
8. A method as claimed in claim 5 or 7, wherein each plane of the n-th sub-ohmic contact structure parallel to the first surface is rectangular or trapezoidal in cross-section perpendicular to the first surface and the second surface in the first direction.
9. The method of claim 6 or 7, wherein the first metal is the same as the metal structure, or the first metal is tungsten and the metal structure is copper.
10. The method of any one of claims 5-7, wherein the conductive region is an active region of a semiconductor structure or a metal structure.
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