CN112397577A - Semiconductor device structure and manufacturing method thereof - Google Patents
Semiconductor device structure and manufacturing method thereof Download PDFInfo
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- CN112397577A CN112397577A CN201910750969.3A CN201910750969A CN112397577A CN 112397577 A CN112397577 A CN 112397577A CN 201910750969 A CN201910750969 A CN 201910750969A CN 112397577 A CN112397577 A CN 112397577A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 78
- 239000002184 metal Substances 0.000 claims abstract description 78
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
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- 238000004140 cleaning Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
Abstract
The present disclosure provides a semiconductor device structure comprising: a conductive region; a dielectric layer formed on the conductive region; the metal structure is formed on the dielectric layer; and the ohmic contact structure is formed in the dielectric layer, the first surface is connected with the conductive area, the second surface is connected with the metal structure, the length of the second surface in the first direction is smaller than that of the first surface in the first direction, and the first direction is the shortest distance connecting line direction of the second surface of the ohmic contact structure and the second surface of the adjacent ohmic contact structure on the same layer. The embodiment of the disclosure can simultaneously have lower ohmic contact resistance and larger interval between adjacent metal structures on the same layer, and effectively prevent the short circuit of the metal structures in the conductive regions or between the conductive regions.
Description
Technical Field
The present disclosure relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor device structure and a method for manufacturing the same.
Background
Due to the advance of advanced manufacturing processes, the transistor size is continuously reduced, the channel length is shorter and shorter, and the occupation ratio of the corresponding ohmic contact structure (contact) is larger and larger. In order to increase the operating current and speed of the transistor, it is necessary to reduce the resistance of the ohmic contact structure, which is usually achieved by increasing the length of the ohmic contact structure in the semiconductor manufacturing technology.
However, since the design rule stipulates that the size of the surface (lower surface of the metal structure) connected with the ohmic contact structure in the metal structure must be larger than the size of the surface (upper surface of the ohmic contact structure) connected with the metal structure in the ohmic contact structure by a certain value, the increase of the length of the ohmic contact structure inevitably leads to the corresponding increase of the length of the metal structure, increases the difficulty of the metal interconnection process, easily leads to the short circuit of the metal interconnection line in the device or between the devices, and forms a new process problem.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
An object of the present disclosure is to provide a semiconductor device structure for overcoming, at least to some extent, the problem of easy short-circuiting of metal structures within or between conductive regions due to limitations and disadvantages of the related art.
According to a first aspect of embodiments of the present disclosure, there is provided a semiconductor device structure, comprising:
a conductive region;
a dielectric layer formed on the conductive region;
the metal structure is formed on the dielectric layer;
and the ohmic contact structure is formed in the dielectric layer, the first surface is connected with the conductive area, the second surface is connected with the metal structure, the length of the second surface in the first direction is smaller than that of the first surface in the first direction, and the first direction is the shortest distance connecting line direction of the second surface of the ohmic contact structure and the second surface of the adjacent ohmic contact structure on the same layer.
In an exemplary embodiment of the present disclosure, a length of the ohmic contact structure in the first direction is continuously reduced or stepped-reduced from the first surface to the second surface.
In one exemplary embodiment of the present disclosure, the conductive region is an active region of a semiconductor structure or a metal structure.
In one exemplary embodiment of the present disclosure, the ohmic contact structure includes a first portion and a second portion, the first portion being located above the second portion, a length of the first portion in the first direction being less than a length of the second portion in the first direction.
In an exemplary embodiment of the present disclosure, a cross section of the first portion and/or the second portion perpendicular to the first surface and the second surface in the first direction is rectangular or trapezoidal.
In an exemplary embodiment of the disclosure, the material of the ohmic contact structure is the same as the material of the metal structure, or the material of the ohmic contact structure is tungsten and the material of the metal structure is copper.
According to an aspect of the present disclosure, there is provided a method for fabricating a semiconductor device structure, including:
providing a conductive region;
the method comprises the steps that an ohmic contact structure located in a dielectric layer is manufactured on a conductive area, a first surface of the ohmic contact structure is connected with the conductive area, a second surface of the ohmic contact structure is horizontal to the surface of the dielectric layer, the length of the second surface in a first direction is smaller than that of the first surface in the first direction, the first direction is the shortest distance connecting line direction of the second surface of the ohmic contact structure and the second surface of an adjacent ohmic contact structure on the same layer, and the distance between the second surface and the adjacent ohmic contact structure on the same layer is larger than that between the first surface and the adjacent ohmic contact structure on the same layer;
and manufacturing a metal structure connected with the second surface on the dielectric layer.
In one exemplary embodiment of the present disclosure, fabricating an ohmic contact structure in a dielectric layer on a conductive region includes:
manufacturing a dielectric layer on the conductive area;
etching a trapezoidal groove in the dielectric layer, wherein a first surface of the trapezoidal groove is connected with the conductive region, a second surface of the trapezoidal groove is horizontal to the surface of the dielectric layer, and the length of the second surface in the first direction is smaller than that of the first surface in the first direction;
the trapezoidal groove is filled with a first metal.
In one exemplary embodiment of the present disclosure, fabricating an ohmic contact structure in a dielectric layer on a conductive region includes:
sequentially stacking and manufacturing a first substructure to an Nth substructure on the conductive region, wherein the substructure comprises a sub-medium layer and a sub-ohmic contact structure formed in the sub-medium layer, the first surface and the second surface of the sub-ohmic contact structure are respectively horizontal to the first surface and the second surface of the sub-medium layer, the length of each plane of the N-th sub-ohmic contact structure and the first surface in the first direction is greater than that of each plane of the N + 1-th sub-ohmic contact structure and the first surface in the first direction, N is greater than or equal to 2, and N belongs to [1, N ].
In one exemplary embodiment of the present disclosure, N ═ 2, fabricating sub-structures 1 through N times on the conductive region includes:
manufacturing a first sub-dielectric layer on the conductive area;
etching a first groove in the first sub-dielectric layer;
filling the second groove with a first metal to simultaneously form a first sub-ohmic contact structure and a first sub-structure;
manufacturing a second sub-dielectric layer on the first sub-structure;
etching a second groove in the second sub-dielectric layer, wherein the length of each horizontal plane of the second groove and the first surface in the first direction is smaller than that of each horizontal plane of the first groove and the first surface in the first direction;
and filling the first metal into the second groove to simultaneously form a second sub-ohmic contact structure and a second sub-structure.
In an exemplary embodiment of the present disclosure, each of the n-th sub-ohmic contact structures and the planes horizontal to the first surface have a rectangular or trapezoidal cross section perpendicular to the first surface and the second surface in the first direction.
In an exemplary embodiment of the disclosure, the first metal and the metal structure are made of the same material, or the first metal is tungsten and the metal structure is made of copper.
In one exemplary embodiment of the present disclosure, the conductive region is an active region of a semiconductor structure or a metal structure.
According to the semiconductor device structure provided by the embodiment of the disclosure, by arranging the ohmic contact structure with the larger lower surface and the smaller upper surface connected with the metal structure, the distance between the metal structure and the adjacent metal structure on the same layer can be reduced under the condition that the design rule is not violated and the lower resistance of the ohmic contact structure is ensured as much as possible, so that the short circuit of the metal structure in the conductive region or between the conductive regions is effectively avoided.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
Fig. 1 is a schematic structural diagram of a semiconductor device structure in an exemplary embodiment of the present disclosure.
Figure 2 is a flow chart illustrating the fabrication of a semiconductor interposer structure according to an embodiment of the present disclosure.
Fig. 3 is a schematic top view of a semiconductor device structure in an exemplary embodiment of the present disclosure.
Fig. 4 is a schematic structural diagram of a semiconductor device structure in one embodiment of the present disclosure.
Fig. 5A to 5I are schematic views illustrating a method of manufacturing the structure shown in fig. 4.
Fig. 6 is a schematic structural diagram of a semiconductor device structure in one embodiment of the present disclosure.
Fig. 7A to 7L are schematic views illustrating a method of manufacturing the structure shown in fig. 6.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and the like. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
Further, the drawings are merely schematic illustrations of the present disclosure, in which the same reference numerals denote the same or similar parts, and thus, a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities.
The following detailed description of exemplary embodiments of the disclosure refers to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a semiconductor device structure in an exemplary embodiment of the present disclosure.
Referring to fig. 1, a semiconductor device structure 100 may include:
a conductive region 1;
a dielectric layer 2 formed on the conductive region 1;
the metal structure 3 is formed on the dielectric layer 2;
the ohmic contact structure 4 is formed in the dielectric layer 2, the first surface 41 is connected with the conductive region 1, the second surface 42 is connected with the metal structure 3, and the length of the second surface 42 in the first direction α is smaller than that of the first surface 41 in the first direction α, wherein the first direction α is the shortest distance connection line direction between the second surface 42 of the ohmic contact structure 4 and the second surface of the adjacent ohmic contact structure in the same layer.
It is understood that the ohmic contact structure may have various forms between the first surface and the second surface, such as those mentioned in the subsequent embodiments of the present disclosure, and thus, the structure between the first surface and the second surface is not drawn in detail in fig. 1.
The metal structure 3 in the semiconductor device structure 100 may be, for example, a metal interconnect or a metal pad, and the ohmic contact structure 4 and the metal structure 3 may be made of the same material or different materials (for example, the ohmic contact structure 4 may be made of tungsten, and the metal structure 3 may be made of copper). The conductive region 1 may be an active region of a semiconductor structure or a metal structure, and the present disclosure is not particularly limited thereto.
Fig. 2 is a schematic flow chart illustrating a process for fabricating the semiconductor device structure 100 shown in fig. 1.
Referring to fig. 2, the fabrication method 200 may include, for example:
step S1, providing a conductive region 1;
step S2, manufacturing a dielectric layer 2 and an ohmic contact structure 4 located in the dielectric layer 2 on the conductive region 1, where a first surface 41 of the ohmic contact structure 4 is connected to the conductive region 1, a second surface 42 is horizontal to a surface of the dielectric layer 2, and a length of the second surface 42 of the ohmic contact structure 4 in a first direction α is smaller than a length of the first surface 41 in the first direction α;
in step S3, a metal structure 3 connected to the second surface 42 is formed on the dielectric layer 2.
Fig. 3 is a top view of the semiconductor device structure 100 shown in fig. 1. For the sake of illustration, the metal structure 3 and the dielectric layer 2 are shown in a semitransparent form in the drawings.
Referring to fig. 3, since the design rule specifies that the size of the surface of the metal structure (e.g., the lower surface of the metal structure) contacting the ohmic contact structure must be larger than the size of the surface of the ohmic contact structure (e.g., the upper surface of the ohmic contact structure) contacting the metal structure by a certain value (the value has a fixed range), in two ohmic contact structures adjacent to the same layer, the length of the surface of the metal structure 3 contacting the ohmic contact structure 4 in the first direction α can be greatly reduced due to the reduction of the length of the contact surface (the second surface) of the ohmic contact structure 4 and the metal structure 3, and since the metal structure 3 is generally thin, the length of each plane of the metal structure 3 horizontal to the first surface in the first direction α is also correspondingly reduced, so as to avoid short circuit with the adjacent metal structure (in-device or between devices) in the same layer; meanwhile, since the ohmic contact structure 4 has a large semiconductor contact area (first surface), the resistance of the entire ohmic contact structure 4 is low, and the purpose of the technical improvement of contact low resistance is not violated. As can be seen from fig. 3, the first direction α is a shortest-pitch connecting line direction of the second surfaces of two adjacent ohmic contact structures.
In various embodiments, the shape of the ohmic contact structure 4 may be varied, and will be described below with reference to specific embodiments.
Fig. 4 is a schematic diagram of a semiconductor device structure 400 in one embodiment of the present disclosure.
Referring to fig. 4, in some embodiments, the length of the ohmic contact structure 4 in the first direction α is continuously decreased from the first surface 41 to the second surface 42, i.e., the cross section of the ohmic contact structure 4 perpendicular to the first surface 41 and the second surface 42 in the first direction α is trapezoidal.
In the embodiment shown in fig. 4, when the ohmic contact structure 4 is located at the source or drain of the transistor, the gate of the transistor may be directly in front of or directly behind the viewing orientation of the figure shown in fig. 4.
Fig. 5A to 5I are schematic views illustrating a manufacturing flow of the semiconductor device structure in the embodiment shown in fig. 4.
As shown in fig. 5A, a dielectric layer 2 may first be fabricated on the conductive region (active layer) 1. The dielectric layer 2 may be formed by CVD (chemical vapor deposition), for example, and the disclosure is not limited thereto.
Referring to fig. 5B, after the photoresist 21 is coated on the dielectric layer 2, an exposure and development process is performed.
Referring to fig. 5C, the etching of the dielectric layer 2 is started by cleaning the photoresist positioning contact windows 22.
Referring to fig. 5D, a trapezoidal groove 23 is formed by wet etching or dry etching, the trapezoidal groove 23 has a position corresponding to the contact window 22 in fig. 5C as an opening, and a position corresponding to the opening of the conductive region 1 as a bottom surface, and a length of the bottom surface in the first direction α is longer than a length of the opening in the first direction α. In the above process, the trapezoidal groove 23 may be formed by controlling the etching rotation speed in the dry etching from the contact window 22 to the conductive region 1 from low to high, or by controlling the etching direction of the plasma etching process, or by controlling the concentration change in the wet etching. The present disclosure does not limit the specific manufacturing process of the trapezoidal groove 23.
Referring to fig. 5E, after the photoresist 21 in fig. 5D is cleaned, a first metal may be filled into the trapezoidal groove 23 through a general metal filling process to form the ohmic contact structure 4 and the corresponding first surface 41 and second surface 42. Wherein the first metal may be tungsten, for example.
Referring to fig. 5F, a metal layer 31 is formed on the upper surface of the dielectric layer 2 (i.e., the second surface 42 of the ohmic contact structure 4) by, for example, PVD (Physical Vapor Deposition), and the target is, for example, copper. In some embodiments, the material of the ohmic contact structure 4 may be the same as the material of the metal layer 31. The present disclosure is not so limited.
Referring to fig. 5G, a photoresist 32 is coated on the metal layer 31, and exposure development is performed.
Referring to fig. 5H, after cleaning a portion of the photoresist 32, the metal layer to be removed is exposed.
Referring to fig. 5I, after removing the excess portion of the metal layer, the metal structure 3 is formed, and then the photoresist 32 covering the metal structure 3 may be removed, so as to form the structure shown in fig. 4.
In some embodiments, the length of the ohmic contact structure 4 in the first direction α decreases in a step shape from the first surface 41 to the second surface 42, that is, the cross-sectional shape of the ohmic contact structure 4 perpendicular to the first surface 41 and the second surface 42 in the first direction is a step shape.
Fig. 6 is a schematic diagram of a semiconductor device structure in another embodiment of the present disclosure.
Referring to fig. 6, the semiconductor device structure 600 may be composed of N sub-structures (N is equal to 2 in fig. 6), and first to nth sub-structures are sequentially stacked in the conductive region from bottom to top (e.g., from a substrate close to the active layer to a substrate far from the active layer), each sub-structure including a sub-dielectric layer and a sub-ohmic contact structure formed in the sub-dielectric layer, a first surface and a second surface of the sub-ohmic contact structure are respectively horizontal to a lower surface and an upper surface of the sub-dielectric layer, and a length of each plane horizontal to the first surface in the nth sub-ohmic contact structure in the first direction α is greater than a length of each plane horizontal to the first surface in the nth +1 th sub-ohmic contact structure in the first direction α, where N ≧ 2, N ∈ [1, N ].
Referring to fig. 6, the cross-sectional shapes of the sub-structures perpendicular to the first surface and the second surface, which are referred to as the lower surface and the upper surface of each sub-structure ("step") in fig. 6, in the first direction α may be the same or different, and may be, for example, rectangular, trapezoidal, etc. The embodiment shown in fig. 6 is N ═ 2, that is, includes a first substructure and a second substructure, the cross-sectional shapes of the first substructure and the second substructure perpendicular to the first surface 41 and the second surface 42 of the ohmic contact structure 4 in the first direction α are both rectangular, and the length of each plane parallel to the upper surface of the conductive region 1 in the first direction α in the first substructure is greater than the length of each plane parallel to the upper surface of the conductive region 1 in the second substructure in the first direction α. It is understood that, in other embodiments of the present disclosure, the cross-sectional shape of each substructure perpendicular to the first and second surfaces in the first direction α may also be other schemes, and the present disclosure does not specifically limit this.
Fig. 7A to 7L are schematic views illustrating a manufacturing flow of the semiconductor device structure in the embodiment shown in fig. 6.
First, a first dielectric layer 21 of a first substructure is formed on the conductive region 1, as shown in fig. 7A. Then, after coating the photoresist 22, exposing and developing, and cleaning the photoresist as shown in fig. 7B, the first contact window 23 is exposed, as shown in fig. 7C.
Referring to fig. 7D, a first groove 24 is etched. The cross-sectional shape of the first groove 24 may be, for example, rectangular.
Referring to fig. 7E, the first groove 24 is filled with a first metal to form a first sub-ohmic contact structure 25, and the first sub-ohmic contact structure 25 and the first dielectric layer 21 together form a first sub-structure.
Referring to fig. 7F, a second dielectric layer 26 is formed on the first substructure, and a second groove 27 is formed after exposure, development, photoresist cleaning, and etching, as shown in fig. 7G.
Referring to fig. 7H, the second recess 27 is filled with the first metal to form a second sub-ohmic contact structure 28, and the second sub-ohmic contact structure 28 and the second dielectric layer 26 together form a second sub-structure.
Since the first sub-ohmic contact structure 25 and the second sub-ohmic contact structure 28 together form an ohmic contact structure, and the first dielectric layer 21 and the second dielectric layer 26 together form a dielectric layer, they are not distinguished in the following figures, and the dielectric layer is directly labeled as 2, and the ohmic contact structure is labeled as 4.
Referring to fig. 7I, a metal layer 31 is deposited on the upper surfaces of the dielectric layer 2 and the ohmic contact structures 4.
After the photoresist 32 is coated/exposed and developed as shown in fig. 7J, the photoresist 32 is cleaned as shown in fig. 7K, and the exposed position is etched as shown in fig. 7L, the remaining photoresist is cleaned, so as to form the semiconductor device structure as shown in fig. 7.
Since the above process is similar to the process shown in fig. 5A to 5I, the disclosure is not repeated herein.
Similar to the above process, when more substructures need to be fabricated, the substructures only need to be sequentially stacked and fabricated according to the above process, and a person skilled in the art can adjust parameters such as the number of the substructures, the shapes of the cross sections perpendicular to the first surface and the second surface in the first direction, and the lengths of the cross sections in the first direction according to actual needs.
According to the semiconductor device structure, the ohmic contact structure with the larger lower surface and the smaller upper surface connected with the metal structure is arranged, so that the distance between the metal structure and the adjacent metal structure on the same layer can be reduced under the condition that the design rule is not violated and the lower resistance of the ohmic contact structure is guaranteed as much as possible, and the short circuit of the metal structure in the conductive region or between the conductive regions is effectively avoided.
It should be noted that although in the above detailed description several modules or units of the device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit, according to embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into embodiments by a plurality of modules or units.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (13)
1. A semiconductor device structure, comprising:
a conductive region;
a dielectric layer formed on the conductive region;
the metal structure is formed on the dielectric layer;
and the ohmic contact structure is formed in the dielectric layer, the first surface is connected with the conductive area, the second surface is connected with the metal structure, the length of the second surface in a first direction is smaller than that of the first surface in the first direction, and the first direction is the shortest distance connecting line direction of the second surface of the ohmic contact structure and the second surface of the adjacent ohmic contact structure on the same layer.
2. The semiconductor device structure of claim 1, wherein the length of each plane parallel to the first surface in the ohmic contact structure in the first direction decreases continuously or in steps from the first surface to the second surface.
3. The semiconductor device structure of claim 1, wherein the conductive region is an active region of a semiconductor structure or a metal structure.
4. The semiconductor device structure of claim 2, wherein the ohmic contact structure comprises a first portion and a second portion, the first portion being located over the second portion, a length of the first portion in the first direction being less than a length of the second portion in the first direction.
5. The semiconductor device structure of claim 4, wherein a cross-section of the first portion and/or the second portion perpendicular to the first surface and the second surface in the first direction is rectangular or trapezoidal.
6. The semiconductor device structure of claim 1, wherein the ohmic contact structure is made of the same material as the metal structure, or the ohmic contact structure is made of tungsten and the metal structure is made of copper.
7. A method for fabricating a semiconductor device structure, comprising:
providing a conductive region;
manufacturing an ohmic contact structure in a dielectric layer on the conductive region, wherein a first surface of the ohmic contact structure is connected with the conductive region, a second surface of the ohmic contact structure is horizontal to the surface of the dielectric layer, the length of the second surface in a first direction is smaller than that of the first surface in the first direction, the first direction is a shortest distance connecting line direction of the second surface of the ohmic contact structure and a second surface of an adjacent ohmic contact structure on the same layer, and the distance between the second surface and the adjacent ohmic contact structure on the same layer is larger than that between the first surface and the adjacent ohmic contact structure on the same layer;
and manufacturing a metal structure connected with the second surface on the dielectric layer.
8. The method of claim 7, wherein forming an ohmic contact structure in a dielectric layer on the conductive region comprises:
manufacturing the dielectric layer on the conductive area;
etching a groove with the same shape and size as the ohmic contact structure in the dielectric layer;
and filling the groove with a first metal.
9. The method of claim 7, wherein forming an ohmic contact structure in a dielectric layer on the conductive region comprises:
and sequentially stacking and manufacturing a first substructure to an Nth substructure on the conductive region, wherein the substructure comprises a sub-medium layer and a sub-ohmic contact structure formed in the sub-medium layer, the first surface and the second surface of the sub-ohmic contact structure are respectively horizontal to the first surface and the second surface of the sub-medium layer, the length of each plane parallel to the first surface in the N-th sub-ohmic contact structure in the first direction is greater than that of each plane parallel to the first surface in the N + 1-th sub-ohmic contact structure in the first direction, N is greater than or equal to 2, and N belongs to [1, N ].
10. The method of claim 9, wherein N-2, and wherein fabricating sub-structures 1-N on the conductive region N times comprises:
manufacturing a first sub-dielectric layer on the conductive area;
etching a first groove in the first sub-dielectric layer;
filling a first metal into the first groove to simultaneously form a first sub-ohmic contact structure and a first sub-structure;
manufacturing a second sub-dielectric layer on the first sub-structure;
etching a second groove in the second sub-dielectric layer, wherein the lengths of the second groove and each plane horizontal to the first surface in the first direction are both smaller than the lengths of the first groove and each plane horizontal to the first surface in the first direction;
and filling the first metal into the second groove to simultaneously form a second sub-ohmic contact structure and a second sub-structure.
11. The method according to claim 9 or 10, wherein a cross section of each plane parallel to the first surface in the n-th sub-ohmic contact structure perpendicular to the first surface and the second surface in the first direction is rectangular or trapezoidal.
12. The method according to claim 8 or 10, wherein the first metal and the metal structure are made of the same material, or the first metal is tungsten and the metal structure is made of copper.
13. The method of any of claims 7 to 10, wherein the conductive region is an active region of a semiconductor structure or a metal structure.
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