1290372 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種液晶顯示面板之製造方法，且特 別是有關於一種薄膜電晶體陣列基板的製造方法。 . 【先前技術】 . 近年來光電相關技術不斷地推陳出新，加上數位化時 Φ 代的到來，進而推動了液晶顯示器市場的蓬勃發展。液晶 ·、、、頁示器具有咼晝質、體積小、重量輕、低驅動電壓、與低 消耗功率等優點，因此被廣泛應用於個人數位助理（pda)、 行動電話、攝錄放影機、筆記型電腦、桌上型顯示器、車 用顯示器、及投影電視等消費性通訊或電子產品，並逐漸 取代陰極射線管而成為顯示器的主流。 液晶顯示器（Liquid Crystal Display，LCD)是一種利用 液晶特性來達到顯示效果的顯示裝置，由於其較傳統常用 _ 之陰極射線管顯示器在尺寸與重量方面有更佳的彈性，因 此，液晶顯示器目前常被使用在各種的個人系統上，小從 . 仃動電話、個人數位助理及數位相機上的顯示幕，大到電 視機及廣告看板，處處都可以見到液晶顯示器的影子。 液晶顯示器之所以能夠較傳統之陰極射線管顯示器在 尺寸及重量更有彈性，是因為液晶顯示器的大部份元件都 是平板狀的，因此可視應用需求將這些元件切割成適中的 尺寸，在重量上也較有著龐大立體外形的陰極射線管來得 輕巧許多。 眾所皆知光罩的價錢昂貴，光罩數越多即意味著所需 5 1290372 支付的成本越高’另外，製造時程也會越長，所以減少光 罩數，除了可降低成本之外，還可以加速產出速度，增加 產品的競筆力。因此，本發明及針對習知的缺點，減少非 晶矽液晶顯示螢幕製程所使用的光罩數，即降低製造的成 本，而使產品更具有競爭力。 在敖薄膜電晶體陣列基板的製程中，已可將所使用 的光罩數目縮減到五道或四道光罩製程。第i圖係搶示傳 統四道光罩製程所形成之薄膜電晶體陣列基板剖面示意 圖。如第1圖所示，在玻璃基板1〇〇上具有閘極1〇2，介電 層104覆蓋閘極102，半導體層106覆蓋介電層104,歐姆 接觸層108,電極層11〇則位於歐姆接觸層1〇8之上，一開 口分斷位於閘極102上方之歐姆接觸層1〇8及電極層ιι〇, 一絕緣保護層114覆蓋於玻璃基板100之結構之上。當薄 膜電晶體陣列基板受到背光116照射時，半導體層106會 產生光電流而改變薄膜電晶體的電性。 再以一般四道光罩製程為例，第2圖係繪示習知製程 中縮減使用光罩數目的關鍵步驟的剖面示意圖。在玻璃基 板100上具有閘極102 ’依序形成介電層1〇4、半導體層 106、歐姆接觸層108、電極層11〇於玻璃基板1〇〇之上。 在塗佈光阻層（未㈣於圈上）後，再以半調式（half_tone) 光罩來進行曝光以及進行後續的顯影步驟，而形成圖案化 光阻層112,圖案化光阻層112在閘極1〇2的上方欲形成源 極/汲極及通道區的區域且成凹字型狀，再利用不同的姓刻 方式形成電晶體。光阻^ 112在預定形成通道區的位置具 有一較小的厚而光阻層112其他部分的厚度係為 1290372 阻層112的厚度在欲形成源W汲極及通道區的區域 域種不同的厚度，這是整個製程關鍵。因為在同一區 ^ ^ (taper angle)^ ^ ^先阻厚度hi都會影響後續㈣的結果，所以兩者的 控制疋非常的重要’但是在實際製程上非常不易控制。 因此’如何繼續減少光罩使用的數目以及維持製程的 率並減少光電流的發生成為-個困難的問題βBACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a method of fabricating a liquid crystal display panel, and more particularly to a method of fabricating a thin film transistor array substrate. [Prior Art] In recent years, optoelectronic related technologies have been continuously introduced, and the arrival of Φ generation in digitalization has promoted the vigorous development of the liquid crystal display market. The liquid crystal·, , and pager have the advantages of enamel, small size, light weight, low driving voltage, and low power consumption, so they are widely used in personal digital assistants (PDAs), mobile phones, and camcorders. Consumer communication or electronic products such as notebook computers, desktop monitors, car monitors, and projection televisions have gradually replaced cathode ray tubes and become the mainstream of displays. Liquid crystal display (LCD) is a display device that uses liquid crystal characteristics to achieve display effects. Since it is more flexible in size and weight than conventional cathode ray tube displays, liquid crystal displays are often used. It is used in a variety of personal systems, from the mobile phone, personal digital assistant and digital camera display screen, to the TV and advertising billboards, you can see the shadow of the LCD display everywhere. The reason why liquid crystal displays can be more flexible in size and weight than conventional cathode ray tube displays is because most of the components of liquid crystal displays are flat, so these components can be cut into moderate size according to the application requirements. It is also much lighter than a cathode ray tube with a large three-dimensional shape. It is well known that the price of the mask is expensive. The more the number of masks, the higher the cost of the required 5 1290372. In addition, the longer the manufacturing time will be, so the number of masks is reduced, in addition to reducing costs. It can also speed up the output and increase the product's competitive power. Accordingly, the present invention and the conventional disadvantages reduce the number of reticle used in the non-silicone liquid crystal display screen process, i.e., reduce the cost of manufacturing, and make the product more competitive. In the process of thin film transistor array substrates, the number of masks used can be reduced to five or four mask processes. The i-th image is a schematic cross-sectional view of the thin film transistor array substrate formed by the conventional four-mask process. As shown in Fig. 1, there is a gate 1〇2 on the glass substrate 1 , a gate 102 covering the dielectric layer 104, a dielectric layer 104 covering the dielectric layer 104, an ohmic contact layer 108, and an electrode layer 11 Above the ohmic contact layer 1〇8, an opening breaks the ohmic contact layer 1〇8 and the electrode layer ιι located above the gate 102, and an insulating protective layer 114 covers the structure of the glass substrate 100. When the thin film transistor array substrate is irradiated by the backlight 116, the semiconductor layer 106 generates a photocurrent to change the electrical properties of the thin film transistor. Taking a general four-mask process as an example, FIG. 2 is a schematic cross-sectional view showing the key steps of reducing the number of masks used in the conventional process. A dielectric layer 1 〇 4, a semiconductor layer 106, an ohmic contact layer 108, and an electrode layer 11 are sequentially formed on the glass substrate 100 with a gate electrode 102' on the glass substrate 1''. After coating the photoresist layer (not (four) on the circle), exposure is performed with a half-tone mask and subsequent development steps to form a patterned photoresist layer 112, and the patterned photoresist layer 112 is Above the gate 1〇2, a region of the source/drain and the channel region is formed and formed into a concave shape, and a transistor is formed by using different surnames. The photoresist 112 has a small thickness at a position where the channel region is to be formed, and the thickness of the other portion of the photoresist layer 112 is 1290372. The thickness of the resist layer 112 is different in the region where the source W drain and the channel region are to be formed. Thickness, this is the key to the entire process. Since the resistance h in the same area ^ ^ (taper angle) ^ ^ ^ will affect the result of the subsequent (4), the control of the two is very important 'but it is very difficult to control in the actual process. Therefore, how to continue to reduce the number of reticle use and maintain the process rate and reduce the occurrence of photocurrent becomes a difficult problem.
【發明内容】 有鏗於此，本發明的目的在提供一種薄膜電晶體陣列 土板的製造方法，可以使用四道光罩即可完成晝素電極及 驅動電晶體的製程。 ”皮本發明的另一目的在提供一種薄膜電晶體陣列基板的 製4方法，可以大幅降低製造的成本，使產品更具有競爭 力。 ,本發明的又一目的在提供一種薄膜電晶體陣列基板的 製造方法，可以有效避免通道區光電流的發生。 本發明的再一目的在提供一種薄膜電晶體陣列基板的 製這方法’可以使用離子佈植而在通道區表面形成歐姆接 觸層。 本發明的再又一目的在提供一種薄膜電晶體陣列基板 的製造方法，可以運用半調式光罩以縮減所使用的光罩 數’且避免習知光阻層厚度及角度上控制的困難。 根據本發明之上述目的，本發明之一較佳實施例提出 一種薄膜電晶體陣列基板的製造方法，使用四道光罩製 7 1290372 程’即可完成晝素電極及驅動電晶體的製造。四道光罩製 程分別包括··在第一道光罩製程定義閘極，接著，依序沉 積介電層、半導體層及導體層；接著，以第二道光罩製程 定義出通道區和訊號電極。第二道光罩製程係利用半調式 光罩來進行，藉由一半色調灰階（Halft〇ne Gray Level)曝光 劑量分佈對一光阻層進行曝光顯影而分別在通道區域及欲 形成訊號電極區域定義出不同的光阻層厚度，其中，在欲 形成訊號電極區域之光阻層厚度最厚、通道區域的光阻層 厚度其次而其他區域為光阻全開區域。在利用不同的蝕刻 (乾蝕刻或濕蝕刻製程）完成通道區及訊號電極的定義之 後，移除通道區上方之光阻層而暴露出導體層。由於在訊 號電極上方之光阻層較厚，仍會有一定厚度之光阻層位於 訊號電極的上方。接著，以一蝕刻製程移除通道區上之導 體層。其中，介電層的材料可以例如為氮化石夕或氮氧化石夕， 半導體層的材料可以例如為多晶石夕或非晶石夕。 接著，再沉積一絕緣保護層於所有元件結構之上，並 以第三道光罩製程在通道區上定義出源/汲極接觸窗、訊號 電極接觸窗以分別暴露出通道區及訊號電極的表面。接 著，實施一離子佈植以在暴露出的通道區表面形成歐姆接 觸。接著沉積透明導體層，並以第四道光罩製程定義出源/ 沒極、畫素電極、訊號電極（資料線）接觸墊。 本發明之另一較佳實施例提出一種薄膜電晶體陣列基 板的製造方法，使用四道光罩製程，即可完成晝素電極及 驅動電晶體的製造。四道光罩製程分別包括：在第一道光 罩製程定義出閘極及訊號電極，接著，依序沉積介電層及 8 1290372 半導體層；接著，以第二道光罩製程定義出通道區。其中， 介電層的㈣可則物為氮切或氮氧切，半導體層的 材料可以例如為多晶矽或非晶矽。 接著’再沉積一絕緣保護層於所有元件結構之上，並 以第二道光罩製程在通道區上定義出源/汲極接觸窗、訊號 電極接觸窗以分別暴露出通道區及訊號電極的表面。接 著，實施一離子佈植以在暴露出的通道區表面形成歐姆接 觸。接著沉積透明導體層，並以第四道光罩製程定義出源/ 汲極、晝素電極、訊號電極（資料線）接觸墊。 因此，運用本發明所揭露之薄膜電晶體陣列基板的製 造方法具有下列優點：（1)可僅使用四道光罩；（2)採用 離子佈植以在通道區表面形成歐姆接觸，無須使用金屬層 或是矽化金屬層來形成歐姆接觸層；雖有使用半調式 (half-tone)光罩來進行曝光以及進行後續的顯影步驟，但可 避免習知在同一小區域形成兩種不同光阻高度，因此並無 習知需嚴格控制光阻角度和光阻凹陷區域（光阻厚度較薄 處）光阻厚度的困難；（4)形成電晶體陣列之通道區島結 構，元件通道區域無蝕刻過程之破壞，使元件保有良好的 特性，在半體層成膜厚度也可降低，不但可減少光電流產 生，也可降低成膜時電漿之破壞，提升元件特性；利用 透明導電膜橋接晝素電極與訊號電極，可把通道區之半導 體層内縮於閘極電極内，使半導體通道區的長度小於該閘 極結構的寬度’利用閘極阻擋背光源，降低照光後之光電 流產生。（6)可降低製造成本。 1290372 【實施方式】 請參照第3圖，第3圖係繪示依照本發明一較佳實施 例以四道光罩製程形成之電晶體陣列基板部分（晝素單元 結構）俯視示意圖。電晶體陣列基板包括閘極線（掃描線） 10、訊號線或訊號電極（資料線）2〇、閘極電極3〇、書素 電極40、通道區50以及源/汲極電極6〇和7〇。 請參照第4A圖至第4D圖，第4A圖至第4D圖係沿第 3圖之1-1’剖面線所示，以四道光罩製程形成之電晶體陣列 基板製造流程之剖面示意圖。請參照第4人圖，在一透明基 板200之上’以-道光罩製程定義一導體層而形成閘極電 極30及閘極線（掃描線）（未繪示）。透明基板2〇〇可以例 如為玻璃基板；導體層的材質可以例如為鋁、鉬、銅、鉻 及其任意組合所形成之合金及氮化金屬所组成之族群。導 體層可以為前述材質所形成之單層或多層結構。接著，在 透明基板200及閘極電極30上方依序沉積閘介電層2〇4、 半導體層206和導體層208,其中閘介電層2〇8的材質可以 例如為氮化矽、氮氧化矽或是氧化矽；半導體層2〇6的材 質可以例如為非晶矽或是多晶矽。而形成導體層2〇8的材 質可以例如為鋁、鉬、銅、鉻及其任意組合所形成之合金、 氮化金屬及矽化金屬所組成之族群。 凊繼續參見第4A圖’在導體層208上方形成以半調式 光罩曝光顯影的光阻層210。在閘極電極3〇的上方的光阻 層210的厚度較薄而位於欲形成訊號電極的上方的光阻層 210的厚度較厚。 明接著參照第4B圖’運用乾姓刻或濕姓刻製程，移除 1290372 第4A圖中未為光阻層210所覆蓋之導體層2〇8和 206而留下如第4B圖所示之半導體層206a、206b 層208a、208b以完成通道區及訊號電極（資料線） 區（pixel area)(未繪示）的定義。整個蝕刻製程可板嘷所 需#刻材質的變化而改變蝕刻劑的組成，例如，在本實施 例中可先以SFe/Cb為蝕刻劑來移除第4A圖中暴露出來的 導體層208及以SF^/O2為#刻劑來移除半導體層206。 請繼續參見第4B圖，可以例如〇2為蝕刻劑來移除第 4A圖中之部分光阻層21〇。由於閘極電極3〇的上方的光阻 層210厚度較薄，而導體層2〇8b的上方的光阻層21〇厚度 較厚，因此，閘極電極30的上方的光阻層21〇被完全移除， 而導體層208b的上方仍會具有光阻層21〇a。接著，以光阻 結構210a為罩幕，以SIVC12為蝕刻劑來移除第4B圖中的 導體層208a而形成第3圖中之通道區50。接著，去除光阻 層210a。半導體層2〇6b和導體層2〇肋構成第3圖中之訊 號線或訊號電極（資料線）2〇。 如第4C圖所示，形成一絕緣保護層212覆蓋閘介電層 204、通道區50及訊號線或訊號電極（資料線）2〇。以一 第三道光罩製程微影蝕刻絕緣保護層212而在通道區5〇上 及訊號電極（資料線）2〇上之絕緣保護層212形成接觸窗 220及222。接觸窗22〇及222分別暴露出通道區％及訊 ，電極（k料線）20的部份上表面。之後進行一離子佈植 製程214而在接觸窗220所暴露出之通道區50的上表面形 成歐姆接觸區域216。 如第4D圖所示，形成共形的透明導體層218於透明基 11 1290372 板200上方的結構之上，並填入接觸窗22〇及222。透明導 體層218的材料可以例如為銦錫氧化物、銦鋅氧化物、錄 鋅氧化物、氧化銦或是氧化錫。以一第四道光罩製程對透 明導體層218進行微影及蝕刻製程以定義出第3圖所示之 源/沒極電極60和70以及晝素電極40而完成第3圖所示 之畫素單元結構。 請參照第5圖，第5圖係繪示依照本發明另一較佳實 施例以四道光罩製程形成之電晶體陣列基板部分（書素單 π結構）俯視示意圖。電晶體陣列基板包括閘極線（掃描 線）10訊说線或訊號電極（資料線）20、閘極電極30、 晝素電極40、通道區50以及源/汲極電極6〇和7〇。訊號 線或訊號電極（資料線）20為閘極線（掃描線）所分斷， 藉由一從源/汲極電極70所延伸出來之導線8Q經接觸窗 308而電性連接兩兩被閘極線（掃描線）1〇所分斷之訊號 線或訊號電極（資料線）20。 請參照第6A圖至第6C圖，第6A圖至第6C圖係沿第 5圖之ΙΙ_ΙΓ剖面線所示，以四道光罩製程形成之電晶體陣 列基板製造流程之剖面示意圖。請參照第6Α圖，在一透明 基板200之上，以第一道光罩製程定義一導體層而形成閘 極電極30以及閘極線（掃描線）（未繪示）。透明基板3〇〇 可以例如為玻璃基板；導體層的材質可以例如為鋁、鉬、 銅、鉻及其任意組合所形成之合金及氮化金屬所組成之族 群。導體層可以為前述材質所形成之單層或多層結構。接 著，在透明基板300、閘極電極30及訊號電極（資料線） 20上方依序沉積閘介電層304及半導體層（未繪示），其中 12 Ϊ290372 閑介電層304的材質可以例如為氮化矽、氮氧化矽或是氧 化石夕；半導體層的材質可以例如為非晶石夕或是多晶石夕。請 繼續參見第6A圖，以第二道光罩製程定義半導體層而形成 通道區50。 請接著參照第6B圖，形成一絕緣保護層310覆蓋閘介 電層304、通道區50。以一第三道光罩製程微影蝕刻通道 區50上方之絕緣保護層31〇以及訊號電極（資料線）2〇 上方之絕緣保護層310和閘介電層304而在通道區50上之 絕緣保護層310形成接觸窗306以及在訊號電極（資料線） 20上方之絕緣保護層31〇和閘介電層304内形成接觸窗 308。接觸窗搭接孔3〇6及3〇8分別暴露出通道區5〇及訊 號電極（資料線）20的上表面。 接著，進行一離子佈植製程314而在接觸窗306所暴 路出之通道區50的上表面形成歐姆接觸區域312。 如第6C圖所示，形成共形的透明導體層316於透明基 板200上方的結構之上並填入接觸窗3〇6及3〇8。透明導體 層316的材料可以例如為銦錫氧化物、銦鋅氧化物、銘辞 氧化物、氧化銦或是氧化錫。以一第四道光罩製程對透明 導體層316進行微影及蝕刻製程以定義出第5圖所示之源/ 汲極電極60和70以及畫素電極40而完成第5圖所示之晝 素單元結構。 由上述本發明較佳實施例可知，應用本發明所揭露的 製造方法係使用四道光罩即可完成畫素電極及驅動電晶體 的製程。相較於習知製程而言，及使在依實施例中運=半 調式光罩，仍可以避免習知光阻層厚度及角度上控制的困 1290372 難，因而可使通道區能完全為閘極電極所遮蔽，而避免在 责光…、射下產生光電流。通道區表面形成歐姆接觸係採用 離子佈植的方式實施。因此，運用本發明所揭露的薄膜電 晶體陣列基板的製造方法，確實可以達成縮製程的減光罩 數、提升元件特性以及降低製造成本的目的。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍内，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 ▲為讓本發明之上述和其他目#、特徵、優點與實施例 月&更明顯易懂，所附圖式之詳細說明如下： 第1圖係緣示傳統四道光罩製程所形成之薄膜電晶體 陣列基板剖面示意圖； 第2圖係繪示習知製程中縮減使用光罩數目的關鍵步 驟的剖面示意圖； 第3圖係繪示依照本發明一較佳實施例以四道光罩製 程形成之電晶_列基板部分（畫素單元結構）俯視 、第4A圖至第4D圖係沿第3圖之w，剖面線所示，以 四道光罩製程形成之電晶體陣列基板製造流程之剖面示意 圖； 〜 第5圖係緣示依照本發明-較佳實施例以四道光罩製 1290372 程形成之電晶體陣列基板部分（晝素早元結構）俯視不意 圖；以及 第6A圖至第6C圖係沿第5圖之ΙΙ-ΙΓ剖面線所示，以 四道光罩製程形成之電晶體陣列基板製造流程之剖面示意 圖。 【主要元件符號說明】 10 :閘極線（掃描線） 20 :訊號線或訊號電極（資料線） 30 :閘極電極 40 :晝素電極 50 :通道區 60、70 :源/汲極電極 100 :玻璃基板 104、204、304 :介電層 106、206、206a、206b :半導體層 108 :歐姆接觸層 110 :電極層 112、210、210a :光阻層 114、212、310 :絕緣保護層 116 :背光 200、300 :透明基板 208、208a、208b :導體層 214、314 :離子佈植 216、312 :歐姆接觸區域 218、316:透明導體層SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method of fabricating a thin film transistor array earth plate, which can be completed by using four masks to complete the process of the halogen electrode and the driving transistor. Another object of the present invention is to provide a method for manufacturing a thin film transistor array substrate, which can greatly reduce the manufacturing cost and make the product more competitive. Another object of the present invention is to provide a thin film transistor array substrate. The manufacturing method can effectively avoid the occurrence of photocurrent in the channel region. A further object of the present invention is to provide a method for fabricating a thin film transistor array substrate, which can form an ohmic contact layer on the surface of the channel region by ion implantation. Still another object is to provide a method of fabricating a thin film transistor array substrate, which can utilize a halftone mask to reduce the number of masks used, and avoid the difficulty in controlling the thickness and angle of the conventional photoresist layer. OBJECTS OF THE INVENTION A preferred embodiment of the present invention provides a method for fabricating a thin film transistor array substrate, which is capable of fabricating a halogen electrode and a driving transistor using a four-pass mask 7 1290372. The four mask processes include · Define the gate in the first mask process, and then deposit the dielectric layer, semiconductor layer and conductor sequentially Layer; then, the channel region and the signal electrode are defined by the second mask process. The second mask process is performed by using a halftone mask, with a half-tone gray level exposure dose distribution pair The photoresist layer is exposed and developed to define different photoresist layer thicknesses in the channel region and the signal electrode region to be formed, wherein the thickness of the photoresist layer in the region where the signal electrode is to be formed is the thickest, and the thickness of the photoresist layer in the channel region is second. The other areas are fully open areas of the photoresist. After the definition of the channel region and the signal electrode is completed by different etching (dry etching or wet etching process), the photoresist layer above the channel region is removed to expose the conductor layer. The photoresist layer above the electrode is thicker, and a photoresist layer having a certain thickness is still located above the signal electrode. Then, the conductor layer on the channel region is removed by an etching process, wherein the material of the dielectric layer may be, for example, nitrogen. In the case of fossil or oxynitride, the material of the semiconductor layer may be, for example, polycrystalline or amorphous. Next, an insulating protective layer is deposited on all components. Above the structure, a source/drain contact window and a signal electrode contact window are defined on the channel region by a third mask process to expose the channel region and the surface of the signal electrode, respectively. Then, an ion implantation is performed to expose An ohmic contact is formed on the surface of the exit channel region. Then, a transparent conductor layer is deposited, and a source/no-pole, pixel electrode, signal electrode (data line) contact pad is defined by a fourth mask process. Another preferred embodiment of the present invention A method for fabricating a thin film transistor array substrate is described. The fabrication of a halogen electrode and a driving transistor can be completed by using four mask processes. The four mask processes include: defining a gate in the first mask process and a signal electrode, followed by sequentially depositing a dielectric layer and a layer of 8 1290372 semiconductor; then, defining a channel region by a second mask process, wherein the (four) of the dielectric layer is a nitrogen cut or a oxynitride, a semiconductor layer The material may be, for example, polycrystalline germanium or amorphous germanium. Then, an insulating protective layer is deposited over all of the component structures, and a source/drain contact window and a signal electrode contact window are defined on the channel region by a second mask process to expose the channel region and the surface of the signal electrode, respectively. . Next, an ion implantation is performed to form an ohmic contact on the exposed surface of the channel region. A transparent conductor layer is then deposited, and the source/drain electrodes, the halogen electrodes, and the signal electrodes (data lines) contact pads are defined by a fourth mask process. Therefore, the manufacturing method of the thin film transistor array substrate disclosed by the present invention has the following advantages: (1) only four photomasks can be used; (2) ion implantation is used to form an ohmic contact on the surface of the channel region without using a metal layer Or deuterium metal layer to form an ohmic contact layer; although a half-tone mask is used for exposure and subsequent development steps, it is possible to avoid the formation of two different photoresist heights in the same small area. Therefore, there is no known difficulty in strictly controlling the photoresist angle and the photoresist thickness of the photoresist recessed region (thickness of the photoresist); (4) forming the channel region island structure of the transistor array, and the component channel region is not destroyed by the etching process. In order to maintain good characteristics of the component, the film thickness can also be reduced in the half layer, which not only reduces the generation of photocurrent, but also reduces the destruction of the plasma during film formation, improves the characteristics of the device; bridges the pixel electrode and signal with a transparent conductive film. The electrode can shrink the semiconductor layer of the channel region into the gate electrode, so that the length of the semiconductor channel region is smaller than the width of the gate structure Barrier backlight, illumination of the photoelectric reduced flow generation. (6) The manufacturing cost can be reduced. 1290372 [Embodiment] Referring to FIG. 3, FIG. 3 is a top plan view showing a portion of a transistor array substrate (a cell structure) formed by a four-mask process according to a preferred embodiment of the present invention. The transistor array substrate includes a gate line (scanning line) 10, a signal line or a signal electrode (data line) 2A, a gate electrode 3A, a pixel electrode 40, a channel region 50, and source/drain electrodes 6A and 7 Hey. Referring to Figs. 4A to 4D, Figs. 4A to 4D are cross-sectional views showing a manufacturing process of a transistor array substrate formed by a four-mask process as shown by a 1-1' hatching in Fig. 3. Referring to the fourth figure, a conductor layer is defined by a reticle process on a transparent substrate 200 to form a gate electrode 30 and a gate line (scanning line) (not shown). The transparent substrate 2 can be, for example, a glass substrate; the material of the conductor layer can be, for example, an alloy composed of aluminum, molybdenum, copper, chromium, and any combination thereof, and a metal nitride. The conductor layer may be a single layer or a multilayer structure formed of the foregoing materials. Next, a gate dielectric layer 2〇4, a semiconductor layer 206, and a conductor layer 208 are sequentially deposited over the transparent substrate 200 and the gate electrode 30. The material of the gate dielectric layer 2〇8 may be, for example, tantalum nitride or oxynitride. Niobium or tantalum oxide; the material of the semiconductor layer 2〇6 may be, for example, an amorphous germanium or a polycrystalline germanium. The material forming the conductor layer 2 〇 8 may be, for example, an alloy composed of aluminum, molybdenum, copper, chromium, or any combination thereof, a metal nitride, and a metal halide.凊Continuing to refer to FIG. 4A', a photoresist layer 210 exposed and developed in a halftone mask is formed over the conductor layer 208. The thickness of the photoresist layer 210 above the gate electrode 3 is thin and the thickness of the photoresist layer 210 located above the signal electrode is thick. Next, referring to FIG. 4B, the dry conductor or wet etching process is used to remove the conductor layers 2〇8 and 206 which are not covered by the photoresist layer 210 in FIG. 4A and leave as shown in FIG. 4B. The layers 208a, 208b of the semiconductor layers 206a, 206b define the channel region and the signal electrode (not shown). The entire etching process can change the composition of the etchant by changing the required material. For example, in the embodiment, the exposed conductor layer 208 in FIG. 4A can be removed by using SFe/Cb as an etchant. The semiconductor layer 206 is removed with SF^/O2 as the #刻刻. Continuing to refer to FIG. 4B, a portion of the photoresist layer 21A of FIG. 4A can be removed, for example, by using 〇2 as an etchant. Since the photoresist layer 210 above the gate electrode 3 is thinner and the photoresist layer 21 above the conductor layer 2〇8b is thicker, the photoresist layer 21 above the gate electrode 30 is thinned. It is completely removed, and the photoresist layer 21〇a is still present above the conductor layer 208b. Next, the channel region 50 in Fig. 3 is formed by using the photoresist structure 210a as a mask and removing the conductor layer 208a in Fig. 4B with SIVC12 as an etchant. Next, the photoresist layer 210a is removed. The semiconductor layer 2〇6b and the conductor layer 2 ribs constitute the signal line or signal electrode (data line) 2〇 in Fig. 3. As shown in FIG. 4C, an insulating protective layer 212 is formed to cover the gate dielectric layer 204, the channel region 50, and the signal line or signal electrode (data line). Contact windows 220 and 222 are formed by a third mask process lithography etch protection layer 212 on the channel region 5 and the insulating layer 212 on the signal electrodes (data lines). The contact windows 22 and 222 respectively expose a portion of the upper surface of the channel region and the electrode (k-line) 20. An ion implantation process 214 is then performed to form an ohmic contact region 216 on the upper surface of the channel region 50 exposed by the contact window 220. As shown in FIG. 4D, a conformal transparent conductor layer 218 is formed over the structure above the transparent substrate 11 1290372 plate 200 and filled into contact windows 22 and 222. The material of the transparent conductor layer 218 may be, for example, indium tin oxide, indium zinc oxide, zinc oxide, indium oxide or tin oxide. The transparent conductor layer 218 is subjected to a lithography and etching process by a fourth mask process to define the source/dot electrodes 60 and 70 and the pixel electrode 40 shown in FIG. 3 to complete the pixel shown in FIG. Unit structure. Referring to FIG. 5, FIG. 5 is a top plan view showing a portion of a transistor array substrate (book element π structure) formed by a four-mask process according to another preferred embodiment of the present invention. The transistor array substrate includes a gate line (scanning line) 10 signal line or signal electrode (data line) 20, a gate electrode 30, a halogen electrode 40, a channel region 50, and source/drain electrodes 6A and 7A. The signal line or signal electrode (data line) 20 is separated by a gate line (scanning line), and is electrically connected to each other by a contact wire 309 extending from the source/drain electrode 70 via the contact window 308. The signal line or signal electrode (data line) 20 that is separated by the pole line (scanning line). Referring to Figs. 6A to 6C, Figs. 6A to 6C are schematic cross-sectional views showing a manufacturing process of a transistor array substrate formed by a four-mask process as shown by the ΙΙ_ΙΓ line of Fig. 5. Referring to Figure 6, a conductor layer is defined on a transparent substrate 200 by a first mask process to form a gate electrode 30 and a gate line (scanning line) (not shown). The transparent substrate 3 〇〇 may be, for example, a glass substrate; the material of the conductor layer may be, for example, an alloy composed of aluminum, molybdenum, copper, chromium, or any combination thereof, and a metal nitride. The conductor layer may be a single layer or a multilayer structure formed of the aforementioned materials. Next, a gate dielectric layer 304 and a semiconductor layer (not shown) are sequentially deposited over the transparent substrate 300, the gate electrode 30, and the signal electrode (data line) 20. The material of the 12 Ϊ 290372 idle dielectric layer 304 can be, for example, Niobium nitride, niobium oxynitride or oxidized oxide; the material of the semiconductor layer may be, for example, amorphous or polycrystalline. Continuing to refer to Figure 6A, the semiconductor layer is defined by a second mask process to form the channel region 50. Referring to FIG. 6B, an insulating protective layer 310 is formed to cover the gate dielectric layer 304 and the via region 50. Insulation protection on the channel region 50 by a third mask process lithography etching the insulating layer 31 above the channel region 50 and the insulating protective layer 310 and the gate dielectric layer 304 above the signal electrode (data line) 2 Layer 310 forms contact window 306 and a contact window 308 is formed in insulating protective layer 31 and signal dielectric layer 304 over signal electrode (data line) 20. The contact window lap holes 3〇6 and 3〇8 expose the upper surface of the channel region 5〇 and the signal electrode (data line) 20, respectively. Next, an ion implantation process 314 is performed to form an ohmic contact region 312 on the upper surface of the channel region 50 where the contact window 306 exits. As shown in Fig. 6C, a conformal transparent conductor layer 316 is formed over the structure above the transparent substrate 200 and filled in contact windows 3〇6 and 3〇8. The material of the transparent conductor layer 316 may be, for example, indium tin oxide, indium zinc oxide, inscription oxide, indium oxide or tin oxide. The transparent conductor layer 316 is subjected to a lithography and etching process in a fourth mask process to define the source/drain electrodes 60 and 70 and the pixel electrode 40 shown in FIG. 5 to complete the pixel shown in FIG. Unit structure. According to the preferred embodiment of the present invention described above, the manufacturing method disclosed in the present invention can complete the process of the pixel electrode and the driving transistor by using four masks. Compared with the conventional process, and in the embodiment, the half-tone mask can avoid the difficulty of controlling the thickness and angle of the photoresist layer 1290372, so that the channel region can be completely the gate electrode. Obscured, and avoiding the blame..., shooting produces photocurrent. An ohmic contact system formed on the surface of the channel region is implemented by ion implantation. Therefore, by using the method for manufacturing a thin film transistor array substrate disclosed in the present invention, it is possible to achieve the object of reducing the number of dimming masks, improving the characteristics of the elements, and reducing the manufacturing cost. Although the present invention has been described above in terms of a preferred embodiment, it is not intended to limit the invention, and it is obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS In order to make the above and other objects, features, advantages and embodiments of the present invention more obvious and easy to understand, the detailed description of the drawings is as follows: Fig. 1 shows the conventional four-way light Schematic diagram of a thin film transistor array substrate formed by a mask process; FIG. 2 is a schematic cross-sectional view showing a key step of reducing the number of masks used in a conventional process; FIG. 3 is a schematic view showing a preferred embodiment of the present invention The electro-crystal formed by the four mask processes _ column substrate portion (pixel unit structure) is viewed from the top, and the 4A to 4D patterns are along the w of FIG. 3, and the transistor array is formed by a four-mask process as shown by the hatching. FIG. 5 is a cross-sectional view showing a portion of a transistor array substrate (former elementary structure) formed by a four-mask reticle 1290372 process in accordance with the present invention - a preferred embodiment; and FIG. 6A 6C is a schematic cross-sectional view showing a manufacturing process of a transistor array substrate formed by a four-mask process as shown in the ΙΙ-ΙΓ cross-section of FIG. [Main component symbol description] 10: Gate line (scanning line) 20: Signal line or signal electrode (data line) 30: Gate electrode 40: Alizarin electrode 50: Channel area 60, 70: Source/drain electrode 100 : Glass substrate 104, 204, 304: dielectric layer 106, 206, 206a, 206b: semiconductor layer 108: ohmic contact layer 110: electrode layer 112, 210, 210a: photoresist layer 114, 212, 310: insulating protective layer 116 : backlights 200, 300: transparent substrates 208, 208a, 208b: conductor layers 214, 314: ion implants 216, 312: ohmic contact regions 218, 316: transparent conductor layers