CN108886073A - Vertical solid-state devices - Google Patents
Vertical solid-state devices Download PDFInfo
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- CN108886073A CN108886073A CN201680076089.7A CN201680076089A CN108886073A CN 108886073 A CN108886073 A CN 108886073A CN 201680076089 A CN201680076089 A CN 201680076089A CN 108886073 A CN108886073 A CN 108886073A
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Led Devices (AREA)
Abstract
Vertical current-mode solid-state devices includes connection pad and side wall, wherein side wall includes metal-insulator semiconductor (MIS) structure, wherein the leakage current effects of vertical device are limited by making MIS structure bias via side wall.
Description
Cross reference to related applications
This application claims the Canadian Patent Application No. 2,916,291 submitted on December 24th, 2015 and in 2016
The priority of the Canadian Patent Application No. submitted March 18 2,924,157, each of above-mentioned Canadian patent application are logical
Reference is crossed to be totally integrating herein with it.
Technical field
The present invention relates to vertical solid-state devices, the cross conduction manipulation of vertical solid-state devices and its manufacturing method.The present invention
Further relate to the manufacture of the integrated array of microdevice.The array of micro- device device is by the contact battle array in device substrate or system substrate
Column limit.
Background technique
Integrated into system substrate of microoptoelectronic device can provide high-performance and H.D system.In order to improve into
The device of this and creation more high pixel density, the size of photoelectric device should be reduced.The example of opto-electronic device be sensor and
Luminescent device (for example, light emitting diode (LED)).However, with these devices size reduce, device performance may start by
Damage.Performance decline some reasons include but is not limited to due to defect cause higher leakage current, the charge of interface it is crowded, lose
Weigh charge and undesirable compound such as Auger and non-radiative recombination.
Light emitting diode (LED) and LED array can be classified as vertical solid-state devices.Microdevice can be sensor, shine
Any other solid state device of diode (LED) or on substrate growth, deposition or monolithic manufacture.Substrate can be oneself of device layer
Right substrate or device layer make solid-state devices be transferred to receiver substrate thereon.
System substrate can be any substrate, and can be rigidity or flexible.System substrate can be by glass, silicon, plastics
Or any other common used material is made.System substrate can also have active electronic component, such as, but not limited to transistor, resistance
Device, capacitor or any other electronic component being usually used in system substrate.In some cases, system substrate can be for electricity
The substrate of signal row and column.In an example, device substrate can be precious for the indigo plant of the LED layer with monolithic growth on top of this
Stone lining bottom, and system substrate can be the backboard with circuit to be driven to miniature LED component.One as vertical device
Part, metal-insulator semiconductor (MIS) structure can be formed by metal layer, spacer material layer and semiconductor material layer.
Device layer is shifted can be used for and is engaged to system substrate by various transfers and joint method.In an example,
Heat and pressure can be used for engaging device layer to system substrate.Electric current flowing master in vertical solid-state devices, on vertical direction
Define the function of device.Light emitting diode (LED) can be classified as vertical solid-state devices.Here, the manufacturing method proposed
It is used to limit the transverse current flowing of these devices.
LED pattern can be brought into some problem into microsized device with the LED array that creation is used for display application,
These problems include the generation of stock utilization, limited PPI and defect.In an example, it in vertical solid-state devices, erects
The function of the upward electric current flowing main definitions device of histogram.Remain the need for improved vertical solid-state devices
It asks.
Present context information be for make applicant believes that Given information become can purpose related to the present invention and provide
's.It is not necessarily intended to recognize, any information being also not necessarily to be construed as in aforementioned information is constituted for of the invention existing
Technology.
Summary of the invention
The purpose of the present invention is to provide the vertical solid-state devices with directional current.
Vertical current-mode solid-state devices is provided on the one hand comprising connection pad and side wall, wherein side wall includes
Metal-insulator semiconductor (MIS) structure, wherein the leakage current effects of vertical device are by making MIS structure bias via side
Wall limits.
In embodiments, device is connected to circuit layer by least one connection pad.
In another embodiment, electric current is shunted from the periphery of vertical device.
In another embodiment, device is miniature LED component.
Provide in another aspect solid-state devices comprising current mode device array, wherein current mode device array
In the continuous semiconductor piece by the resistance engineering development of at least one conducting shell.
In embodiments, connection pad changes resistance and limits the size of independent vertical device.
In another embodiment, resistance engineering includes being etched at least one conducting shell.
In another embodiment, resistance engineering include at least one conducting shell carry out measurement change, modulation or its
Combination.
In another embodiment, device is miniature LED component.
In another embodiment, mask for changing at least one conducting shell lateral resistance.
In another embodiment, the resistance of conducting shell is changed by aoxidizing.
Provide in another aspect the method for manufacturing vertical solid-state devices, wherein the method includes generating vertical device
Array, wherein each vertical device includes connection pad and side wall, wherein side wall includes metal-insulator semiconductor (MIS)
Structure, wherein the leakage current effects of vertical device are limited by making MIS structure bias via side wall.
In embodiments, this method further includes that device is connected to circuit layer by least one connection pad.
In another embodiment, the resistance of conducting shell is changed by aoxidizing.
In another embodiment, vertical solid-state devices is generated before device is transferred to system substrate.
In another embodiment, vertical solid-state devices is generated after being transferred to system substrate.
In another embodiment, vertical solid-state devices is partly generated before device is transferred to system substrate,
And vertical solid-state devices is completed after device is transferred to system substrate.
On the other hand the method for manipulating the top conduction layers of vertical device is provided, wherein the function of period is by vertical electricity
Current limit, this method include：Top-layer resistance engineering, the thickness or ratio that wherein the lateral resistance of top conduction layers passes through change top layer
Resistance manipulates；The complete or partial etching modulation of the top layer of vertical device；And conductivity of materials modulation, the wherein electricity of top layer
Resistance is modulated.
In embodiments, conductivity of materials modulation is realized by etching, compensating doping, laser ablation or combinations thereof.
In another embodiment, the modulation of vertical device is by adding metal (electrode)-insulator-semiconductor (MIS)
It is added at least one surface of vertical device and executes.
In another embodiment, vertical device is opto-electronic device.
On the other hand the method for pixellated display part is provided, the method includes：Pixel pad is limited on backboard
Connection；And the LED component of no current spreader or patterned current spreader layer is attached to backboard.
In embodiments, joint element is used to LED component remaining to backboard.
On the other hand the method redirected to the electric current in the current driving apparatus including side wall, the side are provided
Method includes：Device is directed current to by connecting pad；And field is generated using metal-insulator semiconductor to eliminate
Leakage current in side wall.
It provides in another aspect by limiting current to the next life in the selected region of blocky current driving device
At the method for vertical device array.
Detailed description of the invention
Read following detailed description and referring to attached drawing after, the foregoing and other advantages of the disclosure will become it is aobvious and
It is clear to.
Figure 1A shows the example of the opto-electronic device at least two terminals.
Figure 1B shows the example of the opto-electronic device on at least side of device with MIS structure.
Fig. 1 C shows one view in the functional electrode of the device with MIS structure on another side.
Fig. 2A shows the exemplary embodiment party of the technique for forming MIS structure on device before the off process
Formula.
Fig. 2 B shows the example of the technique for forming MIS structure on microdevice before the off process and later
Property embodiment.
Fig. 2 C shows the exemplary embodiment party of the technique for forming MIS structure on device after shifting process
Formula.
Fig. 3 shows the transferred microdevice in system substrate with negative slope.
Fig. 4 A shows the transferred microdevice in system substrate with positive slope.
Fig. 4 B shows formation of the different MIS structures on transferred microdevice.
Fig. 4 C shows passivation or the formation of planarization layer and passivation or planarization layer pattern is used for electrode to be formed
The opening of connection.
Fig. 4 D shows deposition of the electrode on device.
Fig. 5 A shows the embodiment for forming different MIS structures on device before branching program.
Fig. 5 B shows the device with the MIS structure being transferred in system substrate and is used to couple device and MIS
Different methods on to electrode or circuit layer.
Fig. 6 A shows another embodiment for forming different MIS structures on device before branching program.
Fig. 6 B shows the device with the MIS structure being transferred in system substrate and is used to couple device and MIS
Different methods on to electrode or circuit layer.
Fig. 7 A shows the schematic diagram for showing the vertical solid-state devices of top layer of transverse current component and part etching.
Fig. 7 B shows the device of the top layer with part etching and the schematic diagram of top layer modulation.
Fig. 7 C shows the schematic diagram of the vertical device with top conduction modulating layer.
Fig. 7 D shows the schematic diagram of the device layer with nanowire structure.
Fig. 7 E shows the cross-sectional view of the MIS structure around contact layer.
Fig. 8 A schematically shows traditional gallium nitride (GaN) LED component.
Fig. 8 B shows the manufacturing process of LED and integrating for device substrate and the microdevice that is limited by top contacts
Technique and substrate to system substrate engagement.
Fig. 8 C shows the LED wafer structure limited by top contacts.
Fig. 8 D shows the LED wafer structure limited by the p layer of top contacts and part etching.
Fig. 8 E shows the LED wafer structure limited by top contacts and p layers of laser-induced thermal etching.
Fig. 9 A shows the LED wafer with the common transparent n contact for being joined to back board structure.
Fig. 9 B shows the integrated device with the microdevice limited by the top contacts for being joined to system substrate and serves as a contrast
Bottom.
Fig. 9 C shows the LED wafer with buffer layer and metal n contact through hole.
Fig. 9 D shows the example of the transferred LED wafer with patterning n-layer.
Fig. 9 E shows the integrated device with the microdevice limited by the top contacts for being joined to system substrate and serves as a contrast
Bottom.
Fig. 9 F, which is shown, to be had by being joined to the top contacts of system substrate and being formed between adjacent microdevice
Optical element limit microdevice integrated device substrate.
Fig. 9 G shows the example of the transferred LED wafer with patterned n-layer and light regime scheme.
Fig. 9 H shows the device stacked with partition method.
Figure 10 A shows the integrated technique of device substrate and system substrate.
Figure 10 B shows the integrated technique of device substrate and system substrate.
Figure 10 C shows the integrated device substrate for shifting and being joined to system substrate.
Figure 10 D shows the integrated morphology for having transferred device layer and joint element in the edge of backboard.
Figure 10 E shows the integrated work of engagement patterning and public electrode carry out after device substrate and system substrate
Skill.
Figure 10 F shows engagement patterning, optical element and public electrode after and forms the device substrate and system carried out
The integrated technique of substrate.
Figure 11 shows the process flow chart of the wafer etching process formed for mesa structure.
Figure 12 A shows device on the wafer surface with dielectric deposition.
Figure 12 B shows dielectric layer and is etched away in this layer of upper opening that generates with the device for subsequent crystal round etching
Part.
Figure 12 C shows the mesa structure after wafer substrate etching step.
Figure 13 shows the process flow chart for being used to form MIS structure.
Figure 14 A shows the dielectric and metal layer for being deposited on and forming MIS structure on mesa structure.
Figure 14 B shows the wafer with the pattern formed using lithography step.
Figure 14 C shows the wafer with the dielectric layer using fluorine chemistry dry etching.
Figure 14 D shows the wafer with the second dielectric layer.
Figure 14 E shows the wafer with ohm p-contact part.
Specific embodiment
Unless otherwise defined, all technical and scientific terms used herein have and technology belonging to the present invention
The identical meaning of the normally understood meaning of the those of ordinary skill in field.
Unless the context clearly indicates otherwise, otherwise singular " one as used in specification and claims
(a) ", " one (an) " and " being somebody's turn to do (the) " includes plural reference.
Wording " comprising " as used in this article be understood to mean that following list be it is non-in detail and can
To include or can not include any other additional suitable items, optionally for example one or more other features, portion
Part and/or element.
Wording " device " and " microdevice " and " opto-electronic device " use interchangeably herein.The technology of this field
Personnel will be clear that embodiment described herein is unrelated with device size.
Wording " donor substrate " and " temporo substrate " use interchangeably herein.However, those skilled in the art should be clear
Chu, embodiment described herein are unrelated with substrate.
Wording " system substrate " and " receiver substrate " are used interchangeably herein.However, those skilled in the art answer
Clear, embodiment described herein is unrelated with substrate type.
The present invention relates to the methods that the cross conduction for vertical solid-state devices (especially opto-electronic device) manipulates.More
Body, this disclosure relates to miniature or nano photoelectronic devices, wherein the performance of device is influenced by size reduction.It also describes
The method that the array of vertical device is generated by modification cross conduction in the case where active layer not being isolated.Using vertical
The LED array of conduction engineering technology can realize that the electric current in horizontal direction transmits, and be controlled to pixel region, therefore be not required to
LED is patterned.
The method of LED structure modification is also described herein, and this method is in retainer member efficiency and uniformity
Simplify the integrated of in light-emitting diode display single chip LED device and back plane circuitry simultaneously.This method and obtained structure increase
The quantity of the LED component manufactured in limited wafer area, and can lead to lower manufacturing cost, in the quantity of manufacturing step
Reduction and higher light-emitting diode display resolution ratio and brightness.LED component in substrate can be engaged to electronics backboard, should
Electronics backboard drives these devices or pixel with passive or active mode.Although with a type of LED component to following side
Method is explained, but they can easily be used together with other LED and the vertical device of non-LED (for example, sensor).Such as
LED component in substrate described herein can be engaged to electronics backboard, which is driven with passive or active mode
Move these devices (pixel).
The method that improves the performance of opto-electronic device is also described through the internal electric field of manipulation device herein.It is special
It is not that can improve the performance of these devices to the limitation of the transverse current flowing of vertical solid-state devices.In particular, to from vertical
The shunting of the electric current of device periphery can be realized by changing cross conduction.The resistance of conducting shell can be changed by aoxidizing, and be passed
The lateral resistance of conducting shell can be changed by changing bias condition.Contact also is used as mask, to change the transverse direction of conducting shell
Resistance.This device can also side with conducting shell and centre have functional layer.
It additionally provides by limiting pixel pad connection in backboard and there is the LED component of vertical conduction modulation to be attached
Make the method for display device pixelation to backboard.In one case, current spreader is removed or its thickness reduces to adjust
The vertical conduction of system.In another case, some in microdevice layer are etched away to generate vertical conduction modulation.Joint element
It can be used for device being fixed to bottom plate.Structures and methods are described for by the way that device layer to be transferred on receiver substrate
Contact pad is formed on device layer before to limit microdevice on device layer.It also describes for miniature what is integrated
The structures and methods of microdevice are limited on receiver substrate in device array system by contact pad or convex block, wherein
Integrated microdevice array system includes the transferred monolithic array of system substrate and microdevice.
Also describe the method for manipulating the top conduction layers of vertical device, wherein the function of device is mainly by vertical electric current
It limits, in one embodiment, this method includes：Top-layer resistance engineering, wherein the lateral resistance of top layer is by changing the layer
Thickness or specific resistance manipulate；Completely or partially etching modulation, wherein the top layer of vertical device by any etching means come
Modulation；And conductivity of materials modulation, wherein the resistance of top layer is by including but is not limited to etching, compensation doping and laser ablation
Various methods adjust.Contact pad on top device layer can limit the size of independent microdevice.In microdevice
Transfer after, public electrode can be deposited in the transferred monolithic array of microdevice to improve conductibility.Common electrical
Pole can the through-hole in the top buffer layer or dielectric layer in the monolithic array by shifting or being deposited on microdevice formed.And
And the top layer of the transferred monolithic array of microdevice can be modulated by any removal means.In this case, optics
Element is formed in the removed region of modulated top layer.
The method that microdevice array is formed in integrated morphology is also described, wherein the device prepared according to the above method
Layer is transferred to reception substrate, wherein the contact pad received on the top of substrate is engaged to device layer, and independent micro-
The size of type device is partly limited by the size of contact pad or convex block on receiver substrate.Spacer or dykes and dams can shapes
At the size for fully limiting microdevice around contact pad or convex block.Spacer around contact pad or convex block or
Dykes and dams can be adhesive to promote to engage device layer to receiver substrate.Herein, the top layer of integrated microdevice array
It is modulated by any removal means.In this case, optical element may be formed at the removed region of modulated top layer
In.
In embodiments, at least one metal-insulator semiconductor (MIS) structure is with a formation in device side
For semiconductor layer.The structure controls electric charge transfer and accumulation for manipulation device internal electric field.MIS structure can be mobile in device
It is formed before into system substrate or after device is formed in system substrate.Electrode in MIS structure can be it is transparent,
So that light passes through or electrode can be to be reflexive or opaque, to control the direction of light.Preferably, device, which exports, includes
For generating the visible light of pixel array in the display.Electrode in MIS structure can be with one in device function electrode altogether
It enjoys.Electrode in MIS structure can also have individual bias point.The input or output of microdevice can be any type of electromagnetism
Wave.The non-limiting example of the device is light emitting diode and sensor.It also describes herein for improving micro photo electric
The structures and methods of sub- device.Device performance is improved by manipulation internal electric field.In one case, MIS structure is used for
Modulate internal electric field.
In the microdevice system integration, device can be manufactured under the conditions of their primitive environment, then can be transferred
To system substrate.In order to encapsulate more microdevices in system substrate or reduce material cost, the size of microdevice should be use up
It may be small.In an example, microdevice is 25 μm or smaller, and is in another example 5 μm or smaller.Due to supplying
Initial devices and layer in body substrate are patterned as smaller area, so leakage and other influences increase device performance
It reduces.Although passivation can improve performance to a certain extent, it can not solve other problems, for example, non-radiative recombination.
Hereinafter it is described in detail to according to the various embodiments of this provided structure and technique.
Vertical device with metal-insulator semiconductor (MIS) structure
Described is to modulate the internal electric field of vertical device using MIS structure to lead to reduce by the reduction in size
The undesirable effect caused.In one embodiment, which is formed entirely in donor substrate or temporarily (temporal) lining
On device in bottom substrate and it is then moved to system substrate.In another case, MIS structure, which is formed in, is integrated in reception
On device on device or system substrate.In another case, before being integrated in receiver substrate, MIS structure part landform
At on device, and after device is transferred in receiver substrate, MIS structure is completed.
Figure 1A shows tool, and there are two the microdevices 100 of function contact A 102 and B 104.The bias of the device is led
Send a telegraph the major part that stream 106 passes through device 100.In the case of light-emitting devices, charge is compound in luminescent layer and generates light
Son.In the case where senser element, outside stimulus (such as light, chemistry, Tera Hz, X-ray etc.) modulates electric current.However, at this
In the case of two kinds, imperfection can all influence the efficiency of device 100.One example is the mainly leakage as caused by the defects of side wall
Electric current 108.Other imperfections can be non-radiative recombination, auger recombination, the crowded, charge imbalance of charge etc..With the ruler of device
Very little reduction, these problems become more to dominate.
Figure 1B shows using metal-insulator semiconductor (MIS) that modulate internal field some in these problems to reduce
Example.At least one MIS structure 110 is formed on a face of device.MIS structure passes through 112 bias of electrode.If MIS
Structure 110 is formed on more than one surface, then they can be continuous structure or several separated MIS structures.For all faces
Or different biass, electrode 112 may be connected to identical bias.
Fig. 1 C shows one view in the functional electrode 102 by microdevice 100.Herein, MIS structure 110
The device is surrounded in the form of one continuous.Leakage current 108 can be reduced and/or avoid in high current by being biased to MIS structure
Band bending under density to avoid non-radiative recombination and/or helps an enhancing charge balance in charge and electric current is avoided to gather around
It squeezes.Bias condition can be chosen so as to tackle the major problem.For example, leakage current is in the case where red light emitting diodes (LED)
Until the main source of loss in efficiency under low current density in.In this case, bias condition can block/reduce electric leakage
Stream, to significantly increase efficiency.In such as green LED in another case, auger recombination can be main problem.Bias condition
It is adjusted to reduce such compound.It should be noted that a kind of situation can be eliminated/be reduced by more than to a kind of bias condition.In addition,
Bias condition is dynamically adapted to obtain better performance.For example, at lower current densities, a kind of effect (such as leak electricity
Stream) it can be main effects, and under higher current density, charge is crowded and other problems can be main effects.Therefore, bias
It can be changed accordingly to provide better performance.Bias can be adjusted to that the entire battle array of individual devices or device cluster or device
Column.It can also be different for different devices.For example, can have for LED and sensor or red and green LED
There is different bias conditions.
The technique that MIS structure is formed on microdevice is described in Fig. 2A to Fig. 2 C.These steps in these techniques
Sequence can be changed in the case where not influencing final result.In addition, each step can be the combination of several lesser steps.
Fig. 2A shows an example of the technique.Firstly, forming microdevice 200.During the step 200, pass through
Patterning forms microdevice by selective growth.During step 202, so that device is prepared transfer, may include clear
It is clean or be moved to temporary substrates.During step 204, MIS structure is formed on a surface of device.During step 206,
So that device is prepared transfer, may include stripping technology, cleaning process and other steps.In addition, during the step 206, to being used for
Device function electrode or connection pad or electrode for MIS structure are deposited and/or are patterned.It, will during step 208
Selected device is transferred to receiver substrate.This can be carried out by various methods, these methods include but is not limited to pick and place
Or it directly shifts.In step 210, connector is formed for device and MIS structure.It, can will be other in addition, after shifting process
Optical layer and device are integrated into system substrate.
Fig. 2 B shows another example that the technique of MIS structure is formed on microdevice.Firstly, forming microdevice
200.During step 200, microdevice is formed by patterning or by selective growth.During step 202, make device
Part prepares transfer, may include cleaning or being moved to temporary substrates.During step 204-1, the shape on a surface of device
At a part of MIS structure, such as dielectric deposition and patterning.During step 206, device is made to prepare transfer, it can
Including stripping technology, cleaning process and other steps.In addition, during the step 206, to for device function electrode or being used for
The connection pad or electrode of MIS structure are deposited and/or are patterned.During step 208, selected device is transferred to
Receiver.This can be carried out by various methods, these methods include but is not limited to pick and place or directly shift.In step 204-2
Period completes MIS structure, may include the deposition and patterning of conducting shell.It is device and MIS structure shape during step 210
At connection.After shifting process, other optical layers and device can be integrated into system substrate.Step 210 can be and 204-2 phase
Same or different and/or independent steps.Other processing steps can also carry out between 204-2 and 210.In an example
In, passivation or planarization layer can be deposited and/or be patterned to prevent between MIS electrode and other connections before step 210
Short circuit.
Fig. 2 C shows another example that the technique of MIS structure is formed on microdevice.Firstly, forming microdevice
200.During the step 200, microdevice is formed by patterning or by selective growth.During step 202, make
Device prepares transfer, may include cleaning or being moved to temporary substrates.During the step 206, device is made to prepare transfer, it can be with
Including stripping technology, cleaning process and other steps.In addition, during the step 206, to for device function electrode or being used for
The connection pad or electrode of MIS structure are deposited and/or are patterned.During step 208, selected device is transferred to
Receiver substrate, this can be carried out by various methods, these methods are such as, but not limited to picked and placed or directly shifted.In step
MIS structure is formed during 204, may include the deposition and patterning of dielectric layer and conducting shell.In 210 phase of following step
Between, it is that device and MIS structure form connection.In addition, other optical layers and device can be integrated into system after shifting process
Substrate.The step of step 210 can be for 204 shared some techniques or to be completely independent.In the latter case, Qi Tagong
Skill step can carry out between 204 and 210.In an example, passivation or planarization layer can be deposited before step 210
And/or patterning is to prevent the short circuit between MIS electrode and other connections.
After patterning to device, according to Patternized technique, device can have straight wall or inclined wall.Following retouches
The case where stating based on selected inclination, but similar technique or the processing step of modification can also be used for other situations.In addition,
According to transfer method, the face for being connected to the device of receiver substrate can be different, and therefore will affect the slope of device wall.Next
The processing step of description can be used directly or be revised as to be used together with other slopes with device architecture.
Fig. 3 shows the microdevice 306 that system or receiver substrate 300 are transferred to negative slope.Device 306 is by extremely
A few contact pad 304 is connected to circuit layer 302.Herein, according to the slope of technique, Common deposition or polymer can be used to use
In generation MIS structure.Method described herein can be used together or be directly used in such case with some modifications.But if
Slope is too wide, then preferred method is to prepare MIS structure on device before transfer.It later will be to being used to give birth to before transfer
It is described at the illustrative methods of MIS structure.
Fig. 4 A shows the embodiment of the MIS structure according to method 1000.This can also be straight wall device.Fig. 4 A is shown
Device 406 after being transferred to system substrate 400 and being connected to circuit layer 402 by least one connection pad 404.Herein
After stage, MIS structure is produced or completed.Although traditional photoetching, deposition and Patternized technique are suitable for generating or completing
This structure is simultaneously connected to bias connection appropriate, but different methods can be used, and has the dislocation for microdevice
Further tolerance.Especially in large area technique, microdevice, which places inaccuracy, can be several microns.
Fig. 4 B shows the different structures that can be formed according to MIS structure.In one case, dielectric layer 408 is sunk
Product is to cover exposed undesirable contact pad.Through-hole 418 can be opened in the dielectric MIS is connected to circuit layer
402.Moreover, similar or different dielectric 410 can be deposited on at least side of microdevice using as the one of MIS structure
Part.The step can also carry out before device is transferred to system substrate 400.Later, the conducting shell 412 of MIS structure is completed
It is deposited and patterned.In one case, conducting shell 414 links together at least two MIS structures.In another situation
Under, MIS structure is connected to the contact pad 406 of microdevice 404 by conducting shell 416.Conducting shell can be to be transparent, to allow it
Its optical texture is integrated into system substrate or it can be to be reflexive, to assist light extraction or absorption.It is answered for some
With can also be opaque.After the formation of MIS structure, further process step can be performed, it is such as, but not limited to heavy
Product public electrode, optical texture/device are integrated.
Fig. 4 C shows the exemplary structure of the system substrate including depositing for public electrode.Herein, surface is flat
Change and is patterned to provide the access point for connection.Public electrode 426 can be connected to miniature by pattern 420,422,424
Device, MIS structure or circuit layer.
Fig. 4 D shows the example of public electrode 426.The electrode 426 can be patterned to generate addressable line.It can
It is transparent, reflexive or opaque.Several other methods can be used for the deposition of public electrode 426.In addition, other light
Learning device and structure can be integrated before or after electrode.
Fig. 5 A is illustrated before being transferred to system substrate 500 on donor (intermediate or original) substrate 560
Form a part or most technique of MIS structure.The technique can be in the initial substrates for manufacturing device or any
It is carried out at intermediate substrate.Fig. 5 A illustrates the different MIS structures that can be formed on device.Other structures can be used as.Electricity
Dielectric layer 516 can be deposited before the formation of MIS structure.This can avoid after the transfer between MIS and other contacts
Any undesirable short circuit/connection.MIS structure is formed by conducting shell 512 and dielectric layer 510.Dielectric layer can be with dielectric
Layer 516 is similar or different.It can also be the stacking of different dielectric layers.In structure 550 and 552, sunk without dielectric
Product is on the top of conducting shell 512.In structure 552, conducting shell 512 is from the marginal trough of device to avoid any short circuit.Make
The edge of 512 covering device 504 of conducting shell is also possible.In structure 554, conducting shell 512 extends to generate for turning
Move on to the easier access that system substrate generates connection later.In addition, the device is covered by dielectric layer 518, wherein electricity is situated between
The electrode that matter layer 518 has opening to be connected to microdevice 504 and extend.Structure 556 is covered miniature using dielectric 518
The top side of device 504.
Fig. 5 B shows the microdevice 504 after being transferred to system substrate 500 with MIS.During shifting process,
Device is reversed to be connected to the surface of donor substrate and be also connected to system substrate.In microdevice 504 and system substrate 500
Between connection pad may be present so that device is connected to circuit layer 502.Different methods, including side described above can be used
Method is used for the connection of MIS and other electrodes (for example, public electrode) to generate.Another kind method shown herein is used for structure
550 and 552.Both the electrode covering device 504 and the conducting shell of MIS structure 512.Electrode can be connected to circuit by 532
Layer 502 or its edge that system substrate can be connected to by engaging.In structure 554, conducting shell 540 be used to tie MIS
Structure is connected to circuit layer 502.Dielectric layer 516 can be made to extend in system substrate 500 to cover microdevice 504 and system and serve as a contrast
Connection pad between bottom 500, to avoid possible short circuit between MIS and other connections.In the case where 556, MIS can be short
Road to device contacts pad or its can be accurately aligned in system substrate with their own contact.For 554 Hes
Both 556, different post-processing step similar from the other structures in this patent can be used.A kind of example can be to have or not
Public electrode deposition with planarization.Another example can be light limiting structure or other optical textures.
Fig. 6 A is illustrated before being transferred to system substrate 500 on donor (intermediate or original) substrate 560
Form a part or most technique of MIS structure.The technique can be in the initial substrates for manufacturing device or any
It is carried out at intermediate substrate.Fig. 6 A illustrates the different MIS structures that can be formed on device.It is aobvious and easy for technicians
What is seen is that other structures can also be used.Dielectric layer 616 can be deposited before the formation of MIS structure.This will can avoid turning
Any undesirable short circuit after shifting between MIS and other contacts/couple.MIS structure is by conducting shell 612 and dielectric layer
610 form.Dielectric layer can be similar or different from 516.It can also be the stacking of different dielectric layers.In addition, connection pad
614 are formed on microdevice.In structure 650 and 652, no dielectric is deposited on the top of conducting shell 612.It is tying
In structure 652, conducting shell 612 is identical as contact pad 614.It is also possible for making the edge of 612 covering device 604 of conducting shell.?
In structure 654, conducting shell 612 extends to generate the easier access for generating connection after being transferred to system substrate.
In addition, the device is covered by dielectric layer 618, wherein dielectric layer 518 has opening to be connected to microdevice 604 and prolong
The electrode stretched.
Fig. 6 B shows the microdevice 604 after being transferred to system substrate 600 with MIS.In 604 He of microdevice
Connection pad may be present between system substrate 600 so that device is connected to circuit layer 602.Different methods can be used, including
Method described above is used for the connection of MIS and other electrodes (for example, public electrode) to generate.Another kind side shown herein
Method is used for structure 650 and 654.Herein, the negative slope of device is used to serve as a contrast by electrode 618 and through-hole 620 in MIS structure and system
Connection is generated between bottom.Passivation layer or planarization layer 622 can be deposited before electrode 618 deposits and patterns.Microdevice
604 can be capped during electrode deposition or conducting shell can by pattern and etch from its top remove.However, passing through
The electrode and MIS electrode 618 on the top 622 of microdevice 604 are separated using negative slope, are easier by unjustified
It influences, and this is very important high-throughput place of microdevice 604.For all structures, can be used in this patent
The similar different post-processing step of other structures.A kind of example can be heavy for the public electrode with or without planarization
Product.Another example can be light limiting structure or other optical textures.
Method described herein can be used for different structures, and the only a small amount example of these methods and can not influence
As a result it is changed in the case where.In an example, electrode and conducting shell can be transparent, reflexive or opaque.No
Same processing step can be added between each step in the case where not influencing and generating the result of MIS structure to improve device
Or different structures is integrated into device.
Vertical device with conductibility modulation engineering
Fig. 7 A shows vertical solid-state devices schematic diagram, and the main portion that can direct current through device is shown
The top layer and transverse current component of the part etching divided.In fig. 7, device layer 701 is formed in device substrate 700.Contact
Pad 703 is formed on device layer 701, and their voltage sources for example by being connected to contact pad 703 and public electrode 702
704 export.The function of device layer 701 is mainly limited by vertical electric current.However, due to the top surface cross conduction of device layer, tool
There is the electric current 705 of cross stream component to flow between contact pad 703 and public electrode 702.Referring still to Fig. 7 A, in order to reduce or
Eliminate transverse current flowing 705, it is proposed that use following technology：
1, top-layer resistance engineering
2, completely/part etching modulation
3, conductivity of materials is modulated
In this way, transverse current fluidal texture can be divided into three primary structures：At least with resistance engineering
One conducting shell, all or part of etching of one or more conducting shells and the material for conductibility modulation.With resistance
The conducting shell of engineering can be described as follows.The lucky semiconductor top layer before metal contact element 703 of vertical device 701 can
It is designed to conductibility or thickness by manipulating conducting shell to limit transverse current flowing.In one embodiment, work as top
When layer is the semiconductor layer of doping, the reduction of the thickness of the concentration of activated dopants and/or this layer can significantly limit lateral electricity
Stream flowing.Moreover, contact area can be defined to limit cross conduction.In another case, conducting shell (or is more than
One conducting shell) thickness can be reduced.Later, contact layer is deposited and patterned.This can be in array device or non-isolated device
It is carried out on part.As a result, active layer is not etched or separates to generate independent device, therefore the periphery of isolating device will not give birth to
At defect, because isolation is electrically developed by controlling electric current flowing.Similar technology is may be used on isolating device
It is shunted with the electric current to the periphery from device.In another case, after device is transferred to another substrate,
Its conducting shell is exposed.The thickness of this layer can be selected as it is high, with improve device manufacture.It is thick after conducting shell is exposed
Degree can be reduced or dopant density is lowered, however, some in conducting shell can also have barrier effect to opposite charges.
As a result, some so that entire conducting shell resistance is thinning to reduce device performance in removal conducting shell.However, it is for single layer
Engineering can be very effective.
Fig. 7 B is the schematic diagram of the device with part etching top layer.In this case, top conduction layers are such as two
P-type or n-type doping layer in pole pipe.Material for conductibility modulation directs current through the main portion of vertical solid-state devices
Point.At least one of conducting shell in device can be etched completely or partially.Referring to Fig. 7 B, it is located under top contacts 712
Top layer 716 in side and the top of device layer 718 can be etched completely or partially to eliminate or limit the transverse direction in these devices
Electric current flowing.Herein, microdevice 714 is limited by the size of contact pad 712.This will be to device for top-layer resistance manipulation
Performance is particularly advantageous for generating the device adversely affected.Herein, the thickness degree between adjacent devices is reduced so that electricity
It is higher to flow the resistance flowed in a lateral direction.Such as dry etching, wet etching or laser ablation can be used for etch process
It carries out.Herein, in many cases, top metal contact part 712 can be used as the mask for etching step.What is be fully etched
In the case of, etching can stop at functional layer.In one embodiment, the contact layer being deposited on the top of conducting shell can quilt
As the mask for being etched to conducting shell, to potentially realize less processing step and self-aligned structure.This is right
Manipulating in conducting shell resistance to be particularly advantageous for vertical device performance generates the device of adverse effect.Herein, it passes
Photoconductive layer thickness reduces in selected region, so that the resistance that electric current flows in a lateral direction is higher.It is logical in bottom conductive layers
After crossing the etching of metastasis or substrate and being exposed, identical etch process can be performed.Herein, contact can also by with
Act on the mask being etched to device.
Fig. 7 C is the schematic diagram with the vertical device of top conduction modulating layer and device layer 718.As shown, adjacent
The resistance in the region 720 of the conduction top layer 722 between contact pad 712 is manipulated to limitation transverse current components of flow.Compensation
The example that doping and laser ablation are modulated to the technique that can be used in the present embodiment.It is similar to whole/partial modulation scheme
Ground, in the present embodiment, top contacts are used as the mask for modulation step.In one case, oxidation can quilt
It uses.In one approach, photoresist is patterned to matching oxide regions, and then device is exposed to oxygen or other
Chemical oxidizing agent is to aoxidize the region.Then, contact is deposited and patterned.In another approach, it connects first
Contact element is deposited and patterned, and then contact is used as being used for aoxidizing mask.Oxidation step can isolating device or it is non-every
It is carried out from device.In another embodiment, before the oxidation, the overall thickness of conducting shell can be reduced.This can be only used for
It is carried out on the selected region of oxidation.In another case, oxidation can be carried out on the wall of device, and this especially suitable for every
From device.Moreover, bottom can similarly be modulated after being exposed.In another approach, conductivity of materials modulation can lead to
Electrical bias is crossed to carry out.Herein, it is desirable that the bias in high-resistance region is modified.In one case, bias modulation can pass through
MIS (metal-insulator semiconductor) structure carries out, and metal layer can substitute with any other conductive material.For example,
The electric current from contact is further distanced laterally from contact in order to prevent, and MIS structure is formed on around contact.It is this
MIS structure can be formed before or after contact is in place.In all above situations, active device area is by forming
Top contact pad on device layer limits.
The device that can be easier to be applied to that there is rod structure is limited to what active device area carried out by top contact pad
Part.Fig. 7 D shows the cross-sectional view of the MIS structure around single contact layer, it should be understood, however, that can equally connect to more than one
Contact layer accomplishes this point.Device layer 718 is the monolithic layer being made of rod structure 722.Since rod structure 722 is not by lateral connection,
So transverse current component is not present in device layer 718.One example of these devices is nanowire LED, wherein LED component
It is made of the multiple nanowire LED structures for manufacturing on a common substrate.In this case, as shown in Figure 7 D, top metal
The active region of contact restriction LED structure.Device layer without cross conduction is not limited to rod structure, and extends to tool
There is the device layer of the active region of separation, such as there is the nanometer of insertion or the layer of micron ball or other forms.
Fig. 7 E shows the cross-sectional view of the MIS structure around contact layer.By the way that the conducting shell of MIS structure is biased into shutdown
Voltage, limited electric current or without electric current will be laterally through the structure.MIS structure may be formed on device or can turn for warp
A part of the substrate of shifting, and MIS structure limits the direction of cross conduction.Other configurations are envisioned that, such as conducting shell
It may extend into the two sides of MIS structure, so that dielectric can extend over other conducting shells.MIS structure can also to be open or
Enclosed construction, or it is optionally continous way or single structure.In another embodiment, dielectric may include from light
Cause the oxide layer of resist or masks.In addition, another dielectric can be deposited on the top of oxide layer, or deposition
Dielectric can be used alone.In another embodiment, conducting shell can be removed, so that dielectric is contacted with semiconductor layer.
MIS structure also may be formed on the wall of device the edge for further containing current direction device.Device surface can also be situated between by electricity
Matter covering.For example, grid conducting shell can be deposited and patterned so that for gate electrode, then dielectric gate electrode can be used to be used as and cover
Mould patterns.In another approach, it is patterned first as the dielectric of insulator, then grid is deposited.Grid
It can be patterned, or can be individually carried out simultaneously with contact.Similar MIS structure can also be in the other side after it is exposed
On manufactured.The thickness of the conducting shell of device can be reduced, to improve the validity of MIS.On the either side of vertical device
In the case that the selective etch of conducting shell or modulation are difficult, MIS method can be it is more actual, especially if etching or resistance
In the case that modulation may damage active layer.In described vertical structure, active device area is limited by top contact zones
It is fixed.
Method for manufacturing light-emitting diode display
The method for manufacturing light-emitting diode display is described using the LED component in common Grown on Sapphire Substrates.
It discloses for the light emitting diode construction of light-emitting diode display and its manufacturing method.LED includes substrate, is formed on substrate
First doped layer (for example, n-layer), active layer and another doping conducting shell (for example, p-type layer).Referring to gallium nitride base
(GaN) LED is described, however, any type that presently described vertical device architecture can be used for having different materials system
LED.
In general, GaN LED is manufactured by the stacking of deposition materials on a sapphire substrate.Fig. 8 A is schematically shown
Conventional GaN LED component comprising such as sapphire substrate, the N-shaped GaN being formed on substrate or buffer layer (such as GaN)
The active layer and p-type GaN layer of layer, such as multiple quantum wells (MQW) layer.The transparent conductive layer of such as Ni/Au or ITO are generally formed in p-
To be conducted for better transverse current in the GaN layer of doping.Traditionally, the p-type electrode of such as Pd/Au, Pt or Ni/Au is then
It is formed on the transparent conducting layer.Since substrate (sapphire) is insulator, N-shaped GaN is exposed to contact the layer.The step
It is rapid to carry out then depositing metal contact element appropriate with exposing n-type GaN usually using dry method etch technology.It is in display pixel
In the light-emitting diode display application of individual devices LED, each LED is engaged to driving circuit, and driving circuit control is flowed into
Electric current in LED component.Herein, driving circuit can be to be routinely used for LCD or Organic Light Emitting Diode (OLED) display panel
In thin film transistor (TFT) (TFT) backboard.Due to typical Pixel Dimensions (10 to 50 μm), engagement can be executed with wafer level.?
In the present solution, being aligned by the LED wafer that the independent LED component being isolated is constituted and being joined to backboard, wherein backboard is in pixel
It is compatible with LED wafer in terms of size and pel spacing.Herein, each of such as laser lift-off or etching can be used in LED wafer substrate
Technique is planted to remove.
Fig. 8 B shows the manufacturing process of LED, and show device substrate with limited by top contacts 802 it is miniature
The integrated technique of device and the substrate to system substrate engagement.Microdevice uses the top being formed on the top of device layer
Portion's contact 801 limits, and can be engaged with contact pad 804 and be transferred to system substrate 803.For example, microdevice can be
Miniature LED, wherein miniature LED has the size limited using any method explained above by the region of its top contacts.
System substrate can be the backboard that independent miniature LED is driven with transistor circuit.In the art, LED component passes through dry
Method etching and passivation layer are isolated.The completely isolated of device can generate defect in active layer or functional layer, to reduce effect
Rate simultaneously leads to inhomogeneities.Due to becoming smaller with device, the periphery in the region of microdevice is more substantive, thus the shadow of defect
Sound becomes readily apparent from.In one embodiment, single chip LED device is not etching active region and is grasping without using cross conduction
Individual miniature LED is converted into the case where vertical.As a result, generating defect without side wall in miniature LED.Across LED gusts
Therefore the peripheral wall of column can be extended, influence until they do not generate peripheral LED component.Optionally, empty around one group of array
Quasi- LED component can be used for reducing influence of the peripheral wall to Active Micro LED component.This technology can also be used for preventing or reducing logical
Cross the electric current of side wall.
In another embodiment, LED wafer, which can be manufactured into, makes p-type layer top layer, just as seen in fig. 8 c.P-type layer
Thickness and conductibility can be manipulated to control the cross conduction by device.This can pass through pre-deposition during LED structure manufactures
P layer etching or carried out by depositing relatively thin p layer.For engraving method, dry method is can be used in accurate thickness control
Etch process is realized.In addition, p layers of material structure can be changed by layer doped level, to increase the lateral resistance of layer.Top
Layer is not necessarily limited to p layers, and extends to other top layers in LED structure.As the change as a result, illumination region can
Only limited by the conduction layer region of the deposited on top of p-type film.
In another embodiment shown in Fig. 8 D, in order to further limit transverse illumination, between two adjacent pixels
P layer can be etched completely or partially.The processing step can carry out after conducting shell deposition in the technique of such as dry etching.
In this case, conducting shell is used as mask.Preferably, the limitation of this structure or the wall passivation of elimination pixel, and this causes
The more or per inch pixel (PPI) of pixel in the specific region of wafer is higher.It is completely isolated with being passivated with wall
LED compare, this can also be converted into less processing step and lower manufacturing cost.
In another example, Fig. 8 E shows the LED wafer knot limited by top contacts and p layers of laser-induced thermal etching
Structure.Herein, the laser ablation of GaN can be used to etch partially or completely to remove for top layer, p-type layer.In this case, laser is logical
Amount defines ablating rate, and any thickness of p-type GaN layer can be etched accurately.A kind of example of this laser is red
Or the femtosecond laser of infrared wavelength.Herein, top metal contact part or other protective layers are used as mask in the art.It is optional
Special optical device can be used to limit for ground, laser beam size, to match desired etching area size.In another example
In, shadow mask can be used for limiting etching area.Laser ablation etches the other layers that can also be extended to LED structure.This
In the case of, independent LED component is isolated each other completely or partiallyly.In this scene, it may be desired to pass through deposit dielectric layer
To be passivated LED etch wall.
In the above-described embodiment, n-layer contact can pass through engagement in layer and remove to back plane circuitry or any other
Substrate is formed after being exposed by being etched to substrate.In this scene, n-layer contact can be transparent conductive
Layer, to allow illumination to pass through the layer.In this case, n-layer contact can be public for all or part of the LED of engagement
, just as illustrated in figure 9 a, and Fig. 9 A shows the LED wafer of the n contact with the common transparent for being joined to back board structure.
In the case where LED device structure is grown in semiconductor buffer layer (such as undoped with GaN substrate), LED shifting process it
Afterwards, which can be removed to access n-layer.In embodiment shown in figure 9 a, entire GaN buffer layer is used as dry
Method/wet etching technique removes.
Fig. 9 B shows the integrated device with the microdevice limited by the top contacts for being joined to system substrate and serves as a contrast
Bottom.Public electrode is formed on the top of structure.It is shifted to the device layer 902 for including bottom p-type layer and top n-layers
After engagement, common top 906 can be deposited on this structure.For some optical device layers, public top is connect
Contact element can be transparent conductive layer.Substrate or backboard are 904.
Fig. 9 C shows the LED wafer with buffer layer and metal n contact through hole and has by being joined to system substrate
Top contacts limit microdevice integrated device substrate.Public electrode is formed in edge and passes through the top of structure
On buffer layer.As shown, buffer layer is patterned around the edge, so that through-hole manufacture is at passing through buffer layer with shape
It is contacted in pairs in the metal of n-layer.The top layer of integrated morphology can be the layer with low conductivity.For example, the layer can be in device
The buffer layer that the growth period of layer 902 uses.In this case, public electrode 910 can be for example, by the edge of structure
Through-hole is set to pass through buffer layer 908 to be formed.
Fig. 9 D shows the example of the transferred LED wafer with patterning n-layer.Successively have below n-layer
Active layer and p-type layer.In order to be further reduced lateral light propagation or adjusting device clarity, as shown in figure 9d, n-layer use with
The identical structure of preceding metal contact element is patterned by being partially or completely removed the layer.Optionally, thickness degree is reduced.n
Type contact can be formed by depositing transparent conductive layer on top of this construction.With the miniature device limited by top contacts
The integrated device substrate of part is engaged to system substrate.It is patterned to be electrically isolated microdevice at the top of the structure.Device
Layer 902 can be patterned or be modulated so that microdevice is further electrically and/or optically isolated.
Fig. 9 E shows another example of the transferred LED wafer with patterning n-layer.There are buffer layers
In the case of, the layer and n-layer are patterned, just as shown in figure 9d.In one embodiment, patterned groove can quilt
It is further processed and is filled with the material for making to be improved by the light propagation of pattered region.The example of this respect is that surface is thick
Roughening is to inhibit total internal reflection and reflecting material to be used to prevent the vertical light propagation in these regions.The integrated device substrate
Including the microdevice limited by the top contacts for being joined to system substrate.Electricity and optics are patterned at the top of the structure
Microdevice is isolated in ground, and public contact is formed in the edge of the structure.If buffer layer 908 exist, in order to every
From microdevice, buffer layer is also required to be patterned or modulate.Similar with embodiment shown in Fig. 9 D, public contact can
Such as the edge of structure is formed in by the through-hole in buffer layer.
Fig. 9 F, which is shown, to be had by being joined to the top contacts of system substrate and being formed between adjacent microdevice
Optical element limit microdevice integrated device substrate.As shown, area of isolation can by one layer of optical layer 914 or
Filling is stacked to improve the performance of the microdevice of isolation.For example, element 914 can be some reflections in miniature optical device
Material so as to preferably be coupled in the vertical direction by the light that microdevice generates.Fig. 9 G is shown with patterned n-layer
With the example of the transferred LED wafer of light regime scheme.
In the light-emitting diode display application that display pixel is individual devices LED, each LED should all be engaged to driving circuit,
And the driving circuit controls the electric current being flowed into LED component.Herein, driving circuit can be to be routinely used for LCD or OLED to show
Show TFT (thin film transistor (TFT)) backboard in panel.Due to typical Pixel Dimensions (10 to 50 μm), engagement can be held with wafer level
Row.In the present solution, being aligned by the LED wafer that the independent LED component being isolated is constituted and being joined to backboard, wherein backboard
It is compatible with LED wafer in terms of Pixel Dimensions and pel spacing.Herein, such as laser lift-off or erosion can be used in LED wafer substrate
The various techniques carved remove.In this case, LED component is isolated by dry etching and passivation layer to be important.
In one embodiment, p-type layer is, for example, that the LED wafer of top layer is manufactured.P-type layer thickness and conductibility are grasped
It indulges to control cross conduction.This by the etching of the p layer of pre-deposition or can deposit relatively thin p layer during LED structure manufactures
Come carry out.For etching scene, dry method etch technology is can be used to realize in accurate thickness control.In addition, p layers of material structure
It can be changed according to layer doped level, to increase the lateral resistance of layer.It should be noted that top layer is not limited to p layers, and extend to
Other top layers in LED structure.As the change as a result, illumination region can be only by the conducting shell of the deposited on top of p-type film
Region limits.
In order to further limit transverse illumination, the p-type layer between two adjacent pixels can be etched completely or partially.The work
Skill step can carry out after conducting shell deposition in the technique of such as dry etching.In this case, conducting shell is used as
Mask.One considerable advantage of the program is to eliminate the wall passivation of pixel, and this leads to the pixel in the specific region of wafer
More or per inch pixel (PPI) it is higher.Compared with the completely isolated LED being passivated with wall, this can also be converted
For less processing step and lower manufacturing cost.
In another example, another device layer can be transferred on the top of existing transferring device.Fig. 9 H shows use
The device that partition method stacks, and show and carry out separator using planarization layer and dielectric layer between two stacking devices
The device of the stacking of part.It should be noted that any layer can be eliminated.In one case, the surface of transferred device is put down first
Smoothization.Then, through-hole can be open to generate the contact for backboard.The contact can be located in the edge or centre of array.
Then contact layer including trace and island is deposited and patterned.Finally, second group of device is transferred.The technique can continue
Shift other devices.In another case, the top contacts of the first device can be shared with the bottom contact of the second device.
In this case, planarization layer can be eliminated.
In another embodiment as shown in FIG. 10A, system substrate contact pad or convex block 954 can limit miniature device
Part region.Figure 10 A shows the integrated technique of device substrate and system substrate.Microdevice in integrated morphology is by system substrate
On contact tab partly limit.In this case, device layer 952 does not have any top contacts to limit miniature device
Part region.Device layer 952 on substrate 950 is joined to by the array by the isolated contact pad of insulating layer 956 or convex block 954
System substrate 958.Herein, it is bonded between metal contact pad 954 and device layer 952 and carries out.The joint technology, which can be used, appoints
What joint technology executes, such as, but not limited to heat and/or pressurize engagement or laser heating engagement.The advantage of this process is that
Microdevice eliminates aligned process during being transferred to system substrate.Herein, microdevice size 960 and spacing 962 are by contacting
Limit to the sized fraction of pad/convex block 954.In an example, device layer 952 can be the LED in Sapphire Substrate 950
Layer, and system substrate 958 can be display backplane, wherein and the display backplane has driving by the contact tab on backboard
Circuit needed for the independent miniature LED partly limited.
Figure 10 B shows the integrated technique of device substrate and system substrate.Microdevice in integrated morphology is served as a contrast by system
Contact tab on bottom limits completely.In order to be accurately defined microdevice size 960 and microdevice spacing 962, bank layer
It is deposited and patterned in system substrate.Bank layer opening around each contact pad 954 will limit microdevice completely
Size 960 and microdevice spacing 962.In one embodiment, bank layer can be jointing material.
Figure 10 C shows the integrated device substrate for shifting and being joined to system substrate.Public electrode is formed in the top of structure
In portion.After by the engagement to system substrate of microdevice substrate, as shown in figure 10 c, microdevice substrate 950 can be used each
Kind method removal, and public contact may be formed above integrated morphology.In the miniature optical of such as, but not limited to miniature LED
In the case where device, which can be transparent conductive layer.Herein, dam configuration 964 is for eliminating may be due to pressure
Short circuit after caused diffusion effect between adjacent pad.Moreover, other layers of public electrode, color conversion layer etc.
966 can be deposited after splicing.
Figure 10 D shows the integrated morphology for having transferred device layer and joint element in the edge of backboard.At this
In embodiment, adhesive bond element 968 can be used in the edge of backboard system substrate is arrived in the engagement of device layer 952.
In one case, joint element 968 can be used for device layer temporarily holding system substrate, for contact pad to device
The joint technology of layer.In another case, microdevice layer 952 is permanently attached to system substrate by joint element 968.
Figure 10 E shows the integrated work of engagement patterning and public electrode carry out after device substrate and system substrate
Skill.In the present embodiment, device layer 952 can be patterned after being transferred to system substrate.Patterning 970 can be designed and
It is embodied as that microdevice is electrically and/or optically isolated.After patterning to device layer, public electrode can be deposited over integrated
On substrate.In the case where the optical device of such as LED, public electrode can be transparent conductive layer.
Figure 10 F shows engagement patterning, optical element and public electrode after and forms the device substrate and system carried out
The integrated technique of substrate.As shown, after device layer 952 is shifted and is patterned, extra play can be deposited and/or
The performance for enhancing microdevice is formed between the microdevice of isolation.In an example, these elements can be passivated isolation
Microdevice side wall in the case where miniature optical device (such as, but not limited to miniature LED) help light vertical coupling
It closes.
In the method explained at present, protective layer can finally be formed on the top of integrated morphology with serve as barrier layer and
Damage resistant layer.Moreover, some can be deposited on after microdevice by opaque layer and be patterned to form pixel.It should
Layer can be located at any position in stacking.Opening will allow light only to pass through pixel array and reduce interference.
Microdevice as described in this article can for example pass through etching wafer and form mesa structure to develop.Table top is formed
Dry or wet etching technique can be used to carry out.Reactive ion etching (RIE), inductively coupled plasma body (ICP)-RIE and
The chemical assistant ion beam moment, (CAIBE) may be utilized in the dry etching of wafer substrate.Chlorine-based gas (such as Cl2、BCl3Or
SiCl4) can be used for etching wafer.Carrier gas (including but not limited to Ar, O2, Ne and N2) can be introduced in reaction chamber to increase respectively
The degree of anisotropy etching and side wall passivation.
Figure 11 shows the process flow chart 1000A of the wafer etching process formed for mesa structure.Referring to Fig.1 1,
It in step 1001, is etched using the peroxosulphuric (piranha) comprising sulfuric acid and hydrogen peroxide, then uses the DI of hydrochloric acid
Water cleaning cleans wafer.Step 1002 is the deposition of dielectric layer.In step 1006, dielectric layer is carried out
Etching in this layer of upper generates to be open for subsequent crystal round etching.In step 1008, dry etch technique and chlorine are used
Chemistry is etched to develop mesa structure wafer substrate.In step 1010, it is gone by wet process or dry etching method
Except hard mask, then wafer is cleaned.
Figure 12 A shows the device deposited on crystal column surface 1202 with dielectric layer 1202.In wafer cleaner step
Later, hard mask 1204 is formed on the wafer surface.In embodiments, 1204 (such as SiO of dielectric layer2Or Si3N4) use
As the appropriate deposition technique of plasma enhanced chemical vapor deposition (PECVD) is formed in wafer substrate.Photoresist
Then 1206 are coated on the dielectric layer.In lithography step, desired pattern is formed in photoresist layer.Example
Such as, PMMA may be formed on dielectric layer, and opening is then formed on PMMA by direct electron beam photoetching technique.
Figure 12 B shows the dielectric layer 1202 on wafer 1200 and is etched away to generate opening on layer for subsequent
The device of crystal round etching.Dielectric layer is etched away in this layer of upper opening that generates for subsequent crystal round etching.In Figure 12 B
It is shown, it may be utilized with the dry-etching method of fluorine chemistry to be etched selectively to dielectric layer.Carrier gas (including but not limited to N2、
Ar、O2) can be introduced into control the degree of anisotropic etching.Specific gas flow rate and mixing ratio, carrier gas type, RF and dc power
And underlayer temperature can be conditioned the anisotropy to realize desired rate of etch and height.
Figure 12 C shows the mesa structure after wafer substrate etching step.In one embodiment, there is straight sidewall
Mesa structure 1208 can be formed.In another embodiment, the mesa structure 1210 with sloped sidewall can be formed.Gas
The type of gas and relevant etching condition are adjusted to alter the gradient of side wall in body mixing ratio, reactor.According to the phase
The mesa structure of prestige, straight sidewall, just oblique side wall and bears oblique side wall and can be formed.In embodiments, the side during etching step
Wall passivation can be used to generate desired side wall profile.In addition, cleaning can be used for removing passivation layer or day from side wall
Right oxide.It acetone, isopropanol can be used to be cleaned, then use (NH4)2And/or NH4OH is surface-treated.
In embodiments, MIS structure can be formed after mesa structure formation.Figure 13 is shown for MIS structure
Formation process flow 1000B.In processing step 1114 and 1116, on mesa structure deposit dielectrics and metal layer with
Form MIS structure.After the deposition of dielectric layer, in technique 1116, such as thermal evaporation, electron beam deposition and sputtering are used
Various methods on layer deposited metal film.In processing step 1118, desired figure is formed on wafer using lithography step
Case.In step 1120, metal is etched using dry or wet etching, thus the top of square mesa structure on the dielectric layer
Opening is formed on side.In step 1122, lithography step can be used to limit dielectric etch region.In another embodiment
In, etched metal layer is used as the mask for etching dielectric layer.In step 1126, it can sink on metal sandwich
The second dielectric layer of product.In step 1128, the deposit ohmic p-contact part on wafer, as shown in Figure 14 E.It is walked in technique
In rapid 1130, the deposition of thick metal on p-contact part, in the processing step from native substrate removing wafer by table top knot
Structure is joined to the subsequent engagement on temporary substrates, as shown in Figure 14 E.
Figure 14 A shows the dielectric and metal layer for being deposited on and forming MIS structure on mesa structure.1402 He of dielectric
Metal layer 1404 is deposited on mesa structure 1400 to form MIS structure.Various dielectric layers can be used comprising but not
It is limited to Si3N4And such as SiO2、HfO2、Al2O3、SrTiO3, Al doping TiO2、LaLuO3、SrRuO3, HfAlO and HfTiOx
Oxide.The thickness of dielectric layer can for several nanometers or micron.The various methods of such as CVD, PVD or electron beam deposition are available
In deposit dielectric layer.In embodiments, atomic layer deposition (ALD) method can be used to be sunk for high k oxides dielectric layer
Product.ALD allows to be formed the dielectric layer of very thin and high K on wafer.It is preceding between the ALD deposition of dielectric oxide layer
Body is driven successively to be introduced into reaction chamber to form thin insulator layer.Metal precursor includes halide, alkyl and alkoxide and β-two
Ketone.Water, ozone or O can be used in oxygen2To provide.According to process chemistry, dielectric film deposition can at room temperature or risen
It is carried out at a temperature of high.Al2O3Deposition can also be used trimethyl aluminium (TMA) and water presoma to carry out.For HfO2ALD is heavy
For product, HfCl4And H2O presoma can be used.Metal electrode is used as the biased contact for carrying out Electric Field Modulated in the devices
Part.Metal contact element includes but is not limited to Ti, Cr, Al, Ni, Au or stacked laminations of metal.
Figure 14 B shows the wafer with the pattern formed using lithography step.Figure 14 C, which shows to have, uses fluorine chemistry
The wafer of the dielectric layer of substance dry etching.Etch stop is the top surface of mesa structure.As shown in fig. 14d, second
Dielectric layer 1406 can be deposited on to deposit for subsequent p- contact in metal intermediate layer, to prevent and device function electrode
Short circuit.Then, the dielectric layer on the top of mesa structure is etched away to generate opening on the top surface of mesa structure.
As shown in Figure 14 E, ohm p-contact part 1408 is deposited on wafer.Thermal evaporation, sputtering can be used in P contact
Or electron beam evaporation deposits.Au alloy (such as Au/Zn/Au, AuBe, Ti/Pt/Au, Pd/Pt/Au/Pd, Zn/Pd/Pt/Au,
Pd/Zn/Pd/Au it) can also be used for P-contact layer.The region that subsequent patterning step never needs to removes metal, to allow to connect
Contact element is made only on the top surface of mesa structure.Thick metal 1410 can be deposited on p- contact, to be used for from native substrate
By mesa structure engagement to the subsequent engagement on temporary substrates in the processing step of removing wafer.
The scope of the present invention is not limited to LED.These methods can be used to limit the active region of any vertical device.Such as
The different method of laser lift-off (LLO), grinding, wet process/dry etching can be used for for microdevice being transferred to from a substrate
Another substrate.Microdevice can be transferred to another substrate from growth substrates first, be then transferred into system substrate.Of the invention
Device is also not necessarily limited to any specific substrate.Mentioned method can be applied to N-shaped or p-type layer.For N-shaped and p-type layer
Exemplary L ED structure for, position should not limit the range of invention.
Although the disclosure is easy to carry out various modifications and alternative form, specific embodiment or implementation are to lift
The mode of example shows in the accompanying drawings and describes in detail herein.However, it should be understood that the disclosure be not limited to it is disclosed
Particular form.On the contrary, the disclosure falls into covering in the spirit and scope of the present invention being defined by the appended claims
All modifications, equivalents, and substitutions object.
Claims (13)
1. vertical current-mode solid-state devices, including：
Connect pad；And
Side wall, the side wall include metal-insulator semiconductor (MIS) structure,
Wherein, the leakage current effects of the vertical device are by limiting the MIS structure bias via the side wall.
2. device as described in claim 1, wherein the device is connected to circuit layer by least one connection pad.
3. device as described in claim 1, wherein the electric current is shunted from the periphery of the vertical device.
4. device as described in claim 1, wherein the device is miniature LED component.
5. solid-state devices, including current mode device array, the current mode device array is located to be conducted by least one
In the continuous semiconductor piece of the resistance engineering development of layer.
6. device as claimed in claim 5, wherein the connection pad changes the resistance and limits independent vertical device
The size of part.
7. device as claimed in claim 5, wherein the resistance engineering includes losing at least one described conducting shell
It carves.
8. device as claimed in claim 5, wherein the resistance engineering includes that the measurement carried out at least one conducting shell changes
Become, modulate or combinations thereof.
9. device as claimed in claim 5, wherein the device is miniature LED component.
10. device as claimed in claim 5, wherein mask for changing at least one conducting shell lateral resistance.
11. device as claimed in claim 5, wherein the resistance of the conducting shell is changed by aoxidizing.
12. the method that the electric current in pair current driving apparatus including side wall redirects, the described method comprises the following steps：
The device is directed current to by connecting pad；And
Field is generated using metal-insulator semiconductor to eliminate the leakage current in the side wall.
13. passing through the side for limiting current to generate vertical device array in the selected region of blocky current driving device
Method.
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| CN202111597807.4A CN114256392A (en) | 2015-12-24 | 2016-12-23 | Vertical solid state device |
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| CA2916291A CA2916291A1 (en) | 2015-12-24 | 2015-12-24 | Improving performance of vertical devices |
| CA2924157A CA2924157A1 (en) | 2016-03-18 | 2016-03-18 | Micro-device array definition and integration |
| CA2924157 | 2016-03-18 | ||
| PCT/IB2016/057995 WO2017109768A1 (en) | 2015-12-24 | 2016-12-23 | Vertical solid state devices |
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| Publication number | Publication date |
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| CN108886073B (en) | 2022-01-11 |
| WO2017109768A1 (en) | 2017-06-29 |
| US12068428B2 (en) | 2024-08-20 |
| CN114256392A (en) | 2022-03-29 |
| DE112016006010T5 (en) | 2019-01-24 |
| US20170186907A1 (en) | 2017-06-29 |
| US20200381582A1 (en) | 2020-12-03 |
| US10784398B2 (en) | 2020-09-22 |
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