CA2924157A1

CA2924157A1 - Micro-device array definition and integration

Info

Publication number: CA2924157A1
Application number: CA2924157A
Authority: CA
Inventors: Reza Chaji
Original assignee: Individual
Current assignee: Individual
Priority date: 2016-03-18
Filing date: 2016-03-18
Publication date: 2017-09-18

Abstract

Patterning LED into micro size devices to create array of LEDs for display applications come with several issues including material utilization, limited PPI, and defect creation. This invention solve these issues by creating array of LEDs using vertical conductivity engineering. In this case, the current transport in horizontal direction is controlled to the pixel area and so there is no need for pattering the LEDs.

Description

APPLICATION FOR PROVISIONAL PATENT
for MICRO-DEVICE ARRAY DEFINITION AND INTEGRATION

MICRO-DEVICE ARRAY DEFINITION AND INTEGRATION
FIELD OF THE INVENTION
[0001] The present invention relates to the fabrication of an integrated array of microdevices. The array of micro devices is defined by another array of contacts either on the device substrate or the system substrate.
BRIEF SUMMARY

[0002] one embodiment is a method of creating an array of vertical devices by modifying the lateral conduction without isolating the active layers

[0003] Here, the vertical device can be micro-led, sensor or other devices

[0004] Another embodiment is a method of diverging the current from the perimeter of a vertical device by modifying the lateral conduction

[0005] In this method the resistance of the conductive layers is modified by oxidation.

[0006] In another case, the lateral resistance of the conductive layers is modified by modifying the bias condition.

[0007] In another case, the contact is used as mask modify the lateral resistance of the conductive layer.

[0008] Another embodiment is a method of pixelating a display device by defining the pixel pad connection in backplane and attaching the LED device with vertical conduction modulation to the backplane. In one case, the current spreader is removed or its thickness is reduced to modulate the vertical conduction. In another case, some of the micro device layers are etched to create vertical conduction modulation. Here, a bonding element can be used to hold the device to the backplane.

[0009] One embodiment that is disclosed are structures and methods for defining micro devices on the device layer by forming contact pads on it before transferring it to a receiver substrate and structures and methods to define the micro devices by contact pads / bumps on the receiver substrate in an integrated microdevice array system consist of a transferred monolithic array of micro device and a system substrate.

[0010] One embodiment is a method of manipulating the top conductive layer of a vertical device in which the functionality of the device predominantly is defined by the vertical currents, the method comprising:
a. Top layer resistance engineering in which the lateral resistance of the top layer is manipulated by changing the thickness or specific resistivity of this layer b. Fully/Partial etching modulation in which the top layer of the vertical device is modulated by any means of etching c. Material conductivity modulation in which the resistance of the top layer is modulated by various methods including but not limited to etching, counter doping, and laser ablation

[0011] Here, the contact pads on the top device layer can define the size of the individual microdevices.

[0012] After transfer of micro devices, a common electrode can be deposited on the transferred monolithic array of microdevices to improve the conductivity.

[0013] The common electrodes can be formed through vias in the top buffer or dielectric layers transferred or deposited on the monolithic array of micro devices .

[0014] Also, the top layer of the transferred monolithic array of micro devices can be modulated by any means of removing. In this case, optical elements are formed in the removed regions of the modulated top layer.

[0015] Another embodiment is a method of forming an array of micro devices on an integrated structure in which the device layer prepared according to aforementioned methods is transferred to a receiving substrate wherein the contact pads on the top of the receiving substrate is bonded to the device layer and the size of the individual microdevices are defined partially by the size of contact pads/bumps on the receiver substrate.

[0016] Here spacers / banks can be formed around contact pads/bumps to fully define the size of the micro devices.

[0017] The spacers/banks around contact pads/bumps can be adhesives to promote bonding the device layer to the receiver substrate.

[0018] Here also the top layer of the integrated microdevice array is modulated by any means of removing. In this case, the optical elements can be formed in the removed regions of the modulated top layer.

[0019] The foregoing and additional aspects and embodiments of the present disclosure will be apparent to those of ordinary skill in the art in view of the detailed description of various embodiments and/or aspects, which is made with reference to the drawings, a brief description of which is provided next.
BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The foregoing and other advantages of the disclosure will become apparent upon reading the following detailed description and upon reference to the drawings.

[0021] FIG. 1 shows a vertical solid state device schematic showing the lateral current components

[0022] FIG. 2 shows the schematic of a device with partially etched top layer.

[0023] FIG. 3 shows the schematic of a device with top layer modulation.

[0024] FIG. 4 shows the schematic of a device layer with nanowire structures.

[0025] FIG. 5 shows the integration process of a device substrate with micro devices defined by top contacts and bonding of this substrate to a system substrate.

[0026] FIG. 6 shows an integrated device substrate with micro devices defined by top contacts bonded to a system substrate. A common electrode is formed on top of the structure.

[0027] FIG. 7 shows an integrated device substrate with micro devices defined by top contacts bonded to a system substrate. Common electrodes are formed at the edges and through a buffer layer on top of the structure.

[0028] FIG. 8 shows an integrated device substrate with micro devices defined by top contacts bonded to a system substrate. Top of the structure is patterned to isolate micro devices electrically.

[0029] FIG. 9 shows an integrated device substrate with micro devices defined by top contacts bonded to a system substrate. Top of the structure is patterned to isolate micro devices electrically and optically and common contacts are formed at the edge of the structure.

[0030] FIG. 10 shows an integrated device substrate with micro devices defined by top contacts bonded to a system substrate and optical elements formed between adjacent micro devices.

[0031] FIG 11 shows the integration process of a device substrate and a system substrate.
The micro devices in the integrated structure is partially defined by the contact bumps on the system substrate.

[0032] FIG. 12 shows the integration process of a device substrate and a system substrate.
The micro devices in the integrated structure is fully defined by the contact bumps on the system substrate.

[0033] FIG. 13 shows an integrated device substrate transferred and bonded to a system substrate. A common electrode is formed on top of the structure.

[0034] FIG. 14 shows an integrated structure with transferred device layers and bonding element at the edge of the backplane.

[0035] FIG. 15 shows the integration process of a device substrate and system substrate with post bonding patterning and common electrode.

[0036] FIG. 16 shows the integration process of a device substrate and system substrate with post bonding patterning, optical element, and common electrode formation.

[0037] While the present disclosure is susceptible to various modifications and alternative forms, specific embodiments or implementations have been shown by way of example in the drawings and will be described in detail herein. It should be understood, however, that the disclosure is not intended to be limited to the particular forms disclosed.
Rather, the disclosure is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of an invention as defined by the appended claims.
DETAILED DESCRIPTION

[0038] This document discloses various methods for lateral conduction manipulation of vertical solid state devices and methods to define and isolate micro devices in an integrated structure where an array of micro devices are transferred and bonded to a system substrate. In addition this document discloses methods for post bonding processes to interconnecting micro devices and isolating them electrically and optically for better performance.

[0039] In this patent, micro devices may be sensors, Light Emitting Diodes (LEDs) or any other solid devices grown, deposited or monolithically fabricated on a substrate. The devices substrate may be the native substrate of the device layers or a receiver substrate where device layers or solid state devices are transferred to.

[0040] The system substrate may be any substrate rigid or flexible. The system substrate may be made of glass, silicon, plastics or any other commonly used material.

[0041] The system substrate may have active electronic components such as but not limited to transistors, resistors, capacitors or any other electronic component commonly used in a system substrate. In some cases the system substrate may be a substrate with electrical signal rows and columns.

[0042] In one example the device substrate may be a sapphire substrate with LED layers grown monolithically on top of it and the system substrate may be a backplane with circuitry to derive micro-LED devices.

[0043] Various transferring and bonding methods may be used to transfer and bond device layers to the system substrate. In one example hart and pressure may be used to bond device layers to a system substrate.

[0044] In a vertical solid state device, the current flow in the vertical direction predominantly defines the functionality of the device. Light Emitting Diodes (LED) may be categorized as a vertical solid state device.

[0045] Here, the proposed fabrication methods are used to limit the lateral current flow of these devices.

[0046] FIG. 1 shows an exemplary schematic of a vertical solid state device with lateral current components. In this figure device layer 101 is formed on the device substrate 100.
contact pads 103 is formed on the device layer 101 and ther are derived by for example a voltage source 104 connected to the contact pads 103 and common electrode 102.
The functionality of device layer 101 is predominantly defined by the vertical current. However, due to the top surface lateral conduction of the device layer, current 105 with lateral components flow between contact pads 103 and common electrode 102.

[0047] Still referring to FIG. 1, in order to reduce or eliminate the lateral current flow 105, following techniques are suggested by this patent 1. Top layer resistance engineering 2. Fully/Partial etching modulation 3. Material conductivity modulation

[0048] Top layer resistance engineering: in this scheme, referring to FIG. 1, the semiconducting top layer of the vertical device 101, just before the metallic contact 103, can be engineered to limit the lateral current flow by manipulating the conductivity or thickness of this layer. In one embodiment, when the top layer is a doped semiconducting layer, decreasing the concentration of active dopants and/or the thickness of this layer can significantly limit the lateral current flows.

[0049] Fully/Partial etching modulation: in this scheme, referring to FIG. 2, the top layer 101A below top contact 201 and on top of the device layer 101 can be fully/partially etched to eliminate/limit the lateral current flow in these devices. Here, the micro device 202 is defined by the size of contact pad 201. This is more beneficial for devices where the top layer resistance manipulation will adversely affect the device performance. Here, the layer thickness between adjacent devices is reduced to make a higher resistance for the current to flow in the lateral direction. Etching process in this scheme can be done using dry etching, wet etching or laser ablation. Here, in many cases, the top metallic contact 201 may be used as the mask for the etching step.

[0050] Material conductivity modulation: in this case, referring to FIG. 3 the resistance of the top layer 101A between adjacent contact pads 201 is manipulated to limit the lateral current flow components. Counter doping and laser ablation modulation are examples of the processes that can be used for this case. Similar to the fully/partial modulation scheme, the top contact pads may be used as the mask for the modulation step.

[0051] In all above mentioned cases, the active device area is defined by the top contact pads formed on the device layer.

[0052] The definition of the active device area by the top contact pad may be more readily applied to devices with pillar structures. Referring to FIG. 4, the device layer 101 is a monolithic layer consist of pillar structures 401. Because the pillar structure 401 is not connected laterally, no lateral current component exist in the device layer 101. A good example of these devices is nanowire LEDs where the LED device consists of several nanowire LED structures fabricated on a common substrate. In this case, as it is shown in Fig. 4, the top metallic contact defines the active area of the LED structure.

[0053] Device layers with no lateral conduction is not limited to pillar structures and may be extended to device layers with separated active regions such as layers with embedded nano/micro spheres or other forms.

[0054] Referring to FIG. 5, where micro devices are defined using the top contact 502 formed on top of the device layer may be bonded and transferred to a system substrate 503 with contact pads 504. For example, the micro devices may be micro LEDs with sizes defined by the area of their top contact using any methods explained above. The system substrate may be a backplane with transistor circuitry to drive individual microLEDs.

[0055] Referring to FIG. 6, after transferring and bonding the device layer 602, a common top electrode 601 may be deposited on the structure. For some optical device layers, the common top contact may be a transparent conductive layer.

[0056] In another embodiment shown in FIG. 7, the top layer of the integrated structure may be a layer with low conductivity. For example this layer may be a buffer layer used during the growth of device layer 602. In this cases, the common electrodes 702 may be formed by making vias through the buffer layer 701 for example at the edge of the structure.

[0057] In one embodiment shown in FIG. 8, the device layer 602 may be patterned or modulated to further isolate micro devices electrically and/or optically.

[0058] Referring to FIG. 9, if the buffer layer 701 exists, to isolate micro devices the buffer layer needs to be patterned/ modulated as well. Similar to embodiment shown in FIG. 8, common contacts may be formed for example at the edge of the structure through vias in the buffer layer.

[0059] Additionally, referring to FIG 10, the isolation regions may be filled by a layer or an stack of optical layers 1001 to improve the performance of isolated micro devices. For example, in optical micro devices, the elements 1001 may some reflective material to better out coupling the light generated by micro devices in a vertical direction.

[0060] In LED display applications where display pixels are single device LEDs, each LED
should be bonded to a driving circuit which controls the current flowing into LED devices. Here, the driving circuit may be a TFT (Thin Film Transistor) backplane conventionally used in LCD or OLED display panels. Due to the typical pixel sizes (10-50 urn), the bonding may be performed at a wafer level scale. In this scheme, an LED wafer consists of isolated individual LED devices are aligned and bonded to a backplane which is compatible with LED wafer in terms of pixel sizes and pixel pitches. Here, the LED wafer substrate may be removed using various processes such as laser lift-off or etching. In this case, it is important to isolate the LED devices by dry etching and passivation layers. As an example, the present invention may be directed to a method of LED structure modification to simplify the integration of monolithic LED devices with backplane circuitry in an LED display. Furthermore, using the methods suggested by the present invention, one can increases the number of LED devices fabricated within a limited wafer area which results in lower fabrication cost and higher resolution for the LED
displays. Another advantage is to decrease the fabrication process steps. Additional advantages of this invention will be set forth in the description which follows. According to this invention LED devices in a substrate will be defined and bonded to an electronic backplane which drives these devices (pixels) in passive or active manner.

[0061] In one embodiment, the LED wafer is fabricated in which for example the p-type layer is the top layer. The p-type layer thickness and conductivity is manipulated to control the lateral conduction. This may be done by either etching of the pre-deposited p-layer or by depositing a thinner p-layer during the LED structure fabrication. For etching scenario, an accurate thickness control can be achieved using dry etching process. In addition, the material structure of the p-layer can be modified in terms of the layer doping level to increase the layer's lateral resistance. One should note that the top layer is not limited to the p-layer and can be extended to other top layers in an LED structure. As a result of this modification, the illumination area can be defined solely by the deposited conductive layer area on top of the p-type film.

[0062] To further limit the lateral illumination, the p-layer between two adjacent pixels fully or partially etched. This process step may be done after the conductive layer deposition in a process such as dry etching. In this case, the conductive layer may be used as a mask.

CA 02924157 2016-03-18 =

[0063] One important advantage of this scheme is to eliminate the wall passivation of pixels which results in higher number of pixels in a specific area of the wafer (higher PPI). This may also be translated to the less process steps and lower fabrication cost compared to fully isolated LEDs with wall passivation.

[0064] In another example, the top layer (here top p-type layer) may be partially or fully removed using laser ablation etching of GaN (same process as the one shown in FIG. 2). In this case, laser fluence defines the ablation rate and any thickness of p-type GaN
layer can be etched precisely. Example of such a laser is femtosecond lasers at RED / Infra-RED wavelengths.
Here the top metal contact or other protective layers are used as a mask in this process.
Alternatively, the laser beam size can be defined using special optics to match the desired etching region dimensions. In another example, shadow masks can be used to define the etching regions.

[0065] It should be noted that, the laser ablation etching may be extended to the other layers of the LED structure as well. In this case, the individual LED devices are isolated fully or partially from each other. In this scenario, it may be required to passivate LED etched walls by depositing dielectric layers.

[0066] In these examples, the n-layer contacts may be formed after bonding and removing the LED wafer to the backplane circuitry. In this scenario, the n-layer contact can be a transparent conductive layer to allow light illumination through this layer.
In this case, the n-layer contact may be common for all or part of the bonded LEDs (ame process as the one shown in FIG. 6).

[0067] These methods and advantages is not limited to the LED and display systems and may be used for other solid state devices such as sensors and other system substrate which drive these devices.

[0068] Alternatively, in some embodiments as shown in Figure 11, the system substrate contact pads / bumps 1102 may define the micro device areas. In this case, the device layer 1101 does not have any top contact to define the micro device area. The device layer 1101 on the substrate 501 is bonded to a system substrate 503 with an array of contact pads / bumps 1102 separated by insulation layer 1103. Here the bonding is made between the metallic contact pads 1102 and the device layer 1101. This bonding process may be performed using any bonding procedure such as but not limited to the heat/pressure bonding or laser heating bonding. The advantage of this procedure is the elimination of the alignment process during the micro device transfer to the system substrate. Here the micro device size 1104 and the pitch 1105 is partially defined by the size of the contact pad/bump 1102.

[0069] In one example, the device layer 1101 may be LED layers on a sapphire substrate 501 and the system substrate 503 may be a display backplane with circuitry required to drive individual microLEDs defined partially by the contact bumps on the backplane.

[0070] In another embodiment shown in FIG. 12, to precisely define the micro device size 1104 and micro device pitch 1105, a bank layer is deposited and patterned on the system substrate. The bank layer opening around each contact pad 1102 will fully define the micro device size 1104 and micro device pitch 1105.

[0071] In one embodiment, the bank layer may be an adhesive material.

[0072] After bonding the micro device substrate to the system substrate, as it is shown in FIG. 13, the micro device substrate 501 may be removed using various methods and a common contact may be formed above the integrated structure. In case of optical micro devices such as but not limited to microLEDs this common electrode may be a transparent conductive layer.

[0073] Referring to FIG. 14, in one embodiment, adhesive bonding elements 1401 may be used at the edge of the backplane to bond the device layer 1101 to the system substrate. In one case, the bonding elements 1401 may be used to temporarily hold the device layer to the system substrate for the bonding process of contact pads to the device layer.
In another case, the bonding element 1401 permanently attach the micro device layer 1101 to the system substrate.

[0074] In another embodiment shown in FIG. 15, the device layer 1101 may be patterned after transferring to the system substrate. The patterning may be designed and implemented to isolate micro devices electrically and/or optically. After patterning the device layer a common electrode may be deposited on the integrated substrate. In the case of optical devices such as LEDs, the common electrode may be a transparent conductive layer.

[0075] As shown in FIG. 16, after transferring and patterning the device layer 1101, additional layers may be deposited/formed between isolated micro devices to enhance the performance of micro devices. In one example, these elements may passivate the sidewalls of the isolated micro devices to help to vertical out coupling of light in the case of optical micro devices such as but not limited to the microLEDs.

[0076] In all above explained procedures, a protective layer may be finally formed on top of the integrated structure to act as a barrier and scratch resistance layer.

[0077] Also some can deposit an opaque layer after the micro device and patterns it to form the pixel. This layer can sit anywhere in the stack. The opening will allow the light to go through only the pixel array and reduce the interference.

Claims

WHAT IS CLAIMED IS:

1) A method of creating an array of vertical devices by modifying the lateral conduction without isolating the active layers

2) A vertical device according to claim 1 where it is a micro-led device

3) A method of diverging the current from the perimeter of a vertical device by modifying the lateral conduction

4) The method in claim 3 where the resistance of the conductive layers is modified by oxidation

5) The method of claim 3 where the lateral resistance of the conductive layers is modified by modifying the bias condition

6) the method of claim 3 where the contact is used as mask modify the lateral resistance of the conductive layer

7) A method of pixelating a display device consist of defining the pixel pad connection in backplane attaching the LED device with no current spreader or patterned current spreader layer to the backplane

8) A method of claim 7 where in bonding element is used to hold the LED device to the backplane