CA2916291A1 - Improving performance of vertical devices - Google Patents
Improving performance of vertical devices Download PDFInfo
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- CA2916291A1 CA2916291A1 CA2916291A CA2916291A CA2916291A1 CA 2916291 A1 CA2916291 A1 CA 2916291A1 CA 2916291 A CA2916291 A CA 2916291A CA 2916291 A CA2916291 A CA 2916291A CA 2916291 A1 CA2916291 A1 CA 2916291A1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/08—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
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- H01L33/0004—Devices characterised by their operation
- H01L33/0037—Devices characterised by their operation having a MIS barrier layer
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- H01L33/005—Processes
- H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
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- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
- H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
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- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
- H01L25/0756—Stacked arrangements of devices
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- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
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- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
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Abstract
A vertical current mode solid state device comprising a connection pad and side walls comprising a metal-insulator-semiconductor (MIS) structure, wherein leakage current effect of the vertical device is limited through the side walls by biasing the MIS structure.
Description
Modified LED wafer processing for micro-LED display applications This document discloses various methods for lateral conduction manipulation of vertical solid state devices. In a vertical solid state device, the current flow in the vertical direction predominantly defines the functionality of the device.
Light Emitting Diodes (LED) can be categorized as a vertical solid state device.
Here, the proposed fabrication methods are used to limit the lateral current flow of these devices. This devices typically have conductive layers at the two sides and functional layers in the middle.
N
=
MOW
N
A
0 Substrate Takeiai current Figure 1: A vertical solid state device schematic showing the lateral current components Figure 1 shows an exemplary schematic of a vertical solid state device with lateral current components.
The lateral current flow limitation can be divided into three main categories:
= At least one conductive layer resistance engineering = Fully/Partial etching of one or more conductive layers = Material conductivity modulation Conductive layer resistance engineering In this scheme, the semiconducting top layer of the vertical devices, just before the metallic contact, can be engineered to limit the lateral current flow by manipulating the conductivity or thickness of this layer. In one embodiment, when the top layer is a doped semiconducting layer, decreasing the concentration of active dopants and/or the thickness of this layer can significantly limit the lateral current flows.
Also, the contact area is defined to limit the lateral conduction.
In one case, the thickness of the conductive layer (or more than one conductive layers) is reduced. After that the contact layer is deposited and patterned.
This can be done on array device (non-isolated devices). As a result, the active layers are not etched or separate to create individual devices. Therefore, no defect is created at the perimeter of the isolated devices since the isolation is developed electrically by controlling the current flow. However, similar technique can be used on isolated devices to diverge the current from the perimeter of the device.
In another case, after the device is transferred to another substrate, the other conductive layer (or laters) is exposed. The thickness of this layer may be chosen to be high to improve device fabrication. However, after the layer is exposed the thickness can be reduced or the dopant density is decreased.
The main issue with this method is that some of the conductive layers may have also blocking role for the opposite charge. As a result, removing some of the conductive layers to thin the total conductive layer resistance may reduce the device performance. However, it can be very efficient on single layer engineering.
Fully/Partial etching of one or more conductive layer In this scheme, at least one of the conductive layer in the device can be etched fully or partially. In case of full etching, the etching stops till function layer.
In one embodiment, the contact layer deposited on top of conductive layer can be used as the mask for etching the conductive layer (or layers). Thus offering fewer processing step and self aligned structure.
This is more important for devices where the conductive layer resistance manipulation will adversely affect the vertical device performance. Here, the conductive layer thickness is reduced in selected area to make a higher resistance for the current to flow in the lateral direction. Etching process in this scheme can be done using dry etching, wet etching or laser ablation. Here, in many cases, the top contact layer can be used as the mask for the etching step.
Also, similar to previous process, after the bottom conductive layers are exposed either by transfer mechanism or etching of substrate, the same etching process can be performed on that. Here also, the contact can be used as the mask for etching the device.
Active Device Area , Part blity Etched top layer Substrate Figure 2: schematic of a device with partially etched top layer (top conductive Layer, for example p-or-n-doped layer in a diode) Material Conductivity Modulation In this case, the resistance of the conductive layers between is manipulated to limit the lateral current flow components (see Figure 3). Counter doping and laser ablation modulation are examples of the processes that can be used for this case.
Similar to the fully/partial modulation scheme, the top contact can be used as the mask for the modulation step.
In one case, the oxidation can be used. In one method, photoresist is patterned to match the oxidation area. Then the devices are exposed to oxygen (or other chemicals) to oxidize the area. Then, contact is deposited and patterned.
In another case, the contact is deposited and patterned first. Then the contact is used as mask for oxidation.
The oxidation can be done on isolated devices or non-isolated devices.
In another embodiment, prior to oxidation, the total thickness of the conductive layer(s) can be reduced. This can be done on selected area for oxidation only.
In another case, the oxidation can be done on the walls of the device (specially for isolated devices).
Also, the bottom layer can be modulated similarly after being exposed.
Actrve Device iRu nodUlatiofl tOP *ter Substrate Figure 3: Schematic of a device with top (conductive) layer modulation In another method, the material conductivity modulation can be done through electrical biasing. Here the bias for the area that require high resistance is modified.
In one case, the bias modulation can be done through an MIS (metal-insulator-semiconductor) structure (the metal layer can be replaced by any other conductive material). For example, to prevent the current from the contact to go further away from the contact laterally, around the contact an MIS structure is formed (this structure can be formed before or after the contact is in place). Figure 3 (b) shows a cross section of the MIS structure surrounding a contact layer (this can be done for more than one contact layer). By biasing the conductive layer of the MIS
structure to off voltage, no current will pass the structure laterally. The MIS structure can be formed on the device or can be part of the transferred substrate.
Gate Contact IMP
____________________________________________ Insulator bk (e.g. doped (or undoped) _________________________________________ :semiconductor) Figure 3 (B): using MIS structure to define the lateral conduction. Here, are some points that can be used to optimized the structure. However, an expert in the field knows that there are other optimization or structural configuration. the conductive layer can extend to both side of MIS structure (the dielectric can have extension over other conductive layer). the MIS structure can be open or closed structure. It can be continues or one piece structure.
In one case, the dielectric can be the oxidation layers from the last process.
Also another dielectric can be deposited on top of the oxidation layer. Also, a deposited dielectric can be used by itself.
In one case, the conductive layer(s) can be removed so that the dielectric is in contact with a semiconductor layer.
In another case, the MIS structure can be formed on the walls of the device as well for further deterring the charges getting to the edge of the device.
In one case, the device surface is covered by dielectric, the gate conductive layer is deposited and patterned for gate electrode, then the dielectric is patterned using gate electrode as a mask. In another case, the dielectric (insulator) is patterned first, and then the gate is deposited. here the gate and contact can be patterned at the same time or can be done separately.
Similar MIS structure can be made on the other side after it being exposed.
To improve the effectiveness of MIS, the thickness of conductive layers of the device can be reduced first.
The MIS method is more practical where selective etching or modulation of conductive layer on either side of vertical device is hard. Specially, if the etching or resistance modulation may damage the active layer.
In all aforementioned cases, the active device area is defined by the top contact area. In the following, these methods are explained in more details using LED
devices grown on a common sapphire substrate.
A light emitting diode structure and its manufacturing method for LED displays is disclosed. The LED comprises a substrate, a first doped layer (e.g. n-type layer), active layers and, another doped conductive layer (e.g. p-type layer) formed on the substrate. This invention is discussed with reference to a GaN-based LED but the invention can be used for any type of LEDs with different material system. In general, GaN LEDs are fabricated by depositing a stack of material on a sapphire substrate.
Figure 4 schematically illustrates a conventional gaN LED device. Referring to this image, this device includes a substrate, such as sapphire, an n-type GaN layer formed on the substrate or a buffer layer (for example GaN), an active layer such as multiple quantum well (MQW) layer and a p-type GaN layer. A transparent conductive layer such as Ni/Au or ITO is usually formed on the p-doped GaN layer for a better lateral current conduction. Conventionally, the p-type electrode such as Pd/Au, Pt or Ni/Au is then formed on the transparent conductive layer. Because the substrate (Sapphire) is insulator, one should expose the n-type GaN to make the contact to this layer. This step is usually done using a dry-etch process to expose the n-type GaN and then deposit the appropriate metal contacts.
p-c,:At.mt ________________________________________ 1" 11..,11r,r ' dud, ve mel=al p-GaN
Active Layer r----- a-contact n-GaN
Sapphire Substrate Figure 4: conventional GaN LED structure In LED display applications where display pixels are single device LEDs, each LED
should be bonded to a driving circuit which controls the current flowing into LED
devices. Here, the driving circuit may be a TFT backplane conventionally used in LCD
or OLED display panels. Due to the typical pixel sizes (10-50 urn), the bonding may be performed at a wafer level scale. In this scheme, an LED wafer consists of isolated individual LED devices are aligned and bonded to a back-plane which is compatible with LED wafer in terms of pixel sizes and pixel pitches. Here, the LED wafer substrate may be removed using various processes such as laser lift-off or etching.
Figure 5 illustrates this process.
t :44 5dCk P14411 LED= Devims t2a POrit ' =
Figure 5 fabrication process of an LED display In this process, it is important to isolate the LED devices by dry etching and passivation layers. However, full isolation of the devices creates defect in the active (functional) layers reducing the efficiency and imposing non-uniformities.
Since the perimeter to area of the micro devices is more substantial as the device becomes smaller, the effect of defects become more dominant.
In one embodiment, a monolithic LED device turns to individual micro-led without etching the active area and using lateral conductive manipulation. As a result, there is not side wall within micro-led to create defects. The surrounding walls across the array of LED can be extended till they have no effect on the peripheral LED
devices.
Or a set of dummy LED devices around the array can be used to reduce the effect of peripheral walls on the active micro-led devices.
In another embodiment, the technique can be used to avoid the current going through the side walls.
The present invention is directed to a method of LED structure modification to simplify the integration of monolithic LED devices with backplane circuitry in an LED
display while preserving device efficiency and uniformity. Furthermore, the present invention increases the number of LED devices fabricated within a limited wafer area which results in lower fabrication cost and higher resolution for the LED
displays.
Another advantage of this invention is to decrease the fabrication process steps.
Additional advantages of this invention will be set forth in the description which follows. According to this invention LED devices in a substrate will be defined and bonded to an electronic backplane which drives these devices (pixels) in passive or active manner. Although the following methods are explained with one type of LED
devices, they can be easily used with other LED and non-led vertical devices (such as sensors).
In one embodiment, the LED wafer is fabricated in which for example the p-type layer is the top layer (Figure 6). The p-type layer thickness and conductivity is manipulated to control the lateral conduction. This may be done by either etching of the pre-deposited p-layer or by depositing a thinner p-layer during the LED structure fabrication. For etching scenario, an accurate thickness control can be achieved using dry etching process. In addition, the material structure of the p-layer can be modified in terms of the layer doping level to increase the layer's lateral resistance.
One should note that the top layer is not limited to the p-layer and can be extended to other top layers in an LED structure. As a result of this modification, the illumination area can be defined solely by the deposited conductive layer area on top of the p-type film.
Duni, e;A
õ
"-tirrhi! hs iktiVt Sapphire Figure 6 LED wafer structure defined by the top contact In another embodiment shown in Figure 7, to further limit the lateral illumination, the p-layer between two adjacent pixels fully or partially etched. This process step may be done after the conductive layer deposition in a process such as dry etching. In this case, the conductive layer may be used as a mask.
=
ached P=r= _______________________________________________________ µ" I POT,' "4rIef *ONO ler I ___________ =v=twfa Ayer Sa pphire Figure 7 LED wafer structure defined by the top contact and partially etched p-layer One important advantage of this scheme is to eliminate the wall passivation of pixels which results in higher number of pixels in a specific area of the wafer (higher PPI).
This may also be translated to the less process steps and lower fabrication cost compared to fully isolated LEDs with wall passivation.
lenr' Tibiat:011 eltekiiiti Sari = -.44111 Arg , = : rr 5:1, eor active toys-- ___________________________ Sapphire Figure 8 LED wafer structure defined by the top contact and laser ablation etching of p-layer In another example, the top layer (here top p-type layer) may be partially or fully removed using laser ablation etching of GaN (Figure 8). In this case, laser fluence defines the ablation rate and any thickness of p-type GaN layer can be etched precisely. Example of such a laser is femtosecond lasers at RED / Infra-RED
wavelengths. Here the top metal contact or other protective layers are used as a mask in this process. Alternatively, the laser beam size can be defined using special optics to match the desired etching region dimensions. In another example, shadow masks can be used to define the etching regions.
It should be noted that, the laser ablation etching may be extended to the other layers of the LED structure as well. In this case, the individual LED devices are isolated fully or partially from each other. In this scenario, it May be required to passivate LED etched walls by depositing dielectric layers.
In above mentioned embodiments the n-layer contacts may by formed after the layer is exposed either by bonding and removing the LED wafer to the backplane circuitry (or any other substrate) or etching the substrate. In this scenario, the n-layer contact can be a transparent conductive layer to allow light illumination through this layer. In this case, the n-layer contact may be common for all or part of the bonded LEDs (Figure 9). However, transparent conductive layer ____________________________________________________ n-type layer active layer ____________________________________________________ p-type layer Backplane Figure 9 LED wafer with common transparent n-contact bonded to a backplane structure In cases where LED device structure is grown on a semiconducting buffer layer (for example undoped GaN), after LED transfer process, this buffer layer can be removed to access the n-type layer.
In one embodiment, as it is shown in Figure 9, the whole GaN buffer layer is removed using processes such as dry/wet etching.
In another case, the buffer layer is patterned around the edge thereby vias are made through buffer layer to make metallic contacts to the n-type layer (See Figure 10).
a 11.
Sackplane Figure 10 LED wafer with buffer layer and metallic n-contact vias.
To further decrease the lateral light propagation or adjust the device definition, as it is shown in Figure 11, the n-type layer is patterned by partially (or fully) removing this layer using the same structure as the front metallic contact (or its thickness is reduced). The n-type contact can be made by depositing a transparent conductive layer on top of this structure.
_____________________________________________________ 4.11, Wet Back plane Figure 11 Transferred LED wafer with patterned n-type layer.
In cases where the buffer layer is present, both this layer and the n-type layer is patterned (Figure 12). In one embodiment the patterned grooves may be further processed and filled with a material that improves the light propagation through the patterned area. A good example in this case is surface roughening to suppress total internal reflection and a reflective material to prevent the vertical light propagation in these regions.
rt4,,ope il'f activt2 Iyer ______ _______________________________________________________ p=type Lier ¨7 Backplane Figure 12 Transferred LED wafer with patterned n-type layer.
. Iftet kow MI .0 õ, ?9-tf-po IOW
¨ pe wer Backp lane Figure 13 Transferred LED wafer with patterned n-type layer and light management scheme.
In another example, another device layer can be transferred on top of existing transfer devices, in one case, the surface of the transferred device is planarized first. Then some via can be opened to create contact to the backplane (this contact can be at edge or in the middle of the arrays). Then the contact layer (traces and islands) are deposited and patterned. Finally the second set of devices are transferred. This process can continue for transferring more devices.
In another case, the top contact of first device can be shared with bottom contact of the second device. In this case, one can eliminate the planarization layer.
Figure 14 shows a stacked device using planraization layer and dielectric layer between two stacked devices to separate the devices, however, either of the layers can be eliminated.
Planarization (& dielectric) conductive layers Active Layer _J
Via 2 Contact __________ Planarization conductive layer -<:E Active Layer , Contact Substrate Figure 14 Stacked devices with isolation methods.
General terms The scope of this invention is not limited to LEDs. One can use these methods to define the active area of any vertical device Different methods such as laser lift-off (LLO), lapping, wet/dry etching may be used to transfer micro-devices from one substrate to another.
Micro devices may be first transfer to another substrate (from growth substrate) and then transferred to the system substrate.
This invention is not limited to any particular substrate.
Mentioned methods can be applied on either n-type or p-type layer. For the example LED
structures above n-type and p-type layers position is not limiting the scope of invention.
The methods can be mixed to create further improved results.
Claims Claim 1 A method of creating an array of vertical devices by modifying the lateral conduction without isolating the active layers Claim 2 A vertical device according to claim 1 where it is a micro-led device Claim 3 A method of diverging the current from the perimeter of a vertical device by modifying the lateral conduction Claim 4 The method in claim 3 where the resistance of the conductive layers is modified by oxidation claim 5 the method of claim 3 where the lateral resistance of the conductive layers is modified by modifying the bias condition claim 6 the method of claim 3 where the contact is used as mask modify the lateral resistance of the conductive layer
Light Emitting Diodes (LED) can be categorized as a vertical solid state device.
Here, the proposed fabrication methods are used to limit the lateral current flow of these devices. This devices typically have conductive layers at the two sides and functional layers in the middle.
N
=
MOW
N
A
0 Substrate Takeiai current Figure 1: A vertical solid state device schematic showing the lateral current components Figure 1 shows an exemplary schematic of a vertical solid state device with lateral current components.
The lateral current flow limitation can be divided into three main categories:
= At least one conductive layer resistance engineering = Fully/Partial etching of one or more conductive layers = Material conductivity modulation Conductive layer resistance engineering In this scheme, the semiconducting top layer of the vertical devices, just before the metallic contact, can be engineered to limit the lateral current flow by manipulating the conductivity or thickness of this layer. In one embodiment, when the top layer is a doped semiconducting layer, decreasing the concentration of active dopants and/or the thickness of this layer can significantly limit the lateral current flows.
Also, the contact area is defined to limit the lateral conduction.
In one case, the thickness of the conductive layer (or more than one conductive layers) is reduced. After that the contact layer is deposited and patterned.
This can be done on array device (non-isolated devices). As a result, the active layers are not etched or separate to create individual devices. Therefore, no defect is created at the perimeter of the isolated devices since the isolation is developed electrically by controlling the current flow. However, similar technique can be used on isolated devices to diverge the current from the perimeter of the device.
In another case, after the device is transferred to another substrate, the other conductive layer (or laters) is exposed. The thickness of this layer may be chosen to be high to improve device fabrication. However, after the layer is exposed the thickness can be reduced or the dopant density is decreased.
The main issue with this method is that some of the conductive layers may have also blocking role for the opposite charge. As a result, removing some of the conductive layers to thin the total conductive layer resistance may reduce the device performance. However, it can be very efficient on single layer engineering.
Fully/Partial etching of one or more conductive layer In this scheme, at least one of the conductive layer in the device can be etched fully or partially. In case of full etching, the etching stops till function layer.
In one embodiment, the contact layer deposited on top of conductive layer can be used as the mask for etching the conductive layer (or layers). Thus offering fewer processing step and self aligned structure.
This is more important for devices where the conductive layer resistance manipulation will adversely affect the vertical device performance. Here, the conductive layer thickness is reduced in selected area to make a higher resistance for the current to flow in the lateral direction. Etching process in this scheme can be done using dry etching, wet etching or laser ablation. Here, in many cases, the top contact layer can be used as the mask for the etching step.
Also, similar to previous process, after the bottom conductive layers are exposed either by transfer mechanism or etching of substrate, the same etching process can be performed on that. Here also, the contact can be used as the mask for etching the device.
Active Device Area , Part blity Etched top layer Substrate Figure 2: schematic of a device with partially etched top layer (top conductive Layer, for example p-or-n-doped layer in a diode) Material Conductivity Modulation In this case, the resistance of the conductive layers between is manipulated to limit the lateral current flow components (see Figure 3). Counter doping and laser ablation modulation are examples of the processes that can be used for this case.
Similar to the fully/partial modulation scheme, the top contact can be used as the mask for the modulation step.
In one case, the oxidation can be used. In one method, photoresist is patterned to match the oxidation area. Then the devices are exposed to oxygen (or other chemicals) to oxidize the area. Then, contact is deposited and patterned.
In another case, the contact is deposited and patterned first. Then the contact is used as mask for oxidation.
The oxidation can be done on isolated devices or non-isolated devices.
In another embodiment, prior to oxidation, the total thickness of the conductive layer(s) can be reduced. This can be done on selected area for oxidation only.
In another case, the oxidation can be done on the walls of the device (specially for isolated devices).
Also, the bottom layer can be modulated similarly after being exposed.
Actrve Device iRu nodUlatiofl tOP *ter Substrate Figure 3: Schematic of a device with top (conductive) layer modulation In another method, the material conductivity modulation can be done through electrical biasing. Here the bias for the area that require high resistance is modified.
In one case, the bias modulation can be done through an MIS (metal-insulator-semiconductor) structure (the metal layer can be replaced by any other conductive material). For example, to prevent the current from the contact to go further away from the contact laterally, around the contact an MIS structure is formed (this structure can be formed before or after the contact is in place). Figure 3 (b) shows a cross section of the MIS structure surrounding a contact layer (this can be done for more than one contact layer). By biasing the conductive layer of the MIS
structure to off voltage, no current will pass the structure laterally. The MIS structure can be formed on the device or can be part of the transferred substrate.
Gate Contact IMP
____________________________________________ Insulator bk (e.g. doped (or undoped) _________________________________________ :semiconductor) Figure 3 (B): using MIS structure to define the lateral conduction. Here, are some points that can be used to optimized the structure. However, an expert in the field knows that there are other optimization or structural configuration. the conductive layer can extend to both side of MIS structure (the dielectric can have extension over other conductive layer). the MIS structure can be open or closed structure. It can be continues or one piece structure.
In one case, the dielectric can be the oxidation layers from the last process.
Also another dielectric can be deposited on top of the oxidation layer. Also, a deposited dielectric can be used by itself.
In one case, the conductive layer(s) can be removed so that the dielectric is in contact with a semiconductor layer.
In another case, the MIS structure can be formed on the walls of the device as well for further deterring the charges getting to the edge of the device.
In one case, the device surface is covered by dielectric, the gate conductive layer is deposited and patterned for gate electrode, then the dielectric is patterned using gate electrode as a mask. In another case, the dielectric (insulator) is patterned first, and then the gate is deposited. here the gate and contact can be patterned at the same time or can be done separately.
Similar MIS structure can be made on the other side after it being exposed.
To improve the effectiveness of MIS, the thickness of conductive layers of the device can be reduced first.
The MIS method is more practical where selective etching or modulation of conductive layer on either side of vertical device is hard. Specially, if the etching or resistance modulation may damage the active layer.
In all aforementioned cases, the active device area is defined by the top contact area. In the following, these methods are explained in more details using LED
devices grown on a common sapphire substrate.
A light emitting diode structure and its manufacturing method for LED displays is disclosed. The LED comprises a substrate, a first doped layer (e.g. n-type layer), active layers and, another doped conductive layer (e.g. p-type layer) formed on the substrate. This invention is discussed with reference to a GaN-based LED but the invention can be used for any type of LEDs with different material system. In general, GaN LEDs are fabricated by depositing a stack of material on a sapphire substrate.
Figure 4 schematically illustrates a conventional gaN LED device. Referring to this image, this device includes a substrate, such as sapphire, an n-type GaN layer formed on the substrate or a buffer layer (for example GaN), an active layer such as multiple quantum well (MQW) layer and a p-type GaN layer. A transparent conductive layer such as Ni/Au or ITO is usually formed on the p-doped GaN layer for a better lateral current conduction. Conventionally, the p-type electrode such as Pd/Au, Pt or Ni/Au is then formed on the transparent conductive layer. Because the substrate (Sapphire) is insulator, one should expose the n-type GaN to make the contact to this layer. This step is usually done using a dry-etch process to expose the n-type GaN and then deposit the appropriate metal contacts.
p-c,:At.mt ________________________________________ 1" 11..,11r,r ' dud, ve mel=al p-GaN
Active Layer r----- a-contact n-GaN
Sapphire Substrate Figure 4: conventional GaN LED structure In LED display applications where display pixels are single device LEDs, each LED
should be bonded to a driving circuit which controls the current flowing into LED
devices. Here, the driving circuit may be a TFT backplane conventionally used in LCD
or OLED display panels. Due to the typical pixel sizes (10-50 urn), the bonding may be performed at a wafer level scale. In this scheme, an LED wafer consists of isolated individual LED devices are aligned and bonded to a back-plane which is compatible with LED wafer in terms of pixel sizes and pixel pitches. Here, the LED wafer substrate may be removed using various processes such as laser lift-off or etching.
Figure 5 illustrates this process.
t :44 5dCk P14411 LED= Devims t2a POrit ' =
Figure 5 fabrication process of an LED display In this process, it is important to isolate the LED devices by dry etching and passivation layers. However, full isolation of the devices creates defect in the active (functional) layers reducing the efficiency and imposing non-uniformities.
Since the perimeter to area of the micro devices is more substantial as the device becomes smaller, the effect of defects become more dominant.
In one embodiment, a monolithic LED device turns to individual micro-led without etching the active area and using lateral conductive manipulation. As a result, there is not side wall within micro-led to create defects. The surrounding walls across the array of LED can be extended till they have no effect on the peripheral LED
devices.
Or a set of dummy LED devices around the array can be used to reduce the effect of peripheral walls on the active micro-led devices.
In another embodiment, the technique can be used to avoid the current going through the side walls.
The present invention is directed to a method of LED structure modification to simplify the integration of monolithic LED devices with backplane circuitry in an LED
display while preserving device efficiency and uniformity. Furthermore, the present invention increases the number of LED devices fabricated within a limited wafer area which results in lower fabrication cost and higher resolution for the LED
displays.
Another advantage of this invention is to decrease the fabrication process steps.
Additional advantages of this invention will be set forth in the description which follows. According to this invention LED devices in a substrate will be defined and bonded to an electronic backplane which drives these devices (pixels) in passive or active manner. Although the following methods are explained with one type of LED
devices, they can be easily used with other LED and non-led vertical devices (such as sensors).
In one embodiment, the LED wafer is fabricated in which for example the p-type layer is the top layer (Figure 6). The p-type layer thickness and conductivity is manipulated to control the lateral conduction. This may be done by either etching of the pre-deposited p-layer or by depositing a thinner p-layer during the LED structure fabrication. For etching scenario, an accurate thickness control can be achieved using dry etching process. In addition, the material structure of the p-layer can be modified in terms of the layer doping level to increase the layer's lateral resistance.
One should note that the top layer is not limited to the p-layer and can be extended to other top layers in an LED structure. As a result of this modification, the illumination area can be defined solely by the deposited conductive layer area on top of the p-type film.
Duni, e;A
õ
"-tirrhi! hs iktiVt Sapphire Figure 6 LED wafer structure defined by the top contact In another embodiment shown in Figure 7, to further limit the lateral illumination, the p-layer between two adjacent pixels fully or partially etched. This process step may be done after the conductive layer deposition in a process such as dry etching. In this case, the conductive layer may be used as a mask.
=
ached P=r= _______________________________________________________ µ" I POT,' "4rIef *ONO ler I ___________ =v=twfa Ayer Sa pphire Figure 7 LED wafer structure defined by the top contact and partially etched p-layer One important advantage of this scheme is to eliminate the wall passivation of pixels which results in higher number of pixels in a specific area of the wafer (higher PPI).
This may also be translated to the less process steps and lower fabrication cost compared to fully isolated LEDs with wall passivation.
lenr' Tibiat:011 eltekiiiti Sari = -.44111 Arg , = : rr 5:1, eor active toys-- ___________________________ Sapphire Figure 8 LED wafer structure defined by the top contact and laser ablation etching of p-layer In another example, the top layer (here top p-type layer) may be partially or fully removed using laser ablation etching of GaN (Figure 8). In this case, laser fluence defines the ablation rate and any thickness of p-type GaN layer can be etched precisely. Example of such a laser is femtosecond lasers at RED / Infra-RED
wavelengths. Here the top metal contact or other protective layers are used as a mask in this process. Alternatively, the laser beam size can be defined using special optics to match the desired etching region dimensions. In another example, shadow masks can be used to define the etching regions.
It should be noted that, the laser ablation etching may be extended to the other layers of the LED structure as well. In this case, the individual LED devices are isolated fully or partially from each other. In this scenario, it May be required to passivate LED etched walls by depositing dielectric layers.
In above mentioned embodiments the n-layer contacts may by formed after the layer is exposed either by bonding and removing the LED wafer to the backplane circuitry (or any other substrate) or etching the substrate. In this scenario, the n-layer contact can be a transparent conductive layer to allow light illumination through this layer. In this case, the n-layer contact may be common for all or part of the bonded LEDs (Figure 9). However, transparent conductive layer ____________________________________________________ n-type layer active layer ____________________________________________________ p-type layer Backplane Figure 9 LED wafer with common transparent n-contact bonded to a backplane structure In cases where LED device structure is grown on a semiconducting buffer layer (for example undoped GaN), after LED transfer process, this buffer layer can be removed to access the n-type layer.
In one embodiment, as it is shown in Figure 9, the whole GaN buffer layer is removed using processes such as dry/wet etching.
In another case, the buffer layer is patterned around the edge thereby vias are made through buffer layer to make metallic contacts to the n-type layer (See Figure 10).
a 11.
Sackplane Figure 10 LED wafer with buffer layer and metallic n-contact vias.
To further decrease the lateral light propagation or adjust the device definition, as it is shown in Figure 11, the n-type layer is patterned by partially (or fully) removing this layer using the same structure as the front metallic contact (or its thickness is reduced). The n-type contact can be made by depositing a transparent conductive layer on top of this structure.
_____________________________________________________ 4.11, Wet Back plane Figure 11 Transferred LED wafer with patterned n-type layer.
In cases where the buffer layer is present, both this layer and the n-type layer is patterned (Figure 12). In one embodiment the patterned grooves may be further processed and filled with a material that improves the light propagation through the patterned area. A good example in this case is surface roughening to suppress total internal reflection and a reflective material to prevent the vertical light propagation in these regions.
rt4,,ope il'f activt2 Iyer ______ _______________________________________________________ p=type Lier ¨7 Backplane Figure 12 Transferred LED wafer with patterned n-type layer.
. Iftet kow MI .0 õ, ?9-tf-po IOW
¨ pe wer Backp lane Figure 13 Transferred LED wafer with patterned n-type layer and light management scheme.
In another example, another device layer can be transferred on top of existing transfer devices, in one case, the surface of the transferred device is planarized first. Then some via can be opened to create contact to the backplane (this contact can be at edge or in the middle of the arrays). Then the contact layer (traces and islands) are deposited and patterned. Finally the second set of devices are transferred. This process can continue for transferring more devices.
In another case, the top contact of first device can be shared with bottom contact of the second device. In this case, one can eliminate the planarization layer.
Figure 14 shows a stacked device using planraization layer and dielectric layer between two stacked devices to separate the devices, however, either of the layers can be eliminated.
Planarization (& dielectric) conductive layers Active Layer _J
Via 2 Contact __________ Planarization conductive layer -<:E Active Layer , Contact Substrate Figure 14 Stacked devices with isolation methods.
General terms The scope of this invention is not limited to LEDs. One can use these methods to define the active area of any vertical device Different methods such as laser lift-off (LLO), lapping, wet/dry etching may be used to transfer micro-devices from one substrate to another.
Micro devices may be first transfer to another substrate (from growth substrate) and then transferred to the system substrate.
This invention is not limited to any particular substrate.
Mentioned methods can be applied on either n-type or p-type layer. For the example LED
structures above n-type and p-type layers position is not limiting the scope of invention.
The methods can be mixed to create further improved results.
Claims Claim 1 A method of creating an array of vertical devices by modifying the lateral conduction without isolating the active layers Claim 2 A vertical device according to claim 1 where it is a micro-led device Claim 3 A method of diverging the current from the perimeter of a vertical device by modifying the lateral conduction Claim 4 The method in claim 3 where the resistance of the conductive layers is modified by oxidation claim 5 the method of claim 3 where the lateral resistance of the conductive layers is modified by modifying the bias condition claim 6 the method of claim 3 where the contact is used as mask modify the lateral resistance of the conductive layer
Claims
Claims Claim 1 A method of creating an array of vertical devices by modifying the lateral conduction without isolating the active layers Claim 2 A vertical device according to claim 1 where it is a micro-led device Claim 3 A method of diverging the current from the perimeter of a vertical device by modifying the lateral conduction Claim 4 The method in claim 3 where the resistance of the conductive layers is modified by oxidation claim 5 the method of claim 3 where the lateral resistance of the conductive layers is modified by modifying the bias condition claim 6 the method of claim 3 where the contact is used as mask modify the lateral resistance of the conductive layer
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA2916291A CA2916291A1 (en) | 2015-12-24 | 2015-12-24 | Improving performance of vertical devices |
| DE112016006010.6T DE112016006010T5 (en) | 2015-12-24 | 2016-12-23 | Vertical solid state devices |
| CN201680076089.7A CN108886073B (en) | 2015-12-24 | 2016-12-23 | Vertical solid state device |
| CN202111597807.4A CN114256392A (en) | 2015-12-24 | 2016-12-23 | Vertical solid state device |
| US15/389,728 US10784398B2 (en) | 2015-12-24 | 2016-12-23 | Vertical solid state devices |
| PCT/IB2016/057995 WO2017109768A1 (en) | 2015-12-24 | 2016-12-23 | Vertical solid state devices |
| US16/998,455 US12068428B2 (en) | 2015-12-24 | 2020-08-20 | Vertical solid state devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA2916291A CA2916291A1 (en) | 2015-12-24 | 2015-12-24 | Improving performance of vertical devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2916291A1 true CA2916291A1 (en) | 2017-06-24 |
Family
ID=59078331
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA2916291A Abandoned CA2916291A1 (en) | 2015-12-24 | 2015-12-24 | Improving performance of vertical devices |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA2916291A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE112016006010T5 (en) | 2015-12-24 | 2019-01-24 | Vuereal Inc. | Vertical solid state devices |
| FR3077931A1 (en) * | 2018-02-14 | 2019-08-16 | Centre National De La Recherche Scientifique | SEMICONDUCTOR DEVICE WITH RECOMBINANT SURFACE PASSIVATING STRUCTURE |
| WO2021016712A1 (en) * | 2019-07-30 | 2021-02-04 | Vuereal Inc. | High efficiency microdevice |
| US10998464B2 (en) * | 2018-08-10 | 2021-05-04 | Samsung Electronics Co., Ltd. | Flip-chip light emitting diode, manufacturing method of flip-chip light emitting diode and display device including flip-chip light emitting diode |
-
2015
- 2015-12-24 CA CA2916291A patent/CA2916291A1/en not_active Abandoned
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE112016006010T5 (en) | 2015-12-24 | 2019-01-24 | Vuereal Inc. | Vertical solid state devices |
| FR3077931A1 (en) * | 2018-02-14 | 2019-08-16 | Centre National De La Recherche Scientifique | SEMICONDUCTOR DEVICE WITH RECOMBINANT SURFACE PASSIVATING STRUCTURE |
| WO2019158430A1 (en) * | 2018-02-14 | 2019-08-22 | Centre National De La Recherche Scientifique | Semiconductor device with structure for passivating recombining surfaces |
| US10998464B2 (en) * | 2018-08-10 | 2021-05-04 | Samsung Electronics Co., Ltd. | Flip-chip light emitting diode, manufacturing method of flip-chip light emitting diode and display device including flip-chip light emitting diode |
| WO2021016712A1 (en) * | 2019-07-30 | 2021-02-04 | Vuereal Inc. | High efficiency microdevice |
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