WO2019158430A1

WO2019158430A1 - Semiconductor device with structure for passivating recombining surfaces

Info

Publication number: WO2019158430A1
Application number: PCT/EP2019/053027
Authority: WO
Inventors: Jean François GUILLEMOLES; Amaury DELAMARRE
Original assignee: Centre National De La Recherche Scientifique
Priority date: 2018-02-14
Filing date: 2019-02-07
Publication date: 2019-08-22
Also published as: FR3077931A1

Abstract

The present invention relates to a semiconductor device (110), comprising a p-n junction (12), said p-n junction comprising first and second substantially planar layers (16, 17) that make contact with each other, defining a stacking direction (Z), each of the first and second layers comprising a lateral edge (22, 24), said lateral edges being substantially in the extension of each other in the stacking direction. The device furthermore comprises a passivating structure (113), such that the first layer (16) is placed between said passivating structure and the second layer (17) in the stacking direction, said passivating structure being configured so as to generate, in the p-n junction, a substantially annular depletion region in proximity to the lateral edge of the first and second layers, said depletion region encircling a non-depleted central region.

Description

Semiconductor device

with passivation structure of the recombinant surfaces

The present invention relates to a semiconductor device, of the type comprising a pn junction, said pn junction comprising a first and a second substantially planar layers, respectively formed of a first and a second material including doping of opposite sign, said first and second layers being in contact with each other, defining a stacking direction, each of the first and second layers comprising a lateral edge, said lateral edges being substantially in an extension of one another according to the stacking direction.

Semiconductor devices, such as LEDs or solar cells, are frequently used to inject or collect large current densities. This results in Joule losses and temperature rises. For this purpose, it is advantageous to reduce the size of the surfaces of the devices, which makes it possible to reach higher current densities.

However, the edges of the semiconductor devices have defects that lead to recombinations. In particular, as shown in FIG. 1, a semiconductor device 10 of the state of the art comprises a pn junction 12, said pn junction comprising a first 16 and a second 17 substantially plane layers, in contact with one another. on the other and including doping of opposite sign. Lateral currents 52 flowing in the first layer 16 reach a peripheral surface 26 of the junction p-n 12. At the defects of said peripheral surface, recombinations 54 may occur. For semiconductor devices of reduced surface area, the ratio between the peripheral defect density and the useful area is increased, which decreases the efficiency of the devices.

To solve this problem, it is known to deposit passivating layers, for example based on sulfur elements for the materials III-V, on the peripheral surfaces 26 of the p-n junctions. These layers make it possible to reduce the recombination rate. Such a solution is described in particular in B. Brennan et al. al., Appt. Surf. Sci. 257, 201 1, 4082-4090 or in A. Gin et. al., Appl. Phys. Lett. 84, 2004, 2037-2039.

However, materials such as gallium arsenide (GaAs) are associated with very high rates of surface recombination. The effectiveness of the passivating layers is therefore insufficient.

It is an object of the present invention to provide a more efficient passivation method for peripheral surfaces of semiconductor devices. For this purpose, the subject of the invention is a semiconductor device of the aforementioned type, further comprising a passivation structure, such that the first layer is disposed between said passivation structure and the second layer in the stacking direction. said passivation structure being configured to generate in the first layer of the pn junction a substantially annular depletion zone near the lateral edge of said first layer, said depletion zone surrounding a non-depleted central zone.

According to other advantageous aspects of the invention, the semiconductor device comprises one or more of the following characteristics, taken individually or in any technically possible combination:

the passivation structure is configured so as to generate a depletion zone completely traversing the first layer in the stacking direction;

the passivation structure is configured to generate a continuous depletion zone along a periphery of the first layer;

the passivation structure comprises a passivation ring, formed of at least one band closed on itself and stacked with the pn junction, a minimum width of said passivation ring, perpendicular to the stacking direction, being preferentially greater or equal to 1 μm, more preferably greater than or equal to 20 μm and even more preferably greater than or equal to 50 μm;

the passivation ring comprises a first and a second stacked strip formed respectively of an electrically conductive material and an electrically insulating material, each of the first and second strips being closed on itself, the second strip being arranged between the first band and the first layer in the stacking direction, the passivation structure further comprising an electrode stacked with the pn junction at the central area and a means for applying an electrical voltage between the first band and the electrode, so as to generate the depletion zone;

the passivation ring comprises a strip formed of a material comprising fixed electric charges;

- A total thickness of the first and second layers in the stacking direction is less than or equal to 10 pm, more preferably less than or equal to 5 pm.

The invention will be better understood on reading the description which follows, given solely by way of nonlimiting example and with reference to the drawings in which:

FIG. 1, already described, is a partial view, in section, of a semiconductor device of the state of the art; FIG. 2 is a view from above of a semiconductor device according to a first embodiment of the invention;

- Figures 3 and 4 are partial views, in section, of the device of Figure 1, respectively in a first and a second configurations; Figure 5 is a sectional view of a device according to a second embodiment of the invention; and

- Figure 6 is a partial view, in section, of a device according to a third embodiment of the invention.

Figures 2, 3 and 4 show a device 1 10 semiconductor according to a first embodiment of the invention. FIG. 5 and FIG. 6 respectively represent semiconductor devices 210 and 310, according to a second and a third embodiment of the invention.

In the following description, the devices 1 10, 210 and 310 will be described simultaneously, the similar elements being designated by the same reference numbers.

The semiconductor device 1 10, 210, 310 comprises in particular a pn junction 12 and a passivation structure 1 13, 313. The semiconductor device 1 10, 210, 310 further comprises a first 14 and a second 15 electrodes. The first 14 and second 15 electrodes of the semiconductor device 310 are not shown in FIG.

The p-n junction 12, similar to the p-n junction of FIG. 1, comprises a first 16 and a second 17 substantially plane main layers. An orthonormal basis (X, Y, Z) is considered, the direction Z being substantially perpendicular to the first 16 and second 17 main layers. The first 16 and second 17 main layers are in contact with each other, stacked in the direction Z. In the remainder of the description, it is considered that the first layer 16 is above the second layer 17.

The first 16 and second 17 main layers are respectively formed of a first 19 and a second 20 materials including doping of opposite sign. By way of example, the first 19 and second 20 materials are based on gallium arsenide (GaAs).

In the remainder of the description, it is considered that the first 19 and second 20 materials are respectively n-doped and p-doped. However, the opposite can also be done as a variant.

The term "doping n" or "doping p" is understood to mean the fact of introducing, into a semiconductor material, impurities so as to increase at equilibrium, respectively the electron concentration and the hole concentration. Furthermore, in the present description, the term "doping" is understood in the broad sense and alternative embodiments implement first 19 and / or second intrinsic semiconductor materials.

Each of the first 16 and second 17 main layers comprises a lateral edge 22, 24. Said lateral edges are substantially in an extension of one another along Z, forming a peripheral surface 26 of the pn junction 12. In the As illustrated, the peripheral surface 26 is substantially parallel to Z. According to one variant, the peripheral surface may be inclined along Z, for example at an angle of between 0 ° and 30 °. According to another variant, the peripheral surface has a non-rectilinear shape according to Z.

As can be seen in FIG. 2, the lateral edges 22, 24 of the main layers of the device 1 10 have a substantially circular shape, so as to minimize the perimeter / area ratio of the pn junction 12. However, the invention makes it possible to reduce the peripheral recombination effects, variations (not shown) of the invention include side edges 22, 24 having any shape, for example substantially square or rectangular.

The semiconductor device 1 10, 210, 310 has an upper surface 30. In the embodiments of Figures 2-4 and 6, the upper surface 30 of the devices 1 10 and 310 is formed by the first main layer 16 of the pn junction 12.

In the embodiment of Figure 5, the device 210 further comprises secondary layers, stacked along Z with the first 16 and second 17 main layers. The device 210, for example a solar cell, comprises in particular a window layer 32 disposed over the first main layer 16 and forming the upper surface 30. The window layer 32 includes a doping of the same sign as the first main layer 16.

Preferably, the window layer 32 is made of a semiconductor material whose bandgap, or gap, is greater than the bandgap width of the first material 19 forming the first main layer 16.

The device 210 further comprises a substrate layer 34, as well as an intermediate layer 36 disposed between the second main layer 17 and said substrate layer 34. Preferably, each layer 34, 36 is made of a semiconductor material including a doping of the same sign as the second main layer 17, here a p-doping. Preferably, the intermediate layer 36 is made of a semiconductor material whose bandgap, or gap, is greater than the bandgap width of the second material 20 forming the second main layer 17.

In the embodiments of Figures 2-4 and 5, the first electrode 14 of the devices 1 10 and 210 is in contact with the upper surface 30. Said first electrode has for example a cross shape arranged in a plane (X, Y ) to leave free a majority proportion of said upper surface 30. Other shapes are possible for the first electrode 14, such as a linear shape.

In the embodiment of Figures 2-4, the first electrode 14 of the device 1 10 is metal. In the embodiment of FIG. 5, the first electrode 14 of the device 210 comprises an upper layer 40 of metal and a contact layer 42, made of a semiconductor material and disposed between the upper layer 40 and the upper surface 30. .

Furthermore, in the embodiments of Figures 2-4 and 5, the second electrode 15 of the devices 1 10 and 210 forms a lower surface of said devices. Said second electrode 15 is preferably made of metal, or else formed of a transparent conductive oxide such as ZnO.

The passivation structure 1 13, 313 of the semiconductor device 1 10, 210, 310 has the function of generating, in the first main layer 16 of the pn junction, a depletion zone 50 (FIGS. 4 and 6), substantially adjacent to the lateral edge 22. This depletion zone 50 increases the electrical resistance, and thus prevents the lateral currents 52 from reaching the peripheral surface 26 of the pn junction 12, so as to avoid surface recombinations 54. depletion zone 50 will be described more precisely below.

The passivation structure 1 13, 313 comprises a passivation ring 160, 360, formed of at least one band closed on itself and stacked along Z with the pn junction 12. The passivation ring 160, 360 is in particular arranged on the upper surface 30, surrounding a non-depleted central zone 61 of said pn junction 12.

In a plane (X, Y), a minimum width 62 of the passivation ring 160, 360 is greater than a diffusion length of the carriers whose passivation structure serves to cut the lateral transport. This diffusion length depends on the properties of the material constituting the p-n junction 12. For gallium arsenide, said diffusion length is of the order of 1 μm to a few tens of micrometers.

As a result, the minimum width 62 of the passivation ring 160, 360 is greater than or equal to 1 μm, preferably greater than or equal to 20 μm and more preferably greater than or equal to 50 μm. The passivation ring 160, 360 is disposed at a distance 64 from the peripheral surface 26 of the pn junction 12. This distance corresponds to a part of the pn junction disconnected by the depletion zone 50. The distance 64 is therefore preferably the lowest possible, according to the constraints of realization.

In the embodiment of Figure 6, the passivation ring 360 of the device 310 comprises a strip formed of a material 66 comprising fixed electrical charges. Said charges spontaneously generate the depletion zone 50 under the passivation ring 360.

By way of example, the material 66 is an aluminum oxide containing negative charges, in particular synthesized by the process described in document B. Hoex et. al., Appl. Phys. Lett. 91, 12107 (2007).

In the embodiments of Figures 2-4 and 5, the passivation ring 160 includes a first 70 and a second 72 stacked strips, respectively formed of an electrically conductive material and an electrically insulating material. Each of the first 70 and second 72 strips is closed on itself, the second strip 72 being arranged along Z between the first band 70 and the first main layer 16.

In addition, the passivation structure 1 13 of the devices 1 10 and 210 comprises a dipole 74 intended to apply a voltage at the level of the first band 70.

Said voltage is for example applied between the passivation ring 160 and the first 14 or the second electrode of the device 1 10, 210. In other words, said first 14 or second electrode is included in the passivation structure 1 13.

Preferably, the voltage is applied relative to the first electrode 14, which, as well as the passivation ring 160, is located on the upper surface 30 of the device 1 10, 210.

In the embodiments of Figures 2-4, 5 and 6, the passivation structure 1 13, 313 is configured to generate a continuous depletion zone 50 along the peripheral surface 26. As an alternative to the embodiment of Figure 6, the passivation ring 360 formed of the material 66 comprising fixed electrical charges, has one or more discontinuities along the peripheral surface 26.

The depletion zone 50 will now be described more precisely, on the basis of FIG. 4.

In a pn junction 12, a depletion layer 81, 82 is formed spontaneously around the interface between the first 16 and second 17 layers. Said depletion web comprises a first 81 and a second 82 portions, respectively disposed in the first 16 and in the second 17 layers. The distribution of depletion layer 81, 82 between the region p and the region n, ie the respective thicknesses of the first 81 and second 82 portions, depends in particular on the doping of the p-n junction 12.

The depletion layer 81, 82 is inherently weakly conductive. The lateral currents 52 described above flow in the non-depleted zone 83 of the first layer 16, or quasi-neutral zone, situated above the first portion 81.

For example, the extension w _n of the space charge area in the region n, here the thickness of the first portion 81, is given by the relation:

Similarly, the extension w _p of the space charge area in the region p, here the thickness of the second portion 82, is given by the relation:

These relationships can be found in such references as H. Mathieu and H. Fanet, Physics of Semiconductors and Electronic Components: Course and Corrected Exercises, Chapter 2 (Dunod, 2009).

e _sc is the dielectric constant of the first 19 or second material of the corresponding layer. Said dielectric constant is defined by the product of the relative dielectric constant of the material E _SCT and the vacuum permittivity e ₀ , equal to 8.8542.10 ¹² Fm ¹ . For example, for GaAs, _{SC> T} = il, S.

j¾ is the concentration of donor dopants, responsible for doping n, N _a is the concentration of acceptor dopants, responsible for doping p.

n _E is the intrinsic carrier density of the semiconductor. For the GaAs, ni = 3.10 ⁶ cm ^-3 .

q is the elemental charge, equal to 1.602.10 ¹⁹ C; k is the Boltzmann constant, equal to 1, 38.10 ²³ JK ¹ .

In the case of a pn junction 12 in GaAs, with doping Nd = 2.10 ¹⁷ cm ³ and Na = 2.10 ¹⁸ cm ³ , we obtain for example w _n = 88 nm and w _p = 8.8 nm.

Preferably, the depletion zone 50 implemented according to the invention integrally crosses Z, the quasi-neutral zone 83, in order to completely block the lateral currents 52 in the first layer 16 of the p-n junction.

w is the thickness of the depletion zone 50. The maximum maximum value w _max of the thickness w is substantially equal to:

Eg being the bandgap of the material, where N _D is the concentration of donor or acceptor dopants. For an n-doped GaAs layer at 2.10 ¹⁷ cm ³ , the maximum thickness w _max of the depletion zone 50 is substantially w _max = 95 nm.

In order to completely block the lateral currents 52, in the case where the first main layer 16 is n-type, it is therefore appropriate for said first main layer 16 to have a total thickness 84 according to Z less than

According to the examples above, the thickness 84 of the first layer 16 is therefore preferably less than 183 nm.

Moreover, the electric field E _isolated present in the insulating layer 72 is defined by the relation:

^£ i _solon s is the dielectric constant of the insulating material, defined by the product of the relative dielectric constant £ _iselantr material and the permittivity of vacuum ¾. For example, for IΆI ₂ 0 ₃ , e- _isoantr takes values substantially equal to 9.

w is the thickness of the depletion zone 50.

A material has a boundary breakdown field beyond which it becomes conductive. It is therefore appropriate to dimension the device so that the field in the insulator is less than this breakdown field. The breakdown field of AI ₂ 0 ₃ is between 5 and 10 MV / cm. If we consider a n-doped GaAs layer at 2.10 ¹⁷ cm ³ , whose maximum thickness of the depletion zone 50 is w _max = 95 nm, the resulting maximum field g _{i30 tat} in an insulating layer 72 of AI ₂ 0 ₃ is 0.38 MV / cm.

A very low interface state density at the interface 85 between the first main layer 16 and the insulating layer 72 leads to satisfactory sizing ranges. Such a very low interface state density is reached for example between the GaAs and G Al ₂ 0 ₃ deposited by ALD (atomic layer deposition), or between the Si and the Si0 ₂ , as described in the document JA del Alamo "Nanometer-scale electronics with III-V compound semiconductors," Nature, vol. 479, no. 7373, pp. 317-323, Nov. 201 1.

In general, the invention is particularly suitable for thin 12 pn junctions. More particularly, in the device 1 10, 210, 310, a total thickness of the first 16 and second 17 main layers according to Z is preferably less than or equal to 10 μm, more preferably less than or equal to 5 μm and is example of the order of 3 pm. This range of thicknesses is particularly preferred in the semiconductor technology based on gallium arsenide.

An exemplary embodiment, corresponding to the embodiment of Figure 5, will now be described in more detail using Table 1 below. Said table summarizes the materials of the different layers of the device 210, as well as their thicknesses according to Z:

Table 1

In the example above, the first band 70 of the passivation ring is formed of a first layer of titanium, deposited on the second strip 72 of aluminum oxide, as well as a second layer of gold, deposited on the first layer of titanium.

In the above example, the second electrode 15 is formed of a first silver layer, deposited on the substrate 34, as well as a second layer of gold deposited on the first silver layer.

The InGaP gap is larger than the GaAs gap. Thus, the window layer 32 passes the upper surface 30 of the solar cell 210 while preventing, in the case of n-doping, the diffusion of holes towards this surface 30. Similarly, the intermediate layer 36 prevents the diffusion of electrons from the second main layer 17 to the substrate 34.

In the GaAs, the n-type doping and the p-type doping are, for example, carried out by introducing impurities, respectively based on sulfur and zinc-based.

According to an alternative embodiment, the n and p dopings are inverted with respect to Table 1. A method of making and using solar cell 210 will now be described. First, the different layers mentioned in Table 1 are made on the substrate layer 34 by known methods. The insulating material of the second band 72 of the passivation ring 160 is for example deposited by ALD.

The dipole 74 is then connected respectively to the first band 70 of the passivation ring 160, and to the first layer 40 of the first electrode. At this point, the p-n junction 12 is in the same configuration as in FIG. 3, with no depletion zone at the right of the passivation ring 160.

A potential difference is then applied between said first band 70 and said first layer 40, so as to deplete the first main layer 16 as majority carriers in the right of the passivation ring 160. If the first main layer 16 is doped n, it is appropriate to apply, at the level of the passivation ring 160, a potential lower than that of the first electrode 14. The inverse is suitable for a first main layer 16 doped p.

The local depletion of the first main layer 16 as majority carriers forms the depletion zone 50, which blocks the lateral currents 52 and eliminates most of the recombinations 54 at the peripheral surface 26 of the solar cell 210. At this stage , the pn junction 12 is in the same configuration as in FIG. 4.

When the dipole 74 is disconnected from the solar cell 210, the depletion zone 50 disappears. In contrast, in the embodiment shown in Figure 6, the depletion zone 50 of the device 310 is permanent.

Claims

1. A semiconductor device (1 10, 210, 310) having a pn junction (12), said pn junction comprising a first (16) and a second (17) substantially planar layers, respectively formed of a first (16) 19) and a second (20) material including doping of opposite sign,

said first and second layers being in contact with each other, defining a stacking direction (Z),

each of the first and second layers comprising a lateral edge (22, 24), said lateral edges being substantially in an extension of one another in the stacking direction,

said device being characterized in that it further comprises a passivation structure (1 13, 313), such that the first layer (16) is disposed between said passivation structure and the second layer (17) in the direction of stack,

said passivation structure being configured to generate in the first layer (16) of the pn junction a substantially annular depletion zone (50) near the lateral edge (22) of said first layer, said depletion zone surrounding an area central (61) not depleted.

2. A semiconductor device according to claim 1, wherein the passivation structure (1 13, 313) is configured to generate a depletion zone integrally through the first layer (16) in the stacking direction.

The semiconductor device according to claim 1 or claim 2, wherein the passivation structure is configured to generate a continuous depletion zone (50) along a periphery (26) of the first layer. .

4. A semiconductor device according to claim 3, wherein the passivation structure comprises a passivation ring (160, 360) formed of at least one band closed on itself and stacked with the pn junction (12). )

a minimum width (62) of said passivation ring, perpendicular to the stacking direction, preferably being greater than or equal to 1 μm, more preferably greater than or equal to 20 μm and even more preferably greater than or equal to 50 μm.

The semiconductor device (1 10, 210) according to claim 4, wherein the passivation ring (160) comprises a first (70) and a second (72) stacked strip formed respectively of a material electrically conductive and electrically insulating material, each of the first and second strips being closed on itself, the second strip (72) being disposed between the first strip (70) and the first layer (16) in the direction of stack,

the passivation structure (1 13) further comprising: an electrode (14, 15) stacked with the p-n junction at the central area (61); and means (74) for applying an electrical voltage between the first band and the electrode so as to generate the depletion zone (50).

The semiconductor device (310) according to claim 4, wherein the passivation ring (360) comprises a strip formed of a material (66) comprising fixed electrical charges.

7. A semiconductor device according to one of the preceding claims, wherein a total thickness of the first (16) and second (17) layers in the stacking direction (Z) is less than or equal to 10 μm, plus preferably less than or equal to 5 μm.