JPH02256287A - Semiconductor light emitting device and usage thereof - Google Patents

Abstract

PURPOSE:To reduce a leakage current flowing through a buried region to obtain high output by effectively making junction to be formed of a current block layer and a current confinement layer into a reverse bias state. CONSTITUTION:A p-type lower part clad layer 2, an active layer 3, an n-type upper part clad layer 4, an n-type cap layer 5, an n-type current block layer 6 and a p-type current confinement layer 7 are provided on a p-type substrate 1. Then, luminous operation is performed by a bias to be impressed between the first and second electrodes 15a and 16, while a third electrode 15a connecting to a p-type region 7 forming the n1-p2 in the n1p2n3p lamination of a course reaching a lower part layer 2 from a cap region 5 through the buried regions 7 and 6 through the ohmic property or the Schottky barrier property and a fourth electrode 15b connecting to an n-type region 6 forming the n3p junction through the ohmic property or the Schottky barrier property are arranged. Thereby, a leakage current is reduced while improving output.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a highly efficient embedded semiconductor light emitting device.

[Conventional technology]

FIGS. 8(a) to 8(C) are cross-sectional views showing structural examples of a conventional embedded type semiconductor light emitting device. In the figure, 1 is a semiconductor crystal substrate, 2 is a lower layer (lower cladding layer) located below the light emitting layer 3, 4 is an upper layer (upper cladding layer) located above the light emitting layer 3, and 5 is an upper layer. This is the camp layer located above 4.

6 and 7 are buried regions located on both side walls of the light emitting layer 3. 8 is the first electrode, FIG. 8(a).

In (C), it is in ohmic contact with the cap layer 5 from above, and in (bl) it is in ohmic contact with the upper layer 4 from above. 9 is the second electrode; It comes into ohmic contact with the 3n type conductive semiconductor substrate l from its back surface, and in (C) makes ohmic contact with the lower layer 2 which contacts the insulating semiconductor substrate l from its top surface.

In the above configuration, the light emitting layer 3 forms a heterojunction with both the upper layer 4 and the lower layer 2 that sandwich it from above and below. That is, the energy gap width of the light-emitting layer 3 is set to be smaller than the energy gap widths of the upper layer 4 and the lower layer 2 that sandwich the light-emitting layer 3 from above and below. When electrons and holes, which are the majority carriers of 2, are injected into the light-emitting layer 3 in a forward polar state, they are more strongly confined within the light-emitting layer N3, and more efficient light emission is realized.

The forward bias state that enables the above-mentioned light-emitting operation means that the majority carriers in the upper layer 4 and the lower layer 2, which are vertically opposed to each other with the light-emitting layer 3 in between, flow toward the opposite sides. It is in a state where it flows into the light-emitting layer 3 located in the middle of the layer 2, and the forward direction in the above bias direction is the forward direction in a general homo pn junction when the light-emitting layer 3 is removed from the above layer structure. In the following, this is defined as the forward bias state of the device.

The buried region 6 connects the first electrode 8 and the second electrode 9 in the device of FIG. 8 placed in the above forward bias state,
Electrons and holes flow along electric lines of force that pass through the light-emitting layer 7 and do not pass through the light-emitting layer 3, and these electric lines serve as current paths through the buried regions 6.7 that do not contribute to the light-emitting operation of the device.

In the case of Fig. 8(a), on the bending electric lines of force there are npnp stacked junctions (hereinafter referred to as rn, p
In the case of (C), when written from above, a pnpn laminated junction (hereinafter referred to as rp3n, pin laminated junction) is formed,
The bias for these stacked junctions is
The t pr pr n junction and the n, p, p3 I'm junctions are all forward biased, and the pg nt nz p junction, which is the center of symmetry, is reverse biased. Furthermore, (in the case of bl, if written from above as above, if it passes through the upper layer 4, pn
It is obvious that the direction of the bias for this stacked junction corresponds to the case (C).

Pr nz p1n2 with the above distinction in notation
The forward bias (emission operation bias) condition applied to the p3n stacked junction and the nt pz nz p stacked junction is such that the center junction of the npnp stacked junction is reverse biased and the outer two junctions are reverse biased. Forward-biased bias state (hereinafter referred to as [forward-biased IJ of npnp junction]
) can be unified and expressed as

The state of the energy band in the forward bias state of the above npnp junction according to the prior art is shown in FIG.
This will be explained below by comparing with l.

10, 11 and 12 in the figure are the conduction band edge, valence band edge and Fermi unit, and 3n and p mean the conductivity type of each region. (2) and V mean the forward bias voltage and reverse bias voltage at the junction, and 13n and I are the junction.

FIG. 5 (al indicates a thermal equilibrium state in which no external bias is applied, and no current flows through the 3npnp junction. (bl indicates the forward bias state of the npnp junction in a device according to the prior art. The n region that is the outer part of the npnp junction structure (the n region that forms the junction
area) and n area (n area forming junction 1) are in direct ohmic contact with the first electrode 8 and the second electrode 9,
Alternatively, it is ohmically connected to the electrodes 8 and 9 through the n region and a region of the same conductivity type in contact with the n region. Therefore, the potentials of the n' pH region and the n region, which are the outer portions of the npnp junction structure, are approximately equal to the potentials of the electrodes 8 and 9, and are directly determined by the electrodes 8 and 9, so to speak.

However, the n region and the n region which are the inner parts in the above npnp junction structure correspond to the buried regions 6 and 7 as shown in FIG. The potential is not directly controlled by external elements and is in a floating state. In addition, the thickness of these buried regions 6 and 7 is approximately the same as the diffusion length of minority carriers, and once minority carriers enter, the thickness is such that they reach the junction on the opposite side from the side where they entered by diffusion. be.

[Problem to be solved by the invention]

Therefore, in the forward bias state of the npnp junction of the prior art device, as shown in FIG. 5(b), junctions r and m are forward biased, and n It is inevitable that electrons are injected from the region into the inner adjacent n region, diffuse to the junction (2), and further drift within the junction (2) to reach the inner n1Ji region. At the same time, in the above npnp junction structure, holes from the n region which is the outer part on the opposite side are
It is injected into the region, diffuses to junction H, and further junction ■
It is also unavoidable that the signal drifts inside and reaches the inner pwi region.

The light emitting layer in such a state is caused by the fact that the potentials of the n region and the n region in the inner part of the npnp junction structure are in a floating state as described above, and the npn
Most of the bias voltage applied to the p-junction is distributed as a forward bias voltage to junctions I and (2), and only a small amount is distributed as a reverse bias voltage to junction (4). In such a state, a reverse bias is applied to the connection in the npnp junction in the light emitting state of the device,
The state in which the current flowing through the implants 6, 7 is blocked is lost.

As described above, the problem with the npnp junction in the conventional device is that the junctions I and (2) are biased in the forward direction in the forward bias state, and the cause of this is the npnp junction described above.
It was shown that the potentials in the inner p region and n region adjacent to the n' pM region and p STA region, which are the outer parts of the pnp junction configuration, are in a floating state.

The present invention has been made in view of these points, and its object is to provide a semiconductor light emitting device in which leakage current flowing through the buried region is small. Another object of the present invention is to provide a semiconductor light emitting device with low dark value current and low drive current, and still another object of the present invention is to provide a semiconductor light emitting device that can realize high output.

[Means to solve the problem]

In order to solve these problems, the present invention includes a light-emitting layer sandwiched between at least two semiconductor heterojunctions on a semiconductor substrate, the upper layer of the light-emitting layer is p-type or n-type, and the light-emitting layer is of p-type or n-type. The lower layer located below and in contact with the substrate is n°
In a semiconductor light emitting device having a double hetero pn junction region of a p-type or a p-type, a buried region formed in contact with at least a side wall of the light emitting layer of the double hetero pn junction region, and a buried region of both the buried region and the double hetero pn junction region. a cap region overlying the region and a first cap region in ohmic contact with the cap region;
and a second electrode that ohmically contacts the lower layer or ohmically contacts the back side of the substrate that is electrically connected to the lower layer with low resistance, and the conductivity type of the cap region is set to a double hetero pn junction. The pn junction of the double hetero pn junction region is biased in the forward direction by the bias applied between the first electrode and the second electrode, and the conductivity type of the upper layer of the emissive layer in the region is the same as that of the upper layer of the emissive layer. P-type and n-type conductive layers are stacked in the buried region, and a p+ nz pz n stacked junction is formed in the path from the cap region to the lower layer via the buried region. or rl+ pz ns n stacked junction included, p+
In the case of nz p3 n stacked junction, pnz
I) A third electrode connected with ohmic or Schottky barrier properties to the n-type region forming the p+ nz junction in the 3 n stack, and an ohmic electrode connected to the p-type region forming the p3n junction in the [)+ nz p3 n stack. Alternatively, a fourth electrode connected with a Schottky barrier property is provided, and in the case of n+ pz nz n stacked junction, 3n
11) z rl+ n+ in the n stack; a third electrical conductor connected to the p-type region forming the Pz junction via ohmic or Schottky barrier properties; and 3n+ 1) n-type region forming the n)p junction in the 2 nz n stack. A fourth electric wire is provided to connect to the fourth electrode through ohmic or Schottky barrier characteristics.

[Effect]

The semiconductor light emitting device according to the present invention has extremely low leakage current. Therefore, the dark value current and drive current can be reduced, heat generation during laser oscillation can be suppressed, and high output can be achieved.

〔Example〕

The features of the present invention will be described using FIG. According to the present invention, the n region corresponding to the outer part in the npnp junction configuration in FIG.
A potential is applied directly to both the region and the n region, and this potential is a potential intended to prevent junctions 1 and 2 from becoming forward biased as the forward bias to the device increases. It is. Therefore, in the present invention, npn
Junction in p or pnpn junction configuration 1. A reverse bias can be applied to junction (2) without changing the junction potential of (III).

That is, the invention described in this specification has the characteristics of bringing the conductors on both sides forming the junctions I and ■ to the same potential (hereinafter referred to as "zero bias state"), that is, approaching the state shown in FIG. or a combination of these two features.

3 in the above zero bias state or reverse bias state
By suppressing the entry of electrons into the junction from the n6M region, which is the outer part of the npnp junction structure, and by suppressing the entry of holes from the n region, which is the outer part of the npnp junction structure, into the junction, the above-mentioned result can be achieved. This produces the effect that the current in the npnp junction can be cut off.

Further, in the forward bias state of the npnp junction caused by the bias voltage applied to the electrodes 8 and 9 (see FIG. 8), the relative relationship of the potentials between the n regions corresponding to the inner portions of the npnp junction structure is as follows. As shown in FIG. 5(C), this corresponds to a state in which a reverse bias is artificially directly applied to the junction H.

Next, a first embodiment of the semiconductor light emitting device according to the present invention will be described. FIG. 1 (tel) is a sectional view showing a first embodiment of a semiconductor light emitting device according to the present invention, and FIGS.
e) is a sectional view showing a cross section in each manufacturing process,
Figure 1 (al is a cross-sectional view of the wafer, Figure 1 (bl is a cross-sectional view of the wafer subjected to mesa etching, Figure 1 (C) is a cross-sectional view of the wafer subjected to buried growth, Figure 1 ( dl is a cross-sectional view of a wafer with mesa etching applied to the buried region;
FIG. 1(e) is a cross-sectional view of a wafer that has been subjected to electrode formation processing.

The structure of the embedded semiconductor light emitting device in this example will be explained below according to its manufacturing process.

First, as shown in Figure 1 (al), (100) plane p-type I
p-type 1n on nPi plate l by liquid phase epitaxial method
P lower cladding layer 2, InGaAs active layer 3
3n type! nP upper cladding layer 43n type [nP camp layer 5 is formed in sequence. Next, as shown in Figure 1(b),
Silicon nitride film 13 is deposited on the growth surface by plasma CVD method.
(110
) stripes of silicon nitride film having a width of 5 to 6 μm are formed to expose the semiconductor layer. Thereafter, the laminated semiconductor layers are processed using an etching solution such as bromethanol.

In this process, the part above the active layer 3 becomes an inverted mesa shape with an inverted triangular cross section due to anisotropic etching, and the part below the active layer 3 forms a parabola toward the substrate. It has a mesa shape.

Subsequently, as shown in FIG. 1(C), an n-type InP current blocking layer 6. P-type 1nP current confinement layer? 3
N-type! An nP cap layer 5 is sequentially grown to form a buried region. Next, the silicon nitride film 13 is removed and the silicon nitride film 13 is removed again.
An insulating film 14 made of O□ or the like is formed above the double hetero pn junction as shown in FIG.
Using the mask as a mask, the buried regions 6 and 7 are etched into a mesa shape. Next, an insulating film 14 made of Sin, etc. is formed again, and a contact hole is formed by a normal photolithography technique, as shown in FIG. 1 (Ill).

The n-type InP cap layer 5 and the p-type [nP current confinement layer 7 are connected through this contact hole.
A u/Zn electrode 15a (third electrode) and an Au/Zn electrode 15b (fourth electrode) connecting the n-type 1nP current blocking layer 6 and the p-type InP substrate 1 are formed. Furthermore, as shown in FIG. 1(e), after polishing the back surface of the substrate 1 to a wafer thickness of about 80 μm, □A u / G e / Ni electrodes 16 are formed on the polished surface of the substrate 1. An ohmic electrode is formed by vacuum evaporation and heat treatment at 420''C for 15 seconds in a hydrogen atmosphere.

Finally, reflective end faces are formed between the folds to complete the embedded semiconductor light emitting device. Note that the third electrode 15a is connected to the first electrode 8 (see FIG. 8) or to the camp layer 5 through ohmic or Schottky barrier characteristics, and the fourth electrode 15b is connected to the first electrode 8 (see FIG. 2 or to the substrate 1 in an ohmic or Schottky barrier manner.

FIG. 2 shows the energy band structure in the buried region of the buried semiconductor light emitting device manufactured in this example. In the figure, ■ is the substrate, 2 is the lower cladding layer, 5 is the cap layer, 6 is the current blocking layer, 7 is the current confinement layer, 10 is the conduction band edge, 11 is the valence band edge, and ■ is the junction. be. The vertical axis shows energy potential and the horizontal axis shows dimensions. At the junction (2) formed by the p-type InP current confinement layer 7 and the n-type 1nP current blocking layer 6, a pseudo-fermipotency cell φ1. A remarkable voltage drop is observed at φ, indicating that a depletion layer is formed. This is A u that combines the n-type InP cap layer 5 and the p-type 1nP current confinement layer 7
/Z n electrode 15a and A u /Z n that couples the n-type 1nP current blocking layer 6 and the p-type 1nP substrate 1
By forming the electrode 15b, the 3n type 1nP cap layer 5 and the p type 1nP current confinement layer 7 are at the same potential, and the n
The 1nP type current confinement layer 6 and the p-type InP substrate l have the same potential, and the junction formed by the p-type 1nP current confinement layer 7 and the n-type 1nP current blocking layer 6 is effectively reverse biased, resulting in a remarkable This is because it has a current blocking effect. As a result, leakage current flowing through the buried regions 6 and 7 can be reduced, and current can be injected into the active layer 3 with high efficiency.

FIG. 3 is a sectional view showing a second embodiment of the semiconductor light emitting device according to the present invention. The manufacturing process of this embodiment includes the step of etching the buried regions 6 and 7 into a mesa shape using the insulating film 14 as a mask, as shown in FIG. The steps up to are the same as those in the first embodiment, so their explanation will be omitted.Embedded region 6,
After cutting and notching 7 into a mesa shape, an insulating film 14 made of, for example, Sin is formed again, and a contact hole is formed by a normal photolithography technique, as shown in FIG. Then, through this contact hole, the n-type In
An Au/Zn electrode 15a that couples the P cap layer 5 and the p-type InP current confinement layer 7 and an Au/Zn electrode 15a that is in ohmic contact with the n-type InP current blocking layer 6.
Electrodes 15b are formed. Furthermore, as shown in Figure 3,
After polishing the back surface of the substrate 1 to a wafer thickness of approximately 80 μm, Au/Ge/Ni was deposited on the polished surface of the substrate 1.
The electric bridge 16 is vacuum deposited and heat treated at 420° C. for 15 seconds in a hydrogen atmosphere to form an ohmic electrode. Finally, reflective end faces are formed between the folds to complete the embedded semiconductor light emitting device.

FIG. 4 shows the energy band structure in the buried regions 6 and 7 of the buried semiconductor light emitting device manufactured in the second example, and the same or equivalent parts as in FIG. 2 are given the same reference numerals. It is. P-type! At the junction formed by the nP current confinement layer 6 and the n-type 1nP current blocking layer 7, a significant voltage drop is observed in the pseudo Fermi potentials φ1°φ2 of electrons and holes, and a depletion layer is formed. I understand. This is A u that combines the 3n type 1nP cap N5 and the p type 1nP current confinement layer 7.
By forming the A u /Z n electrode 15a and the A u /Z n electrode 15b on the n-type 1nP current blocking layer 6, the n Since the potential of the 1nP current confinement layer 6 can be controlled, the junction formed by the p-type 1nP current confinement layer 7 and the n-type InP current blocking layer 6 can be brought into a reverse bias state more effectively. This is because a current blocking effect can be achieved.

As a result, the leakage current flowing through the buried region 6.7 can be significantly reduced, and current can be injected into the active layer 3 with high efficiency.

FIG. 6 is a sectional view showing a third embodiment of the semiconductor light emitting device according to the present invention. The manufacturing process of this embodiment is the same as that of the first embodiment up to the step of etching the double heterojunction region using the insulation 1!13 as a mask, as shown in FIG. Following the etching of the double heterojunction region, an n-type 1nP current protection layer 6, F is formed on the sidewall of the mesa-shaped part.
An eF-type semi-insulating InP layer (one layer) 16, a p-type (nP) current confinement layer 73, and an n-type (1nP) cap layer 5 are sequentially grown to form a buried region. Hereafter, the same steps as in the first embodiment are repeated to complete the embedded semiconductor light emitting device.

Conventionally, in semiconductor lasers that use an Fe-doped semi-insulating InP layer as a current blocking layer, when electrons and holes are simultaneously injected into the Fe-doped semi-insulating InP layer, a recombination current flows, which does not necessarily result in high resistance. However, in this semiconductor light emitting device, since the pn junctions located above and below the Fe-doped semi-insulating InP layer are maintained in a zero bias state, the Fe-doped semi-insulating InPIi
There is no injection of carriers into the layer, and it functions as a complete high-resistance layer. As a result, leakage current flowing through the buried regions 6, 16.7 can be significantly reduced, and current can be injected into the active layer 3 with high efficiency.

FIG. 7 is a sectional view showing a fourth embodiment of the semiconductor light emitting device according to the present invention. As shown in FIG. 1 (dl), the manufacturing process of this embodiment is as shown in FIG.
Since this is the same as the embodiment, the explanation thereof will be omitted. After the buried regions 6 and 7 are etched into a mesa shape, an insulating film 14 made of Sin or the like is formed again, and a contact hole is formed by a normal photolithography technique. and,
Electrode 8. connected to cap 115 through this contact hole. an electrode tsb connected to the current blocking layer 6;
An electrode 15a connected to the current confinement layer 7 is formed. Hereafter, the same steps as in the first embodiment are carried out again to complete the embedded semiconductor light emitting device.

In the semiconductor light emitting device, since the potential of the current confinement layer 7 can be controlled independently, the junction formed by the current blocking layer 7 and the current confinement layer 6 can be brought into a reverse bias state more effectively. As a result, leakage current flowing through the buried regions 6 and 7 can be significantly reduced, and current can be injected into the active layer 3 with high efficiency.

Although the present invention has been described above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples and can be modified without departing from the gist thereof.

〔Effect of the invention〕

As explained above, in the semiconductor light emitting device according to the present invention, in the case of a pr nz p3 n laminated junction, pI nz in the pt ng p3 n laminated junction
A third electrode connected to the n-type region forming the junction by ohmic or Schottky barrier properties, and pI nz p1n2p
1) In the case of a 3n stacked junction, 3nI pt rl+ 1) In the case of a 3nI pt n3p stacked junction, 3nI pt rl+ 1) n1p2 in the stacked
a third electrode connected to the p-type region forming the junction by ohmic property or Schottky barrier property; and a fourth electrode connected to the n-type region forming the nz p-junction by ohmic property or Schottky barrier property in the 3nt Pgn3p stack; By arranging a The upper layer of h pI”n-type region 1 forming the z junction
Reduces the occurrence of leakage current flowing through the p-type region forming a pin junction and the leakage current flowing through the p-type region forming the cap region + f't'' junction. There is an effect that it can be done.

Similarly, a p-type region forming a 3nI pt junction and an n
Since the junction between the n-type region forming the p-junction is completely reverse biased and a depletion layer is formed, the upper layer of the light-emitting layer r nI p-type region forming the pz junction, I'
1ii) It is said that the occurrence of leakage current flowing through the n-type region forming the junction and the leakage current flowing through the cap region + nt p-type rectangular region forming the nt pt junction + n-type region forming the nz p junction can be reduced. effective.

Furthermore, since the leakage current is extremely small, the dark value current and drive current can be reduced, and a high-performance semiconductor light-emitting device can be provided.

Furthermore, since the dark value current and drive current can be reduced, heat generation during laser oscillation is suppressed, and high output is also possible.

Furthermore, pI nff1+ p3 n in the buried region
By bringing the junction or nI pg r ns p junction into a zero bias state, carrier injection into the buried region can be suppressed, which reduces leakage current flowing through the cladding layer, current blocking layer, and current confinement layer, and the cap layer. This has the effect of reducing the occurrence of leakage current flowing through the current blocking layer and the current confinement layer.

[Brief explanation of drawings]

1(e) are sectional views showing the manufacturing procedure of the first embodiment of the semiconductor light emitting device according to the present invention, and FIG.
3 is a cross-sectional view showing the second embodiment of the semiconductor light emitting device according to the present invention, and FIG. 4 is an explanatory diagram showing the energy band structure of the buried region of the device in FIG. 3. FIG. 5 is an explanatory diagram showing the energy band structure of the buried region; FIGS. 6 and 7 are cross-sectional views showing the third and fourth embodiments of the present invention; FIG. 1 is a sectional view showing a conventional semiconductor light emitting device. ■...p-type 1nP substrate, 2...p-type 1nP lower crat layer, 3...InGaAs active layer, 4...n-type 1
0P upper cladding layer, 5... n-type InP cap layer,
6...n-type 1nP current blocking layer, 7...p-type 1n
P current confinement layer, 13... silicon nitride film, 14.
・・Insulating layer, 15 a, l 5 b-Au/Zn electric scraping,
16- Au/Ge/Ni electrodes.

Claims (4)

[Claims] (1) A light-emitting layer sandwiched between at least two semiconductor heterojunctions on a semiconductor substrate, the upper layer of the light-emitting layer being p-type or n-type, and located below the light-emitting layer and in contact with the substrate. In a semiconductor light emitting device having a double hetero pn junction region in which the lower layer is n-type or p-type, a buried region formed in contact with at least a side wall of the light emitting layer of the double hetero pn junction region; a cap region overlying both regions of the double hetero pn junction region; a first electrode in ohmic contact with the cap region; and a first electrode in ohmic contact with or having low resistance electrical contact with the lower layer. a second electrode in ohmic contact with the back side of the substrate connected to the substrate, the conductivity type of the cap region being the same as the conductivity type of the upper layer of the light emitting layer in the double hetero pn junction region; The pn junction of the double hetero pn junction region is biased in the forward direction by a bias applied between the electrode and the second electrode, and electrons and holes flow into the light emitting layer and recombine to emit light, P-type and n-type conductive layers are stacked in the buried region, and a p_1n_2p_3n stacked junction or n_1p_2n is formed in a path from the cap region to the lower layer through the buried region.
_3p laminated junction is included, and in the case of the p_1n_2p_3n laminated junction,
a third electrode connected to the n-type region forming the p_1n_2 junction in the p_1n_2p_3n stack with an ohmic or Schottky barrier property, and the p_1n_2p_3n
In the case of the n_1p_2n_3p multilayer junction, a fourth electrode connected to the p-type region forming the p_3n junction in the stacked layer is provided with an ohmic or Schottky barrier property.
a third electrode connected to the p-type region forming the n_1p_2 junction in the n_1p_2n_3p stack by ohmic or Schottky barrier property; and the n_1p_2n_3p
A semiconductor light-emitting device characterized in that a fourth electrode is provided to connect an n-type region forming an n_3p junction in a stacked layer with an ohmic property or a Schottky barrier property. (2) In the semiconductor light emitting device according to claim 1, p_1
In the case of an n_2p_3n stacked junction, the third electrode is connected to the first electrode or ohmic or Schottky barrier to the p-type conductive layer forming said p_1n_2 junction, and the fourth electrode is connected to the second electrode. connect or the p_
It is connected to the n-type conductive layer forming the 3n junction using ohmic or Schottky barrier properties, and in the case of an n_1p_2n_3p stacked junction, the third
An electrode is connected to the first electrode or is ohmic or Schottky barrier connected to the n-type conductive layer forming the n_1p_2 junction, and a fourth electrode is connected to the second electrode or forming the n_3p junction. A semiconductor light emitting device characterized in that it is connected to a p-type conductive layer using ohmic or Schottky barrier properties. (3) In the semiconductor light emitting device according to claim 1 or claim 2, in the case of p_1n_2p_3n stacked junction, n_2
A semi-insulating layer is inserted between the p_3 layer and the n_1p
In the case of _2n_3p stacked junction, p, layer and n_3
A semiconductor light emitting device characterized in that a semi-insulating layer is inserted between the two layers. (4) In the semiconductor light emitting device according to claim 1, p_1
In the case of an n_2p_3n stacked junction, the potential of the third electrode is kept higher than the potential of the first electrode, and the potential of the first electrode is applied higher than the potential of the second electrode to cause light emitting operation, resulting in an n_1p_2n_3p stacked junction. In the case of joining, the third
1. A method of using a semiconductor light emitting device, characterized in that the potential of the first electrode is kept lower than the potential of the first electrode, and the potential of the first electrode is applied lower than the potential of the second electrode to emit light.