CN108878258A - 用于在沟槽的侧壁或平坦表面上选择性地形成氮化硅膜的方法 - Google Patents

用于在沟槽的侧壁或平坦表面上选择性地形成氮化硅膜的方法 Download PDF

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Publication number
CN108878258A
CN108878258A CN201810447158.1A CN201810447158A CN108878258A CN 108878258 A CN108878258 A CN 108878258A CN 201810447158 A CN201810447158 A CN 201810447158A CN 108878258 A CN108878258 A CN 108878258A
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CN
China
Prior art keywords
film
dielectric film
plasma
power
sidewall sections
Prior art date
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Pending
Application number
CN201810447158.1A
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English (en)
Chinese (zh)
Inventor
石川大
深泽笃毅
芝英郎
芝英一郎
上田真也
胡谷大志
S·全
Y·刘
Y·闵
S·金
J·崔
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ASM Japan KK
Original Assignee
ASM Japan KK
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Filing date
Publication date
Priority claimed from US15/592,730 external-priority patent/US10529554B2/en
Application filed by ASM Japan KK filed Critical ASM Japan KK
Publication of CN108878258A publication Critical patent/CN108878258A/zh
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/34Nitrides
    • C23C16/345Silicon nitride
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • C23C16/513Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using plasma jets
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/0254Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
CN201810447158.1A 2017-05-11 2018-05-11 用于在沟槽的侧壁或平坦表面上选择性地形成氮化硅膜的方法 Pending CN108878258A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/592,730 2017-05-11
US15/592,730 US10529554B2 (en) 2016-02-19 2017-05-11 Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches

Publications (1)

Publication Number Publication Date
CN108878258A true CN108878258A (zh) 2018-11-23

Family

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CN201810447158.1A Pending CN108878258A (zh) 2017-05-11 2018-05-11 用于在沟槽的侧壁或平坦表面上选择性地形成氮化硅膜的方法

Country Status (4)

Country Link
JP (1) JP7233173B2 (ja)
KR (1) KR20180124788A (ja)
CN (1) CN108878258A (ja)
TW (1) TWI766014B (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210313178A1 (en) * 2020-04-03 2021-10-07 Asm Ip Holding B.V. Method for forming barrier layer and method for manufacturing semiconductor device

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WO2011125733A1 (ja) * 2010-04-02 2011-10-13 株式会社アルバック 成膜装置
US8293642B2 (en) * 2010-04-27 2012-10-23 Hynix Semiconductor Inc. Method of manufacturing semiconductor devices
US20140113457A1 (en) * 2010-04-15 2014-04-24 Lam Research Corporation Plasma enhanced atomic layer deposition with pulsed plasma exposure
US20140349033A1 (en) * 2013-05-23 2014-11-27 Asm Ip Holding B.V. Method For Forming Film By Plasma-Assisted Deposition Using Two-Frequency Combined Pulsed RF Power
JP2015144268A (ja) * 2013-12-30 2015-08-06 ラム リサーチ コーポレーションLam Research Corporation パルスプラズマ暴露を伴うプラズマ原子層堆積
CN105448701A (zh) * 2014-09-24 2016-03-30 朗姆研究公司 均匀减少氮化硅膜的特征内湿法蚀刻速率的方法和装置
CN105762073A (zh) * 2015-01-05 2016-07-13 朗姆研究公司 用于各向异性钨蚀刻的方法和装置
US20170107621A1 (en) * 2015-10-15 2017-04-20 Asm Ip Holding B.V. Method for depositing dielectric film in trenches by peald
JP2017079327A (ja) * 2015-08-24 2017-04-27 エーエスエム アイピー ホールディング ビー.ブイ. SiN薄膜の形成

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JP2001237308A (ja) 2000-02-22 2001-08-31 Sanyo Electric Co Ltd 半導体装置の製造方法
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JP2008047620A (ja) 2006-08-11 2008-02-28 Mitsubishi Heavy Ind Ltd プラズマ処理方法、及び、プラズマ処理装置
US7758764B2 (en) * 2007-06-28 2010-07-20 Lam Research Corporation Methods and apparatus for substrate processing
JP2011003838A (ja) 2009-06-22 2011-01-06 Elpida Memory Inc 半導体装置の製造方法
JP6151335B2 (ja) 2011-01-14 2017-06-21 株式会社日立国際電気 半導体装置の製造方法、基板処理装置およびプログラム
JP2016539514A (ja) * 2013-11-04 2016-12-15 アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated 酸化物−ケイ素スタックのための付着性の改善
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US20140113457A1 (en) * 2010-04-15 2014-04-24 Lam Research Corporation Plasma enhanced atomic layer deposition with pulsed plasma exposure
US8293642B2 (en) * 2010-04-27 2012-10-23 Hynix Semiconductor Inc. Method of manufacturing semiconductor devices
US20140349033A1 (en) * 2013-05-23 2014-11-27 Asm Ip Holding B.V. Method For Forming Film By Plasma-Assisted Deposition Using Two-Frequency Combined Pulsed RF Power
JP2015144268A (ja) * 2013-12-30 2015-08-06 ラム リサーチ コーポレーションLam Research Corporation パルスプラズマ暴露を伴うプラズマ原子層堆積
CN105448701A (zh) * 2014-09-24 2016-03-30 朗姆研究公司 均匀减少氮化硅膜的特征内湿法蚀刻速率的方法和装置
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US20170107621A1 (en) * 2015-10-15 2017-04-20 Asm Ip Holding B.V. Method for depositing dielectric film in trenches by peald
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210313178A1 (en) * 2020-04-03 2021-10-07 Asm Ip Holding B.V. Method for forming barrier layer and method for manufacturing semiconductor device
US11830738B2 (en) * 2020-04-03 2023-11-28 Asm Ip Holding B.V. Method for forming barrier layer and method for manufacturing semiconductor device

Also Published As

Publication number Publication date
JP2018190986A (ja) 2018-11-29
KR20180124788A (ko) 2018-11-21
JP7233173B2 (ja) 2023-03-06
TW201900922A (zh) 2019-01-01
TWI766014B (zh) 2022-06-01

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