CN108666225B - 制造半导体装置的方法 - Google Patents

制造半导体装置的方法 Download PDF

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Publication number
CN108666225B
CN108666225B CN201810130900.6A CN201810130900A CN108666225B CN 108666225 B CN108666225 B CN 108666225B CN 201810130900 A CN201810130900 A CN 201810130900A CN 108666225 B CN108666225 B CN 108666225B
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layer
conductive layer
semiconductor chip
wire
pad electrode
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CN108666225A (zh
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柳生祐贵
磯崎诚也
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Renesas Electronics Corp
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Renesas Electronics Corp
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Abstract

本公开涉及制造半导体装置的方法。为了提供具有改进的可靠性的半导体装置。制造半导体装置的方法包括：将由铜组成的导线与在半导体芯片的焊盘电极上形成的导电层连接，对半导体芯片进行热处理，以及然后用树脂密封半导体芯片和导线。

Description

制造半导体装置的方法
相关申请的交叉引用
于2017年3月27日提交的日本专利申请No.2017-061806的公开内容(包括说明书、附图和摘要)的全部通过引用并入本文中。
技术领域
本发明涉及制造半导体装置的方法。具体地，本发明涉及在应用于制造半导体装置的方法时有效的技术，所述方法包括将铜线经由导电层与焊盘电极的表面连接。
背景技术
日本未经审查的专利申请公开No.2014-187073(专利文献1)公开了在由Al-Cu合金膜制成的焊盘电极上形成镀膜、将铜线连接到镀膜并由此将焊盘电极与铜线电连接的技术。镀膜由作为下层的OPM膜OP1和作为上层的OPM膜OP2组成。作为OPM膜OP1，公开了Ni膜、Ti膜、Cr膜等，以及作为OPM膜OP2，公开了Pd膜、Au膜等。
日本未经审查的专利申请公开No.2008-311316(专利文献2)涉及在其上具有由难熔金属制成的金属化层的陶瓷基板上安装半导体芯片并经由导线将半导体芯片与金属化层连接的技术。该文献公开了在形成在金属化层上的镍镀层和金镀层之间插入防扩散镀层并由此改进导线的连接强度的技术。
[专利文献1]日本未经审查的专利申请公开No.2014-187073
[专利文献2]日本未经审查的专利申请公开No.2008-311316
发明内容
本发明的发明人已经研究了通过用树脂密封具有焊盘电极的半导体芯片而获得的半导体装置。半导体装置的输入/输出端子经由导线与半导体芯片的焊盘电极电连接。这种导线经由在焊盘电极上形成的、由金属制成的导电层与焊盘电极电连接。
期望上述半导体装置具有改进的可靠性。
根据本文的描述和附图，其它问题和新颖的特征将是清楚的。
根据一个实施例的制造半导体装置的方法包括：将由铜组成的导线与在半导体芯片的焊盘电极上形成的导电层连接，对半导体芯片进行热处理，以及然后用树脂密封半导体芯片和导线。
根据一个实施例，能够提供具有改进的可靠性的半导体装置。
附图说明
图1是本实施例的半导体装置的平面图；
图2是沿图1的线A-A截取的截面图；
图3是本实施例的半导体芯片的平面图；
图4是作为本实施例的半导体元件的非易失性存储器单元的截面图；
图5是沿图3的线B-B截取的局部截面图；
图6是图5的局部放大图；
图7是示出本实施例的半导体装置的制造步骤的过程流程图；
图8是在本实施例的半导体装置的制造步骤期间本实施例的半导体装置的平面图；
图9是在图8之后的半导体装置的制造步骤期间半导体装置的平面图；
图10是在图9中所示的导电层OP的制造步骤期间图9中所示的导电层OP的截面图；
图11是在图10之后的导电层OP的制造步骤期间导电层OP的截面图；
图12是在图11之后的导电层OP的制造步骤期间导电层OP的截面图；
图13是在图12之后的导电层OP的制造步骤期间导电层OP的截面图；
图14是在图9之后的半导体装置的制造步骤期间半导体装置的平面图；
图15是在图14之后的半导体装置的制造步骤期间半导体装置的截面图；
图16是在图15之后的半导体装置的制造步骤期间半导体装置的透视图；
图17是在图16之后的半导体装置的制造步骤期间半导体装置的截面图；
图18是在图17之后的半导体装置的制造步骤期间半导体装置的截面图；
图19是在图18之后的半导体装置的制造步骤期间半导体装置的截面图；
图20是在图19之后的半导体装置的制造步骤期间半导体装置的截面图；
图21是在图20之后的半导体装置的制造步骤期间半导体装置的截面图；
图22示出了本实施例的密封树脂中所含有的硅烷偶联剂的化学结构；
图23示出了本实施例中的硅烷偶联剂与氧化镍层之间的反应机理；
图24是示出本实施例中的金膜的厚度与焙烧条件之间的关系的表；
图25是修改例1的半导体装置的局部截面图；
图26是图25的局部放大截面图；
图27是在修改例1的半导体装置的制造步骤期间修改例1的半导体装置的截面图；
图28是在图27之后的半导体装置的制造步骤期间半导体装置的截面图；
图29是在图28之后的半导体装置的制造步骤期间半导体装置的截面图；
图30是修改例2的半导体芯片的平面图；
图31是沿着图30的线C-C截取的截面图；以及
图32是修改例3的半导体装置的截面图。
具体实施方式
在下面描述的实施例中，为了方便起见，在需要的情况下在分成多个部分或实施例之后进行描述。除非另有特别指定，否则这些部分或实施例彼此不是独立的，并且它们中的一个可以是另一个的一部分或全部的修改例、细节、补充描述等。
在下面描述的实施例中，当提到部件的数字(包括数量、值、量、范围等)时，该数字不限于具体的数字，而是可以多于或少于该具体的数字，除非另有特别指定或原则上(principally)清楚该数字限于该具体数字。
另外，在下面描述的实施例中，不用说，构成部件(包括部件步骤等)并不总是必需的，除非另有特别指定或原则上清楚它是必需的。
类似地，在下面描述的实施例中，当提到构成部件的形状、位置关系等时，也涵盖形状等基本上近似或类似的部件，除非另外特别指定或原则上清楚不是那样。这也适用于上述的数字或范围。
在用于描述实施例的所有附图中，相同的构件原则上将由相同的参考标号或标记来识别，并且重复的描述将被省略。即使平面图也可以加阴影线，以便于对它们的理解。
(实施例)
<研究例>
首先，将描述由本发明的发明人研究的半导体装置。
在研究例的半导体装置中，由铝(Al)层组成的焊盘电极具有在其上的导电层，并且由铜(Cu)组成的导线经由这个导电层与焊盘电极电连接。在焊盘电极和导线之间插入导电层被称为OPM(焊盘上金属化，over pad metallization)工艺。
当将硬度高于由金(Au)组成的导线的硬度的由铜组成的导线直接热接触接合到由铝组成的焊盘电极并且将超声波施加到由铜组成的导线的球部分时，构成焊盘电极的铝的一部分被排开到导线的球部分与焊盘电极之间的接合部分的外围(该现象被称为“飞溅”)。发生这种飞溅之后，接着的是构成这个焊盘电极的铝的部分与位于其旁边的另一个焊盘电极的接触(短路)或者覆盖这个焊盘电极的部分(在这里为外围部分)的保护膜的破裂。
因此，本发明的发明人研究了使用硬度比铝和金(Au)的硬度高的镍(Ni)。具体地说，本发明的发明人研究了其中由镍制成的金属层(镍层)被由金制成的金属层(金层)覆盖的堆叠结构。通过在由镍制成的金属层上形成由金(Au)制成的金属层，可以实现导线和导电层之间的改进的连接可靠性。
本发明的发明人发现，当他们尝试将由铜组成的导线与由铝制成的焊盘电极电连接时，虽然导电层的主表面(导线接合表面)由金制成，但导线的接合强度降低。
通过本发明的发明人的研究已经揭示，在将导线与焊盘电极电连接的步骤(导线接合步骤)之前向焊盘电极施加热量(更具体而言，“温度×时间”)导致镍(元素)经由构成金层的金的晶粒边界(crystal grain boundary)沉积在(转移到)这个金层的表面(导线接合表面和侧表面)上，其中，镍(元素)构成位于金层正下方的镍层，金层被形成为覆盖镍层。还已经揭示，在导线接合步骤期间，当沉积在金层表面上的镍存在于构成导电层的金层的表面的导线连接区域中时，这种镍插入在导线和金层之间并且使导线的接合强度劣化。
为了防止镍沉积在金层的表面上，需要在镍层与金层之间插入例如由钯制成的金属层(钯层)。但是，本发明的发明人的进一步研究已经揭示，当采取措施以仅仅防止镍沉积在金层的表面上时，由树脂制成并在布线接合步骤之后执行的树脂密封步骤中形成的密封体与导电层的表面(特别是导线所接合到的主表面)分离。出现这个问题是因为，如上所述，导电层的主表面由作为贵金属的金制成。即使在之前的导线接合步骤中导线可以接合到导电层的主表面，当密封体与导电层的表面(特别是主表面)发生分离(界面分离)时，由于界面分离的影响，导线与导电层之间的接合部分也可能被损坏。
因此，本实施例的目标不仅在于改进在由铜组成的导线与在焊盘电极上形成的导电层之间的接合强度，而且在于改进在焊盘电极上形成的导电层与树脂(密封体)之间的粘合。
接下来，将以QFP(四方扁平封装)半导体装置作为示例来描述本实施例。更具体而言，将描述使用引线框(leadframe)作为其上将要安装半导体芯片3的基部材料的示例。
<半导体装置>
首先，将参考图1至6描述本实施例的半导体装置(半导体集成电路装置)SD的构造。图1是本实施例的半导体装置的平面图。图2是沿图1的线A-A截取的截面图。图3是本实施例的半导体芯片的平面图。图4是作为本实施例的半导体元件的非易失性存储器单元的截面图。图5是沿图3的线B-B截取的局部截面图。图6是图5的局部放大截面图。
如图1中所示，本实施例的半导体装置SD具有基本上矩形的密封体1和多个引线2。密封体具有四侧，并且从每一侧起，多个引线2从密封体1突出，使得它们在与该侧正交的方向上延伸。密封体1在其中心部分具有半导体芯片3。这个半导体装置SD是QFP(四方扁平封装)半导体装置。
在图2中，双点划线表示其上要安装半导体装置SD的安装基板的安装表面MB。半导体装置SD具有半导体芯片3、多个导线5、多个引线2以及密封体1。
半导体芯片3由例如由硅(Si)制成的半导体基板组成，并且具有多个半导体元件、多个布线、多个焊盘电极4(端子、外部电极、外部引线电极或电极焊盘)以及导电层OP。
半导体元件通过多个布线(金属布线)连接并且构成电路块。电路块(半导体元件)经由布线与焊盘电极4电连接。焊盘电极4经由导电层OP和导线5与引线2电连接。焊盘电极4经由导电层OP通过由例如铜(Cu)作为主要成分组成的导线(接合导线)5与由例如铜(Cu)作为主要成分组成的引线2连接。更具体而言，虽然没有示出，但是导线5所要连接的引线2的表面的一部分(区域)具有在其上的镀膜(金属膜)。经由这个镀膜，导线5与引线2电连接。如稍后将描述的图5中所示的，导线5具有球部分5a和导线部分5b。如从图2和5清楚的，导线部分5b在其一端具有球部分5a。球部分5a经由导电层OP与焊盘电极4连接。导线部分5b在其另一端(尖端部分)与引线2连接。
如本文使用的术语“由铜(Cu)组成”是指“是由铜(Cu)作为主要成分组成的金属”。由铜(Cu)作为主要成分组成的金属膜、引线或导线可以是含有包含微量金属添加物(1％或以下)的铜合金的金属膜、引线或导线。金属添加物的示例包括(Al)、镁(Mg)、钛(Ti)、锰(Mn)、铁(Fe)、锌(Zn)、锆(Zr)、铌(Nb)、钼(Mo)、钌(Ru)、钯(Pd)、银(Ag)、金(Au)、铟(In)、镍(Ni)、铂(Pt)、镧系元素金属和锕系元素金属。这些金属可以被单独或组合包含。在本实施例中使用的导线中，由例如铜(Cu)组成的导线的表面可以被不同于铜的金属(例如，钯)覆盖。
由例如环氧树脂组成的密封体1覆盖半导体芯片3、聚酰亚胺层PI、导电层OP、导线5、多个引线2、管芯焊盘(芯片安装部分)6和粘合剂层7。利用粘合剂层7使得半导体芯片3粘合到管芯焊盘6。如图2中所示，密封体1具有主表面(密封体主表面)1a、背表面(密封体背表面)1b以及连接在主表面1a与背表面1b之间的侧表面(密封体侧表面)1c。当半导体装置SD安装在安装基板上时，主表面(上表面)1a和背表面(底表面)1b平行于安装表面MB。安装在安装基板上的半导体装置SD的靠近安装表面MB的表面被称为“密封体背表面”(底表面)1b，远离安装表面MB的表面被称为“密封体主表面”(上表面)1a。
引线2各自具有主表面(上表面、引线主表面或导线接合表面)2a和背表面(底表面或引线背表面)2b。引线2各自由位于密封体1内部的内引线部分IL以及与这个内引线部分1L连接并位于密封体1外部的外引线部分OL组成。虽然未在图1中示出，但是引线2中的每个引线的内引线部分IL布置在半导体芯片3周围并从密封体1的侧表面1c延伸到半导体芯片3。外引线部分OL的主表面2a和背表面2b覆盖有焊料镀膜2c。引线2的外引线部分OL的侧表面(不是图2中由参考标号2d指示的表面，而是面向在图1中与其相邻的引线2的表面)也覆盖有焊料镀膜2c，但是外引线部分OL的端部2d没有用焊料镀膜2c覆盖。因此，存在有基部材料被暴露的部分。但是，端部2d的基部材料在其外围覆盖有焊料镀膜2c。导线5与引线2的内引线部分IL的主表面2a连接。
外引线部分OL具有鸥翼形状并且由以下组成：从内引线部分IL连续且线性地向密封体1的外部突出的突出部分，从突出部分起朝安装表面MB延伸的弯曲部分，以及基本上平行于安装表面MB的从弯曲部分起延伸并且经由安装焊料与安装基板连接的连接部分。
如图3中所示，在平面图中具有矩形形状的半导体芯片3具有彼此面对的侧3c和3d以及彼此面对的侧3e和3f。半导体芯片3在其主表面3a上具有焊盘电极组4c至4f，焊盘电极组4c至4f分别是沿着侧3c至3f的多个焊盘电极4的组件。在焊盘电极组4c中，沿着侧3c布置有两排焊盘电极4。焊盘电极4各自具有在其上的导电层OP，并且导线5的球部分5a与导电层OP连接。焊盘电极组4d、4e和4f也具有类似的构造。在用四个焊盘电极组4c至4f包围的区域中，半导体芯片3具有在平面图中具有矩形形状的聚酰亚胺层(有机绝缘膜)PI在其主表面3a上。聚酰亚胺层PI在以焊盘电极组4c至4f包围的区域中形成。分别地，聚酰亚胺层既不存在于半导体芯片3的角落处(例如，在焊盘电极组4c与焊盘电极组4e或4f之间的区域中或者在焊盘电极组4d与焊盘电极组4e或4f之间的区域中)，也不存在于焊盘电极组4c至4f与侧3c至3f之间的区域中。另外，在焊盘电极组4c至4f中的每个中的焊盘电极4之间的区域中不形成聚酰亚胺层PI。换句话说，如图5中所示，在聚酰亚胺层PI与侧3c至3f之间的并且其中没有焊盘电极4(和导电层OP)的区域中，密封体1与绝缘层11接触。
半导体元件包括例如MISFET(金属绝缘体半导体场效应晶体管)和非易失性存储器单元，并且例如位于半导体基板SB(参考图5)的覆盖有图3中的聚酰亚胺层PI的区域中。
如图4中所示，非易失性存储器单元MC具有控制栅极电极CG、存储器栅极电极MG、漏极区域MD以及源极区域MS。控制栅极电极CG经由栅极绝缘膜GI存在于半导体基板SB的主表面(元件形成表面)上，而存储器栅极电极MG经由存储器绝缘膜MZ存在于半导体基板SB的主表面(元件形成表面)上。在半导体基板SB中形成为将控制栅极电极CG和存储器栅极电极MG夹在其间的漏极区域MD和源极区域MS分别由半导体区域EX2和半导体区域SR2以及半导体区域EX1和半导体区域SR1组成。另外，存储器绝缘膜MZ具有三层堆叠结构，其中，例如，由氮化硅膜组成的绝缘膜MZ2夹在由氧化硅膜组成的绝缘膜MZ1和MZ3之间。绝缘膜MZ2是数据保持层，并且非易失性存储器单元MC的数据“1”或“0”由绝缘膜MZ2是否保持电荷来确定。
图5是沿图3的线B-B截取的截面图。图5还包括焊盘电极4和导电层OP的平面图。图6是图5的局部放大图。特别地，图6示出了导电层15的细节。
如图5中所示，半导体基板SB具有经由绝缘层10在其主表面(元件形成表面)上的焊盘电极4。如图4中所述，半导体基板SB在其主表面(元件形成表面)上具有多个非易失性存储器单元MC，并在其之上具有交替形成(布置)的多个布线层和多个绝缘层。布线层各自包括多个布线。焊盘电极4由在多个布线层中的最上面的一层中形成的布线的部分组成。在多个布线层中的除最上面的一层以外的布线层中形成的布线例如各自由例如以铜(Cu)作为主要成分组成的金属膜制成。在多个绝缘层之中，位于由铜组成的这个布线层与与其不同但类似地由铜组成的布线层之间的绝缘层(层间绝缘膜)使用具有3.0或以下的具体介电常数的绝缘膜，所谓的低k膜。另一方面，在多个绝缘层之中，位于焊盘电极4正下方的绝缘层10使用具有比层间绝缘膜的介电常数高的具体介电常数的绝缘膜，例如无机绝缘膜(诸如氧化硅膜)。图5没有图示多个布线层和层间绝缘膜。
半导体基板SB具有经由绝缘层10在其主表面上的焊盘电极4。焊盘电极4由铝膜制成，但是它可以具有堆叠结构，该堆叠结构在铝膜下方具有钛/氮化钛膜堆叠等并且在铝膜上具有氮化钛膜。铝膜可以含有微量(例如2wt％或以下)的铜等。
绝缘层10的主表面(上表面)10m和焊盘电极4覆盖有绝缘层11，绝缘层11用作保护膜，并且绝缘膜11的主表面(上表面)11m具有与焊盘电极4的厚度对应的台阶差(stepdifference)部分。这个台阶差部分存在于焊盘电极4的附近，并且同时存在于焊盘电极4和导电层OP的外部。换句话说，台阶差部分与焊盘电极4隔开等于绝缘膜11的厚度的距离。此外，绝缘层11中具有开口(开口部分)11a，从该开口(开口部分)11a中暴露焊盘电极4的主表面(上表面)4m的部分(使导电层与之接触的表面)。绝缘层11由氮化硅膜或通过在氧化硅膜上堆叠氮化硅膜获得的膜堆叠来制成。这意味着，类似于绝缘层10，绝缘层11由无机绝缘膜制成。
焊盘电极4在其上具有导电层OP，并且导线5经由这个导电层OP与焊盘电极4电连接。这个导电层OP在绝缘层11中形成的开口11a中与焊盘电极4接触，并且它进一步延伸到在焊盘电极4的外围部分上形成的绝缘层11的主表面(上表面)11m上。当构成焊盘电极4的铝膜具有氮化钛膜在其上时，在开口11a中移除电阻比铝膜的电阻高的钛膜，并且暴露铝膜的主表面。这意味着导电层OP与铝膜接触，中间没有氮化钛膜。
如图5中所示，导电层OP由从底层起依次为导电层12、13、14和15的4层组成。在本实施例中，导电层12、13、14和15分别由铬(Cr)、铜(Cu)、镍(Ni)和金(Au)组成。导电层15是用于抑制由镍组成的金属层(镍层)的氧化的层，并且它还是用于与导线5形成合金层的接合层。导电层14是应力松弛层，用于防止焊盘电极4在导线接合期间由于应力而变形。当通过电镀形成导电层14和15时，导电层13是用作电源层的层。导电层12是焊盘电极4与导电层13之间的防反应层。作为构成导电层12的材料，可以使用钛(Ti)以及铬。作为构成导电层13的材料，可以使用钯(Pd)以及铜。本实施例描述了使用电镀来形成导电层(镍层)14和导电层(金层)15，但是它们可以使用无电镀敷(electroless plating)来形成。在这种情况下，可以省略用作电源层的导电层(铜层)13和导电层(铬层)12的形成。但是，当使用电镀时，可以容易地使构成通过这种电镀形成的膜(即，金属层)的晶粒大于构成通过无电镀敷形成的膜(即，金属层)的晶粒。换句话说，通过电镀形成的膜的质量比通过无电镀敷形成的膜的质量更好。
导电层12、13、14和15在平面图中具有基本上相等的矩形形状，并且它们在相同的位置处彼此重叠。图5示出了导电层OP比焊盘电极4大的示例，但是导电层OP的尺寸可以与焊盘电极4相同，或者可以小于焊盘电极4。焊盘电极4和导电层OP优选地大于在绝缘层11中形成的开口(开口部分)11a。
接下来，图5中所示的参考标号R1表示属于导电层(金层)15的主表面(上表面，导线接合面)15m的并且使导线5的球部分5a与其接触的区域(导线接合区域)，以及，图5中所示的参考标号R2表示属于导电层(金层)15的主表面15m的并且使密封体1与其接触的区域(密封体接合区域)。简言之，区域R1是平面图中导电层15的中心部分，而区域R2连续地包围区域R1。导电层(金层)15在其主表面(上表面)15m的中心处具有凹部15a。这意味着导电层15的主表面15m由这个凹部15a的表面(导线所接合到的表面)以及位于这个凹部15a周围并且定位成比这个凹部15a的表面更靠近密封体1的主表面1a的表面来组成。导线5的球部分5a例如存在于这个凹部15a内部(参考图5的平面图)。但是，由金层制成的导电层15可以由于导电层具有低硬度而跨过凹槽15a及其周围的突起。由于导电层(镍层14)的硬度比导电层(金层)15的硬度高，因此球部分5a优选地位于导电层14的凹部内部。
如图5中所示，聚酰亚胺层PI存在于绝缘层11上，同时与绝缘层11的主表面(上表面)11m接触，并且聚酰亚胺层PI、导电层OP、导线5和绝缘层11覆盖有密封体1。密封体1由例如环氧树脂制成。密封体1例如含有硅烷偶联剂。
接下来，将参考图6的局部放大图详细描述参考图5描述的导电层OP以及导电层OP与导线5之间的接合部分。
如图6中所示，导电层15和导线5的球部分5a具有合金层17在其间，合金层17由构成导电层(金层)15的金(Au)和构成导线5的铜(Cu)组成。这意味着图5中的区域R1在其中具有图6中所示的合金层17。导电层15在其主表面15m和侧表面15s上具有金属氧化物层14a，该金属氧化物层14a由经由金层的晶粒边界15e从导电层14扩散的镍组成。这意味着金属氧化物层14a是氧化镍层(NiO)。虽然稍后详细描述，但是，由于这个金属氧化物层14a与含有硅烷偶联剂的密封体1接触，因此导电层15与密封体1之间的粘合力变得比没有金属氧化物层14a的粘合力更好，从而使得能够防止它们之间的分离。换句话说，存在于连续包围区域R1的区域R2中的这个金属氧化物层14a可以防止密封体1与导电层15的主表面15m和侧表面15s分离。例如，当侧表面15s没有金属氧化物层14a在其上时，分离发生在导电层15的侧表面15s上并且这种分离延伸到主表面15m。因此，在导线5与导电层15之间的接合部分处有发生损坏的风险。但是，在本实施例中，由于可以改进在导电层15的主表面15m和侧表面15s处导电层15与密封体1之间的粘合，因此可以防止导线5与导电层15之间的接合部分处的损坏。换句话说，导电层OP和密封体1可以具有改进的粘合，并且可以防止导线5与导电层OP的分离。由于区域R1没有金属氧化物层14a在其中，因此导线5和导电层OP可以以改进的强度被接合。
<制造半导体装置的方法>
接下来将参考图7至24来描述制造本实施例的半导体装置SD的方法。图7是示出本实施例的半导体装置的制造步骤的过程流程图。图8、9和14分别是在本实施例的半导体装置的制造步骤期间本实施例的半导体装置的平面图。图10至13分别是在图9中所示的导电层OP的制造步骤期间导电层OP的截面图。图15和17至21分别是在本实施例的半导体装置的制造步骤期间本实施例的半导体装置的平面图。图16是在本实施例的半导体装置的制造步骤期间本实施例的半导体装置的透视图。图22示出了本实施例的密封树脂中含有的硅烷偶联剂的化学结构。图23示出了本实施例中的硅烷偶联剂与氧化镍层之间的反应机理。图24是示出本实施例中的金膜的厚度与焙烧条件之间的关系的表。
首先，执行图7中所示的焊盘电极4形成步骤(S1)。
如图8中所示，提供具有以矩阵形式布置的多个半导体芯片3的半导体晶片WF。半导体芯片3中各自具有多个焊盘电极4。图8、9和14是半导体芯片3的简化视图。因此，例如焊盘电极4或导电层OP的数量与图3中所示的数量不同。
接下来，执行图7中所示的导电层OP形成步骤(S2)。
如图9中所示，在半导体芯片3中的每个的焊盘电极4上形成导电层OP。将参考图10至13来描述形成导电层OP的方法。
如图10中所示，形成绝缘层11，该绝缘层11覆盖绝缘层10的主表面(上表面)10m和焊盘电极4的外围部分，并且具有暴露焊盘电极4的主表面(上表面)4m的一部分的开口(开口部分)11a。如上所述，在本实施例中，绝缘层10和绝缘层11各自由无机绝缘膜组成。
接下来，如图11中所示，将由铬(Cr)组成的导电层(金属层或铬层)12a形成为使其与从绝缘层11暴露的焊盘电极4的主表面4m的部分(暴露部分或暴露表面)接触，并且在这个导电层12a上形成由铜(Cu)组成的导电层(金属层或铜层)13a。在本实施例中，导电层12a、13a各自使用例如溅射法来形成。
接下来，如图12中所示，在导电层13a上形成光致抗蚀剂层PR1，该光致抗蚀剂层PR1具有与上述由四个导电层(金属层)12、13、14和15组成的导电层OP对应的开口PRO1。接下来，通过电镀在开口PRO1中选择性地形成由镍制成的导电层(金属层、镍层)14和由金制成的导电层(金属层或金层)14。导电层(镍层)14具有例如1.5至2.0μm的厚度，以及，导电层(金层)15具有1.5μm或以上的厚度，优选地为1.5μm或以上并且为2.0μm或以下。导电层(镍层)14足够厚，以缓和在稍后描述的导线接合步骤期间对焊盘电极4的影响。导电层(金层)15足够厚，以便即使在稍后描述的图7的热处理步骤(S4)之后，也防止来自导电层(镍层)14的镍在导线接合步骤(S8)中造成导电层(金层)15中的晶粒边界扩散并从导电层(金层)15的主表面(与面向导电层14的表面相对的一侧上的表面或导线5所接合到的表面)15m暴露。
接下来，在移除上述光致抗蚀剂层PR1之后，移除从导电层14和导电层15暴露的区域中的导电层12a和导电层13a。在本实施例中，例如通过湿法蚀刻移除导电层12a和导电层13a的不与导电层14和导电层15重叠的相应部分。以这种方式，如图13中所示，形成具有由四个导电层12、13、14和15组成的堆叠结构的导电层OP(参考图5)。在本实施例中，所描述的是如图13中所示四个导电层12、13、14和15彼此具有相同矩形形状(外部尺寸)的情况，换句话说，所描述的是导电层12、13、14和15构成一个侧表面的情况。导电层12和导电层13的侧表面可以存在于导电层15的侧表面内部，这取决于上述湿法蚀刻步骤的条件(例如，时间)。
接下来，执行图7中所示的晶片测试1步骤(S3)。
本实施例的半导体芯片3在其中具有图4中所示的非易失性存储器单元MC。执行这个非易失性存储器单元MC的电路操作(诸如编程、擦除和读取)，并且测量非易失性存储器单元MC的擦除(或编程)时的阈值。这个晶片测试1步骤通过使探针PB与半导体芯片3的导电层OP接触来执行，如图14中所示。
接下来，执行图7中所示的热处理步骤(S4)。
本实施例的热处理步骤例如在250℃和16小时的条件下执行。这个热处理步骤是其中具有非易失性存储器单元的半导体晶片所特有的，并且被称为例如保持焙烧(retention bake)。如图15中所示，对容纳在炉体FB中的多个半导体晶片WF进行热处理。这种热处理引起加速的屏蔽(screening)，由此可以防止由于图4中所示的存储器绝缘膜MZ的缺陷而引起的数据保持故障(data retention failure)。如本文所使用的术语“数据保持”是指直到存储在非易失性存储器单元的存储器绝缘膜MZ中的数据丢失为止的时间。
如上所述，如本发明的发明人的研究所揭示的那样，构成导电层(镍层)14的镍的扩散(晶粒边界扩散)由于热的影响(例如，在如上所述的保持焙烧步骤中)而发生在覆盖导电层14的导电层(金层)15中。另一方面，在本实施例中，由于导电层(金层)15的厚度等于或大于导电层(镍层)14的厚度，因此在完成保持焙烧步骤的阶段没有镍沉积在导电层(金层)15的表面(特别地，表面积大于侧表面的表面积的导线接合表面)上。
接下来，执行图7中所示的晶片测试2步骤(S5)。
如图14中所示，通过使探针PB与半导体芯片3的导电层OP接触并且再次在非易失性存储器单元MC的擦除(或编程)时测量阈值，来检测是否存在数据保持故障。
接下来，执行图7中所示的晶片切割步骤(S6)。
如图16中所示，用切割刀片DB将半导体晶片WF分成多个半导体芯片3。
接下来，执行图7中所示的管芯接合步骤(S7)。
如图17中所示，经由粘合层7使单个的半导体芯片3粘合到引线框LF的管芯焊盘6上。管芯接合步骤伴随着例如在175℃的大约一个小时的热处理。这个步骤的热负荷比上述热处理步骤(S4)和稍后描述的热处理步骤(S9)的热负荷小得多，并且不影响稍后描述的镍的晶粒边界扩散。虽然这里未示出，但是引线框LF具有多个半导体装置形成区域，并且引线框LF在其上具有多个管芯焊盘6。
接下来，执行图7中所示的导线接合步骤(S8)。
如图18中所示，在半导体芯片3的主表面上形成的焊盘电极4经由导线5和在这个焊盘电极4上形成的导电层OP与引线2电连接。例如，本实施例的导线5是由铜(Cu)作为主要成分组成的导线，并且这个导线5通过球接合(也称为钉头接合)与导电层OP连接，其中球接合(也称为钉头接合)是组合使用热压接合和超声振动的方法。接下来将详细描述这个步骤。首先，使导线5的部分(这里是指图5中所示的球部分5a)与导电层OP的主表面(上表面或导线接合表面)OPm接触。将负荷和超声波各自施加到导线5的该部分，以在导线5的该部分与其接触的导电层OP的主表面(上表面或导线接合表面)OPm上形成合金层17(参见图6)，该合金层17由构成导线5的材料(在这里是铜)和构成定位为导电层OP的最上层的导电层(金层)15的材料(在这里是金)组成。在本实施例中，在导线5的球部分5a与导电层(金层)15之间形成的合金层17具有例如大约数个纳米(nm)的厚度。
重要的是，在导线接合步骤中，来自下面的导电层(镍层)14的镍还没有沉积在导电层(金层)15的表面15m和15s(特别是主表面15m)上，其中导电层(金层)15是图5中所示的导电层OP的最上层。由于在本实施例中导电层(金层)15具有如上所述的厚度，并且在导线接合步骤中导电层(金层)15没有氧化镍层在其表面上(特别是在导线与其连接的区域R1中)，因此可以形成无杂质的合金层17。换句话说，导线5和导电层OP可以以改进的强度接合。导线接合步骤伴随着例如在150-230℃的大约2至5分钟的热处理。与上述热处理步骤(S4)和稍后描述的热处理步骤(S9)中的热负荷相比，这个步骤中的热负荷小得多(意思是时间短得多)，并且不影响稍后描述的镍的晶粒边界扩散。
接下来，执行图7中所示的热处理步骤(S9)。
如图19中所示，例如在250℃、16小时和空气气氛的条件下，多个半导体芯片3被容纳在炉体FB中并且被热处理。这种热处理加速了镍的晶粒边界扩散。如图6中所示，沉积在导电层15的表面(主表面和侧表面)上的镍形成氧化镍层。这个氧化镍层与图6中所示的金属氧化物层14a对应。从导电层(金层)15的表面暴露(沉积在导电层(金层)15的表面上)的镍与空气中的氧键合，以形成这个金属氧化物层14a。如上所述(参考图5和6)，在区域(导线接合区域)R1以外的区域中形成金属氧化物层(氧化镍层)14a，换句话说，仅在暴露于空气中的氧的区域(密封体接合区域)R2中形成金属氧化物层(氧化镍层)14a。
在本实施例中，通过这个热处理，使镍有意地从导电层(金层)15的主表面(更优选地是主表面和侧表面)暴露，以形成金属氧化物层(氧化镍层)14a。此外，通过这个热处理步骤，在上述导线接合步骤(S8)中形成的合金层17的厚度增加到数十纳米(nm)，并且所得的层有助于改进导线5与导电体层OP之间的接合强度。
接下来，执行图7中所示的等离子体清洁步骤(S10)。
通过将其上已经安装有半导体芯片3的引线框LF(特别地，具有与其连接的导线5的导电层OP)暴露于氩(Ar)气气氛，即，如图20中所示的通过将在半导体芯片3的焊盘电极4上形成的导电层OP(特别地，导电层15)的表面暴露于等离子体(氩气等离子体)，在之前的热处理步骤(S9)中形成的金属氧化物层14a的表面上的羟基(hydroxyl group)的数量增加。这使得能够进一步改进导电层OP与由稍后描述的树脂密封步骤(S11)形成的密封体1之间的粘合(粘合性)。在本实施例中，描述了在热处理步骤(S9)之后但在树脂密封步骤(S11)之前执行的等离子体清洁步骤(S10)，但是这个等离子体清洁步骤并不总是必需的，这取决于上述导电层(金层)15的厚度或上述热处理步骤(S9)中的条件。
接下来，执行图7中所示的树脂密封步骤(S11)。
如图21中所示，通过将半导体芯片3和引线框LF安置在模具16的上力(upperforce)16a和下力(lower force)16b之间在配合表面处形成的空腔16c中并且用树脂(密封树脂)1r填充空腔16c而形成图2中所示的密封体1。这种树脂1r由例如含有硅烷偶联剂的环氧树脂组成。
在本实施例中，在树脂密封步骤之前(更具体地，在上面执行的导线接合步骤之后)，从导线5暴露的导电层(金层)15在其表面(特别是具有与密封体1的大接触面积的主表面)上具有金属氧化物层14a。这有助于改善由树脂1r制成的密封体1与导电层OP(特别是导电层15)之间的粘合。换句话说，可以抑制密封体1与导电层(金层)15的表面的分离。
在本实施例中，如图21中所示，使用例如传递模塑(transfer molding)来形成密封体1。可以代替地使用压缩模塑(compression molding)(将熔融的树脂置于空腔中、将半导体芯片和引线框浸入其中然后固化树脂的方法)。当使用传递模塑时，横向(水平方向)力(树脂填充压力)被施加到与焊盘电极4上的导电层OP连接的导线5，而在压缩模塑中，与传递模塑相比，不对导线5施加该横向力。通过使用压缩模塑来形成密封体1，可以进一步抑制导线的接合故障的发生。在压缩模塑中，树脂含有硅烷偶联剂也是重要的。
接下来，将参考图22至23描述密封树脂1r与在导电层15的表面上形成的金属氧化物层(氧化镍层)14a之间的接合机理。
如上所述，在图7中所示的热处理步骤(S9)之后，导电层15在其主表面和侧表面上具有氧化镍层。这个氧化镍层与空气中的水分反应，以在其表面上具有羟基。
图22示出了硅烷偶联剂的化学结构，这个图中的Y表示反应性官能团，诸如氨基、环氧基、甲基丙烯酸类基团(methacrylic group)、乙烯基或巯基，并且OR表示水解性基团，诸如OCH3、OC2H5或OCOCH3基。图23示出了硅烷偶联剂与氧化镍层之间的反应机理。首先，硅烷偶联剂的烷氧基与水分反应，并且水解成硅烷醇基。经由与无机颗粒的表面上的羟基氢键键合，它转移到无机颗粒的表面。然后，在脱水缩合反应之后，它与无机颗粒形成强共价键。图23中所示的无机颗粒与由图6中所示的氧化镍层组成的金属氧化物层14a对应。这意味着在导电层15的主表面和侧表面上形成的金属氧化物层与含有硅烷偶联剂的密封体1之间的粘合的改进。简言之，可以改进导电层OP 1与密封体1之间的粘合。
如上所述，在本实施例中，由金层组成并构成导电层OP的导电层15的厚度具有重要的意义。金层应当足够厚，以便即使在导电层OP形成步骤(S2)之后且在导线接合步骤(S8)之前将热负荷(热处理)施加到半导体芯片3时，也防止导电层14的镍由于界面扩散而被暴露在由金层组成的导电层15的主表面上以及形成氧化镍层，其中，步骤(S2)和步骤(S8)每个都在图7中示出。这意味着重要的是在导线接合步骤(S8)中镍还没沉积在导电层15的主表面上。此外，重要的是在图7中所示的树脂密封步骤(S11)开始时沉积在导电层15的主表面上的镍已经形成了氧化镍层。
图24示出了当金层的厚度和焙烧(热处理)条件改变时金层(Au)的表面的分析结果。该图示出了通过俄歇电子能谱(Auger electron spectroscopy，AES)检测导电层15的主表面的镍量的结果。例如，在250℃下16小时的焙烧条件与执行图7中所示的热处理步骤(S4)时的条件对应，而在250℃下32小时的焙烧条件与执行热处理步骤(S4、S9)时的条件对应。已经揭示的是，例如，当金膜具有1.5μm的厚度时，在图7中所示的热处理步骤(S4)之后，没有从导电层15的主表面检测到镍，以及，在图7中所示的热处理步骤(S9)中进一步执行了250℃下16小时的热处理后，检测到了镍。在本实施例中，当金层的厚度被设置为大约1.5μm时，可以改进导线5与导电层OP之间的接合强度以及导电层OP与密封体1之间的粘合。当金膜具有1.0μm的厚度时，根据本实施例的具有非易失性存储器单元的半导体装置的导线5与导电层OP之间的接合强度可能恶化。当金膜具有2.0μm的厚度时，导线5与导电层OP之间的接合强度增加，但是导电层OP与密封体1之间的粘合变得不足。因此，热处理步骤(S9)的时间必须增加。
已经基于实施例具体描述了由本发明的发明人作出的发明。但是，不用说，本发明不限于上述实施例，并且可以在不背离本发明的主旨的情况下以各种方式进行改变。以下将示出多个修改例。这些修改例可以根据需要组合使用。
在上述实施例中，已经描述了其中具有非易失性存储器单元的半导体芯片作为示例。在其中没有非易失性存储器单元的半导体芯片中，可以使得导电层15比导电层14更薄(例如，从0.5到1.0μm)，这是因为图7中所示的热处理步骤(S4)变得不必要。
<修改例1>
修改例1是上述实施例的导电层15的修改例。除了导电层15具有厚膜部分和薄膜部分之外，修改例1类似于上述实施例。因此，省略对于除导电层15以外的构件的描述。
图25是修改例1的半导体装置SD1的局部截面图。图26是图25的局部放大截面图。图27至29是示出修改例1的半导体装置SD1的制造步骤的截面图。
图25与上述实施例的图5对应，但是它省略了图5中所示的聚酰亚胺层PI和密封体1。如图25和26中所示，由金(Au)制成的导电层15b在平面图中具有在其中心处的厚膜部分15c和围绕厚膜部分15c的薄膜部分15d。如图25中所示，厚膜部分15c与区域R1和R3对应，而薄膜部分15d与区域R4对应。导线5的球部分5a与导电层15b之间的接合部分是区域(导线接合区域)R1，并且这个区域是厚膜部分15c的部分。密封体1与导电层15b之间的接合部分是区域(密封体接合部分)R3和区域(密封体接合部分)R4。区域R3是厚膜部分15c的部分，而区域R4与薄膜部分15d对应。
如图25的截面图所示，导电层15b的厚膜部分15c的厚度E大于薄膜部分15d的厚度D。如图26中所示，薄膜部分15d在其主表面15dm上具有金属氧化物层(氧化镍层)14a。厚膜部分15c在其主表面15cm上没有金属氧化物层14a。在图26中所示的导电层15b的厚膜部分15c中，来自导电层(镍层)14的镍的界面扩散在以实线示出晶粒边界15e的部分中发生，而没有扩散在虚线示出的部分中发生。这意味着图26中所示的区域R1是导线5和导电层15b之间的接合区域，并且它在其中具有如图26中所示的合金层17。在区域R1和R3中，导电层15c没有金属氧化物层14a在其主表面15cm上。另一方面，区域R4在其中具有金属氧化物层14a。在修改例1中，重要的是，在平面图中，导线5与导电层15b之间的整个接合区域在厚膜部分15c中形成，因为，当球部分5a突出到区域R4的薄膜部分15d时，导线5的球部分5a与导电层15b之间的接合强度降低。
在修改例1中，图7中所示的上述实施例的热处理步骤(S9)可以通过调整厚膜部分15c和薄膜部分15d的相应厚度而被省略。具体地说，在薄膜部分15d的主表面上沉积镍，并且在热处理步骤(S4)中在其上形成金属氧化物层14a。但是，在厚膜部分15c的主表面上没有沉积镍，并且在其上没有形成金属氧化物层15a。由于厚膜部分15c上不具有金属氧化物层14a，因此在图7中所示的导线接合步骤(S8)中导线5和导电层15b可以以改进的接合强度接合。另外，在图7的树脂密封步骤(S11)中，在薄膜部分15d上形成的金属氧化物层14a可以改进密封体1与导电层之间的粘合力。
对上述实施例的图24的参考已经揭示，有必要将薄膜部分15d的厚度调整为1.0μm，将厚膜部分15c的厚度调整为1.5μm或以上。
接下来，将描述制造修改例1的导电层15b的方法。
图27与上述实施例的图12对应。在导电层13a上形成其中具有开口PRO2的光致抗蚀剂层PR2之后，通过电镀在开口PRO2中连续地形成导电层(镍层)14和导电层(金层)15d。在这个时候，在导电层14上形成的金层具有与薄膜部分15d的厚度对应的厚度。
接下来，如图28中所示，通过形成具有与厚膜部分15c对应的开口PRO3的光致抗蚀剂层PR3然后通过电镀进一步在开口部分PRO3中形成导电层(金层)，形成厚膜部分15c。
然后，如图29中所示，光致抗蚀剂层PR2和PR3被移除。类似于上述实施例，通过移除在从导电层15b和导电层14暴露的区域中的导电层(铜层)13a和导电层(铬层)12a而形成图25中所示的导电层OP1。
<修改例2>
修改例2是上述实施例和修改例1的修改例。在这里，将其作为上述实施例的修改例进行描述。
图30是修改例2的半导体芯片的平面图。图31是沿图30的线C-C截取的截面图。如图30中所示，修改例2的半导体芯片3A在其角落部分处具有虚拟焊盘电极4g和虚拟导电层OPd。半导体芯片3A的角落部分是例如夹在沿彼此正交的侧3d和3e延伸的焊盘电极组4d和4e之间的区域。
如图31中所示，修改例2的半导体装置SD2具有由上述实施例的焊盘电极4、导电层OP和导线5组成的结构，以及由虚拟焊盘电极4g和虚拟导电层OPD组成的另一个结构。导线5不与虚拟导电层OPd连接，并且导电层15的整个主表面15m与密封体1接触。虚拟焊盘电极4g和虚拟导电层OPd具有类似于焊盘电极4和导电层OP的截面结构的截面结构。具体地说，由金组成并构成虚拟导电层OPd的导电层15在其主表面15m和侧表面15s上具有金属氧化物层14a，这改进了密封体1与虚拟导电层OPd之间的粘合。它们在平面形状上可以不同。特别地，虚拟导电层OPd可以具有比导电层OP的平面形状更大或者更小的平面形状。
虚拟导电层OPd是为了改进半导体芯片3A与密封体1之间的粘合而提供的。换句话说，通过在半导体芯片3A的角落部分处提供虚拟导电层OPd，可以改进半导体芯片3A与密封体1之间的粘合。
<修改例3>
修改例3是将上述实施例、修改例1或修改例2的半导体芯片安装在BGA(球栅阵列)封装上的示例，并且它将使用上述实施例作为示例来进行描述。更具体而言，将描述使用布线板WB作为其上将要安装半导体芯片3的基部材料的示例。
图32是修改例3的半导体装置的截面图。修改例3的半导体装置SD3具有布线板WB、半导体芯片3、密封体1以及焊球电极BE。布线板WB具有经由粘合层7在其主表面上的半导体芯片3，并且在半导体芯片3的主表面上形成的多个导电层OP经由导线5与在布线板WB的主表面上形成的端子电极LD1连接。半导体芯片3在其主表面上具有聚酰亚胺层PI，并且半导体芯片3、聚酰亚胺层PI、导电层OP、导线5和端子电极LD1覆盖有密封体1。另外，布线板WB在其背表面上具有与端子电极LD1连接的多个端子电极LD2，并且焊球电极BE与端子电极LD2连接。
在修改例3中，考虑到由于热引起的布线板WB的翘曲，优选地将图7中所示的上述实施例的热处理步骤(S9)的温度设置在200℃或以下。换句话说，优选地在比使用引线框制造半导体装置的方法中使用的温度低的温度执行热处理步骤(S9)。
上述实施例包括以下模式。
[附录1]
一种半导体装置，具有：
半导体基板；
第一焊盘电极，在半导体基板上形成；
导电层，具有在第一焊盘电极上形成的由镍层制成的第一层和在第一层上形成的由金层制成的第二层；
导线，由与第二层的主表面连接的铜组成；以及
密封体，覆盖导电层和导线，
其中，第二层的主表面具有导线所接合到的第一区域和作为除第一区域之外的区域并且具有在其中形成的氧化镍层的第二区域，以及
其中，在第二区域中，密封体与第二层的主表面接触。
[附录2]
根据附录1所述的半导体装置，
其中，第一区域在其中具有金和铜的合金层，以及
其中，第二区域在平面图中具有包围第一区域的外围的形状。
[附录3]
根据附录1所述的半导体装置，
其中，第二层具有其上具有氧化镍层的侧表面，
其中，侧表面与密封体接触。
[附录4]
根据附录1所述的半导体装置，
其中，第一焊盘电极由铝组成。
[附录5]
根据附录1所述的半导体装置，
其中，密封体由含有硅烷偶联剂的环氧树脂组成。
[附录6]
根据附录1所述的半导体装置，
其中，半导体基板在平面图中具有：
第一侧，面向第一侧的第二侧，连接第一侧与第二侧的第三侧，以及面向第三侧的第四侧；
第一焊盘电极组，具有在半导体基板之上形成并沿第一侧布置的多个第一焊盘电极；
第二焊盘电极组，具有在半导体基板之上形成并沿第二侧布置的多个第一焊盘电极；
第三焊盘电极组，具有在半导体基板之上形成并沿第三侧布置的多个第一焊盘电极；以及
第四焊盘电极组，具有在半导体基板之上形成并沿第四侧布置的多个第一焊盘电极。
[附录7]
根据附录6所述的半导体装置，还具有聚酰亚胺层，该聚酰亚胺层在平面图中在用第一焊盘电极组、第二焊盘电极组、第三焊盘电极组和第四焊盘电极组包围的区域中形成并与密封体接触。
[附录8]
根据附录1所述的半导体装置，还具有：
第二焊盘电极，在半导体基板之上形成；以及
导电层，具有由镍层组成并在第二焊盘电极之上形成的第三层和由金层组成并在第三层之上形成的第四层，
其中，第四层的整个主表面与密封体接触。
[附录9]
根据附录8所述的半导体装置，
其中，半导体基板在平面图中具有矩形主表面，以及
其中，第二焊盘电极布置在矩形主表面的角落部分处。

Claims (13)

1.一种制造半导体装置的方法，所述方法包括以下步骤：
(a)提供具有半导体芯片的半导体晶片，所述半导体芯片包括：
半导体基板，
焊盘电极，在所述半导体基板之上形成，以及
导电层，包括：
第一层，由镍层组成并且在所述焊盘电极之上形成，以及
第二层，由金层组成并且在第一层之上形成；
(b)将由铜组成的导线与所述导电层连接；
(c)在步骤(b)之后，对所述半导体芯片执行第一热处理；以及
(d)在步骤(c)之后，用树脂密封所述半导体芯片和所述导线，并且形成密封体，
其中，第二层的主表面具有第一区域以及除第一区域以外的第二区域，所述导线接合到第一区域，
其中，在步骤(c)中，通过在第二层的主表面上沉积来自第一层的镍，在第二区域中形成氧化镍层，以及
其中，在第二区域中，所述密封体与第二层的主表面接触。
2.根据权利要求1所述的方法，
其中，所述树脂具有含有硅烷偶联剂的环氧树脂。
3.根据权利要求1所述的方法，
其中，在步骤(b)中，在第一区域中，在第二层的主表面上没有沉积来自第一层的镍，并且在第二层的主表面之上形成铜和金的合金层。
4.根据权利要求1所述的方法，
其中，在将多个半导体芯片存储在炉体中时执行步骤(c)。
5.根据权利要求4所述的方法，
其中，步骤(c)在250℃的温度执行16小时。
6.根据权利要求1所述的方法，还包括在步骤(c)和(d)之间的步骤：
(e)对第二层的主表面执行氩等离子体处理。
7.根据权利要求1所述的方法，
其中，所述半导体芯片具有在其中的非易失性存储元件，
所述方法还包括在步骤(a)和(b)之间的步骤：
(f)对所述半导体芯片执行第二热处理，以及
其中，在步骤(b)中，在第一区域中，在第二层的主表面上没有沉积来自第一层的镍，并且在第二层的主表面之上形成铜和金的合金层。
8.一种制造半导体装置的方法，包括以下步骤：
(a)提供半导体芯片，
所述半导体芯片包括焊盘电极和在所述焊盘电极之上形成并且与所述焊盘电极连接的导电层，
所述导电层包括第一金属层和在第一金属层之上形成并且与第一金属层接触的第二金属层，
所述焊盘电极由比第一金属层软的材料组成，
第一金属层由镍作为主要成分组成，
第二金属层由金作为主要成分组成，以及
第二金属层是所述导电层的最上层；
(b)在步骤(a)之后，将导线经由所述导电层电连接到所述半导体芯片的所述焊盘电极，
所述导线由铜作为主要成分组成；
(c)在步骤(b)之后，焙烧所述半导体芯片，并由此在属于构成所述导电层的第二金属层的表面的并且所述导线不与其接触的区域中形成氧化物膜；以及
(d)在步骤(c)之后，用树脂密封所述半导体芯片和所述导线，并且使所述树脂与所述氧化物膜接触。
9.根据权利要求8所述的方法，
其中，在步骤(a)中提供的所述半导体芯片还具有半导体基板和在所述半导体基板的主表面之上形成的存储器电路，
其中，第二金属层的厚度等于或大于第一金属层的厚度，以及
其中，在步骤(a)之后但在步骤(b)之前，焙烧所述半导体芯片。
10.根据权利要求8所述的方法，
其中，所述第一金属层具有1.5μm至2.0μm的厚度。
11.根据权利要求8所述的方法，
其中，所述第二金属层具有1.5μm或以上的厚度。
12.根据权利要求11所述的方法，
其中，所述第二金属层具有1.5μm至2.0μm的厚度。
13.根据权利要求8所述的方法，
其中，在步骤(c)之后但在步骤(d)之前，将等离子体暴露于第二金属层的表面。
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