CN1086618A - 运算装置 - Google Patents
运算装置 Download PDFInfo
- Publication number
- CN1086618A CN1086618A CN93118166.6A CN93118166A CN1086618A CN 1086618 A CN1086618 A CN 1086618A CN 93118166 A CN93118166 A CN 93118166A CN 1086618 A CN1086618 A CN 1086618A
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- CN
- China
- Prior art keywords
- mentioned
- data
- arithmetic
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- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6502—Reduction of hardware complexity or efficient processing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/3961—Arrangements of methods for branch or transition metric calculation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
- H03M13/4107—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing add, compare, select [ACS] operations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
- H03M13/413—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors tail biting Viterbi decoding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
- H03M13/4161—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management
- H03M13/4169—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management using traceback
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6502—Reduction of hardware complexity or efficient processing
- H03M13/6505—Memory efficient implementations
Landscapes
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Data Mining & Analysis (AREA)
- Mathematical Analysis (AREA)
- Computational Mathematics (AREA)
- Mathematical Optimization (AREA)
- Algebra (AREA)
- Pure & Applied Mathematics (AREA)
- Databases & Information Systems (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Error Detection And Correction (AREA)
Abstract
Description
Claims (12)
Applications Claiming Priority (9)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25956392A JP3191442B2 (ja) | 1992-09-29 | 1992-09-29 | ビタビ復号用演算装置 |
JP259563/92 | 1992-09-29 | ||
JP259563/1992 | 1992-09-29 | ||
JP14494893A JPH0722969A (ja) | 1993-06-16 | 1993-06-16 | 演算装置 |
JP144948/93 | 1993-06-16 | ||
JP144948/1993 | 1993-06-16 | ||
JP19109293A JPH0746145A (ja) | 1993-08-02 | 1993-08-02 | 演算装置 |
JP191092/1993 | 1993-08-02 | ||
JP191092/93 | 1993-08-02 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN99106651.0A Division CN1237046A (zh) | 1992-09-29 | 1999-05-18 | 用于实现误码纠错用卷积码的维特比译码的运算装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1086618A true CN1086618A (zh) | 1994-05-11 |
CN1049778C CN1049778C (zh) | 2000-02-23 |
Family
ID=27318908
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN93118166A Expired - Fee Related CN1049778C (zh) | 1992-09-29 | 1993-09-29 | 用于实现误码纠错用卷积码的维特比译码的运算装置 |
CN99106651.0A Pending CN1237046A (zh) | 1992-09-29 | 1999-05-18 | 用于实现误码纠错用卷积码的维特比译码的运算装置 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN99106651.0A Pending CN1237046A (zh) | 1992-09-29 | 1999-05-18 | 用于实现误码纠错用卷积码的维特比译码的运算装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5715470A (zh) |
EP (2) | EP0590597B1 (zh) |
CN (2) | CN1049778C (zh) |
AU (1) | AU652896B2 (zh) |
DE (2) | DE69333460T2 (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100340971C (zh) * | 1997-06-06 | 2007-10-03 | 松下电器产业株式会社 | 运算装置 |
CN1862485B (zh) * | 1998-03-18 | 2010-05-12 | 高通股份有限公司 | 数字信号处理器 |
CN107211135A (zh) * | 2015-01-31 | 2017-09-26 | 高通股份有限公司 | 用于调色盘模式译码的译码逃脱像素 |
Families Citing this family (53)
Publication number | Priority date | Publication date | Assignee | Title |
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US5970097A (en) * | 1996-10-15 | 1999-10-19 | Matsushita Electric Industrial Co., Ltd. | Arithmetic apparatus for use in Viterbi decoding |
DE19647157A1 (de) * | 1996-11-14 | 1998-05-28 | Siemens Ag | Mehrstufige Multiplexeranordnung |
DE19647156A1 (de) * | 1996-11-14 | 1998-05-20 | Siemens Ag | Mehrstufige Multiplexeranordnung |
JP3338374B2 (ja) * | 1997-06-30 | 2002-10-28 | 松下電器産業株式会社 | 演算処理方法および装置 |
US6641897B2 (en) | 1998-02-13 | 2003-11-04 | The Milwaukee School Of Engineering | Three dimensional object |
US6309581B1 (en) | 1998-02-13 | 2001-10-30 | Milwaukee School Of Engineering | Method of making a three dimensional object |
US6573936B2 (en) * | 1998-08-17 | 2003-06-03 | Intel Corporation | Method and apparatus for providing a single-instruction multiple data digital camera system that integrates on-chip sensing and parallel processing |
US6952823B2 (en) * | 1998-09-01 | 2005-10-04 | Pkware, Inc. | Software patch generator using compression techniques |
US7031407B1 (en) * | 1998-09-28 | 2006-04-18 | Ceva D.S.P. Ltd. | Apparatus and method for decoding and trace back of convolution codes using the viterbi decoding algorithm |
FR2789247B1 (fr) * | 1999-01-28 | 2004-10-15 | St Microelectronics Sa | Circuit electronique modulaire a synchronisation amelioree |
US6623687B1 (en) | 1999-08-06 | 2003-09-23 | Milwaukee School Of Engineering | Process of making a three-dimensional object |
US6318156B1 (en) * | 1999-10-28 | 2001-11-20 | Micro Motion, Inc. | Multiphase flow measurement system |
US8230482B2 (en) | 2000-03-09 | 2012-07-24 | Pkware, Inc. | System and method for manipulating and managing computer archive files |
US20060143180A1 (en) * | 2000-03-09 | 2006-06-29 | Pkware, Inc. | System and method for manipulating and managing computer archive files |
US6879988B2 (en) * | 2000-03-09 | 2005-04-12 | Pkware | System and method for manipulating and managing computer archive files |
US20060143253A1 (en) * | 2000-03-09 | 2006-06-29 | Pkware, Inc. | System and method for manipulating and managing computer archive files |
US8959582B2 (en) | 2000-03-09 | 2015-02-17 | Pkware, Inc. | System and method for manipulating and managing computer archive files |
US20060155788A1 (en) * | 2000-03-09 | 2006-07-13 | Pkware, Inc. | System and method for manipulating and managing computer archive files |
US7844579B2 (en) * | 2000-03-09 | 2010-11-30 | Pkware, Inc. | System and method for manipulating and managing computer archive files |
US20060173847A1 (en) * | 2000-03-09 | 2006-08-03 | Pkware, Inc. | System and method for manipulating and managing computer archive files |
US20060143199A1 (en) * | 2000-03-09 | 2006-06-29 | Pkware, Inc. | System and method for manipulating and managing computer archive files |
US20060143237A1 (en) * | 2000-03-09 | 2006-06-29 | Pkware, Inc. | System and method for manipulating and managing computer archive files |
US20050015608A1 (en) | 2003-07-16 | 2005-01-20 | Pkware, Inc. | Method for strongly encrypting .ZIP files |
US20060143249A1 (en) * | 2000-03-09 | 2006-06-29 | Pkware, Inc. | System and method for manipulating and managing computer archive files |
DE10127348A1 (de) | 2001-06-06 | 2002-12-19 | Infineon Technologies Ag | Verfahren und Schaltungsanordnung zur Übertragung von Daten zwischen einem Prozessor und einem Hardware-Rechenwerk |
EP1297668B1 (de) | 2000-07-03 | 2005-11-16 | Infineon Technologies AG | Viterbi-entzerrer der verschiedene hardware-datenpfade für acs-operationen und für übertragungsmetriken verwendet |
JP3532884B2 (ja) * | 2001-05-18 | 2004-05-31 | 松下電器産業株式会社 | ビタビ復号器 |
US6552625B2 (en) | 2001-06-01 | 2003-04-22 | Microchip Technology Inc. | Processor with pulse width modulation generator with fault input prioritization |
US6985986B2 (en) * | 2001-06-01 | 2006-01-10 | Microchip Technology Incorporated | Variable cycle interrupt disabling |
US6976158B2 (en) * | 2001-06-01 | 2005-12-13 | Microchip Technology Incorporated | Repeat instruction with interrupt |
US6604169B2 (en) | 2001-06-01 | 2003-08-05 | Microchip Technology Incorporated | Modulo addressing based on absolute offset |
US20030023836A1 (en) * | 2001-06-01 | 2003-01-30 | Michael Catherwood | Shadow register array control instructions |
US7007172B2 (en) * | 2001-06-01 | 2006-02-28 | Microchip Technology Incorporated | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection |
US20030005269A1 (en) * | 2001-06-01 | 2003-01-02 | Conner Joshua M. | Multi-precision barrel shifting |
US6975679B2 (en) * | 2001-06-01 | 2005-12-13 | Microchip Technology Incorporated | Configuration fuses for setting PWM options |
US20030005268A1 (en) * | 2001-06-01 | 2003-01-02 | Catherwood Michael I. | Find first bit value instruction |
US6728856B2 (en) | 2001-06-01 | 2004-04-27 | Microchip Technology Incorporated | Modified Harvard architecture processor having program memory space mapped to data memory space |
US6937084B2 (en) * | 2001-06-01 | 2005-08-30 | Microchip Technology Incorporated | Processor with dual-deadtime pulse width modulation generator |
US20030028696A1 (en) * | 2001-06-01 | 2003-02-06 | Michael Catherwood | Low overhead interrupt |
US7020788B2 (en) * | 2001-06-01 | 2006-03-28 | Microchip Technology Incorporated | Reduced power option |
US6934728B2 (en) * | 2001-06-01 | 2005-08-23 | Microchip Technology Incorporated | Euclidean distance instructions |
US20020184566A1 (en) * | 2001-06-01 | 2002-12-05 | Michael Catherwood | Register pointer trap |
US6601160B2 (en) | 2001-06-01 | 2003-07-29 | Microchip Technology Incorporated | Dynamically reconfigurable data space |
US7467178B2 (en) * | 2001-06-01 | 2008-12-16 | Microchip Technology Incorporated | Dual mode arithmetic saturation processing |
US6952711B2 (en) * | 2001-06-01 | 2005-10-04 | Microchip Technology Incorporated | Maximally negative signed fractional number multiplication |
US6848074B2 (en) * | 2001-06-21 | 2005-01-25 | Arc International | Method and apparatus for implementing a single cycle operation in a data processing system |
AUPR679201A0 (en) * | 2001-08-03 | 2001-08-30 | Lucent Technologies Inc. | Path metric normalization of add-compare-select processing |
US6552567B1 (en) | 2001-09-28 | 2003-04-22 | Microchip Technology Incorporated | Functional pathway configuration at a system/IC interface |
US20040021483A1 (en) * | 2001-09-28 | 2004-02-05 | Brian Boles | Functional pathway configuration at a system/IC interface |
JP2005045727A (ja) * | 2003-07-25 | 2005-02-17 | Matsushita Electric Ind Co Ltd | ビタビ復号器 |
US7188302B2 (en) * | 2004-04-14 | 2007-03-06 | Realtek Semiconductor Corp. | Parallel decision-feedback decoder and method for joint equalizing and decoding of incoming data stream |
US7231586B2 (en) * | 2004-07-21 | 2007-06-12 | Freescale Semiconductor, Inc. | Multi-rate viterbi decoder |
CN101192833B (zh) * | 2006-11-28 | 2011-12-07 | 华为技术有限公司 | 一种低密度校验码ldpc并行编码的装置及方法 |
Family Cites Families (7)
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US4488252A (en) * | 1982-02-22 | 1984-12-11 | Raytheon Company | Floating point addition architecture |
US4639887A (en) * | 1984-02-24 | 1987-01-27 | The United States Of America As Represented By The United States Department Of Energy | Bifurcated method and apparatus for floating point addition with decreased latency time |
US4622877A (en) * | 1985-06-11 | 1986-11-18 | The Board Of Trustees Of The Leland Stanford Junior University | Independently controlled wavetable-modification instrument and method for generating musical sound |
JPS648438A (en) * | 1987-06-30 | 1989-01-12 | Mitsubishi Electric Corp | Data processor |
DE3886739D1 (de) * | 1988-06-02 | 1994-02-10 | Itt Ind Gmbh Deutsche | Einrichtung zur digitalen Signalverarbeitung. |
US4979175A (en) * | 1988-07-05 | 1990-12-18 | Motorola, Inc. | State metric memory arrangement for a viterbi decoder |
JP2917577B2 (ja) * | 1991-05-30 | 1999-07-12 | 松下電器産業株式会社 | 演算装置 |
-
1993
- 1993-09-27 AU AU47598/93A patent/AU652896B2/en not_active Ceased
- 1993-09-27 US US08/126,563 patent/US5715470A/en not_active Expired - Fee Related
- 1993-09-28 EP EP93115631A patent/EP0590597B1/en not_active Expired - Lifetime
- 1993-09-28 DE DE69333460T patent/DE69333460T2/de not_active Expired - Fee Related
- 1993-09-28 DE DE69331568T patent/DE69331568T2/de not_active Expired - Fee Related
- 1993-09-28 EP EP00113488A patent/EP1049001B1/en not_active Expired - Lifetime
- 1993-09-29 CN CN93118166A patent/CN1049778C/zh not_active Expired - Fee Related
-
1999
- 1999-05-18 CN CN99106651.0A patent/CN1237046A/zh active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100340971C (zh) * | 1997-06-06 | 2007-10-03 | 松下电器产业株式会社 | 运算装置 |
CN1862485B (zh) * | 1998-03-18 | 2010-05-12 | 高通股份有限公司 | 数字信号处理器 |
CN107211135A (zh) * | 2015-01-31 | 2017-09-26 | 高通股份有限公司 | 用于调色盘模式译码的译码逃脱像素 |
Also Published As
Publication number | Publication date |
---|---|
US5715470A (en) | 1998-02-03 |
EP0590597A3 (en) | 1995-10-18 |
EP0590597A2 (en) | 1994-04-06 |
AU652896B2 (en) | 1994-09-08 |
DE69333460T2 (de) | 2005-02-03 |
DE69331568T2 (de) | 2002-10-24 |
DE69333460D1 (de) | 2004-04-22 |
EP1049001B1 (en) | 2004-03-17 |
EP0590597B1 (en) | 2002-02-13 |
CN1049778C (zh) | 2000-02-23 |
EP1049001A1 (en) | 2000-11-02 |
AU4759893A (en) | 1994-04-14 |
DE69331568D1 (de) | 2002-03-21 |
CN1237046A (zh) | 1999-12-01 |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CI01 | Publication of corrected invention patent application |
Correction item: The patent conferred the name of the invention Correct: Computing device for Viterbi decoding of convolutional codes for error correction False: An operation device for decoding a convolutional code used to perform error correction Number: 8 Page: 154 Volume: 16 |
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ERR | Gazette correction |
Free format text: CORRECT: GRANTED DENOMINATION OF INVENTION BY PATENT RIGHT; FROM: ERROR CORRECTION IMPLEMENTATION OF CONVOLUTIONAL CODES WITH VITERBI DECODING OF THE COMPUTING DEVICES TO: ERROR CORRECTION IMPLEMENTATION OF CONVOLUTIONAL CODES WITH VITERBI COMPUTING DEVICE |
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C19 | Lapse of patent right due to non-payment of the annual fee | ||
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