CN108630709A - 双垂直窗三埋层soi高压器件结构 - Google Patents
双垂直窗三埋层soi高压器件结构 Download PDFInfo
- Publication number
- CN108630709A CN108630709A CN201710185314.7A CN201710185314A CN108630709A CN 108630709 A CN108630709 A CN 108630709A CN 201710185314 A CN201710185314 A CN 201710185314A CN 108630709 A CN108630709 A CN 108630709A
- Authority
- CN
- China
- Prior art keywords
- buried layer
- layer
- double
- voltage device
- device structures
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 24
- 239000001301 oxygen Substances 0.000 claims abstract description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 8
- 229920005591 polysilicon Polymers 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims description 4
- 230000005684 electric field Effects 0.000 abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
- 230000015556 catabolic process Effects 0.000 abstract description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 239000002253 acid Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Element Separation (AREA)
- Thin Film Transistor (AREA)
Abstract
本发明公开了一种多埋层大功率高压器件结构，器件结构如图1所示，该结构的埋层包含三层氧化层，两个窗不与埋层平行或者第一埋层与第二埋层不在同一平面上，第一层与第三层通过二氧化硅相连。第一层第二层埋氧层与第三层埋氧层之间填充多晶硅。该方法通过增强第三层埋氧层的电场，同时第一第二埋氧层的硅窗口可以调制漂移区电场来提高纵向击穿电压。
Description
技术领域
本发明涉及高压器件领域，尤其涉及多埋层SOI高压器件结构。
背景技术
SOI独特的结构带来隔离性能好、漏电流小、速度快、抗辐照和功耗低等优点，充分发挥了硅集成电路技术的潜力，特别是SOI高压集成电路在未来空天抗辐照领域具有特殊作用，因而得以广泛发展和应用。SOI横向高压器件作为高压集成电路的基石，由于介质层阻止了其耗尽区向衬底层扩展，使得习用的器件纵向耐压仅由顶层硅和介质层承担。而因隔离和散热的限制，顶层硅和介质层都不能太厚，同时由界面处无电荷高斯定理，使得器件击穿时的介质层电场仅为硅临界场的3倍即100V／μm左右，远未达到实际常用介质材料如SiO2的临界场600V／μm，所以SOI横向高压器件纵向耐压较低，限制了高压集成电路的应用和发展，目前投入应用的还没有突破600V的瓶颈。对此，国内外众多学者进行了深入研究，当前工作主要集中在使用新器件结构提高纵向电压。
业界通常改变各个区域的掺杂浓度或者改变埋氧层结构来增加埋氧层的电场强度和使电场线更均匀分布，来提高纵向击穿电压。
下面以单窗口双埋层SOI高压器件阐述现有的SOI高压器件结构。
图1是现有技术中SOI高压器件的结构示意图，该结构的埋层包含两层氧化层，第一埋氧层有单一窗口，两氧化层之间填充多晶硅。第一层埋氧阻挡了横向电场对第二埋氧层与多晶硅界面反型层电荷的抽取，该反型电荷将大大增强第二层埋氧层的电场；同时第一埋氧层的硅窗口可以调制漂移区电场，因而可获得较高的击穿电压。不过相对于实际应用要求，该SOI高压器件结构的击穿电压仍然需要进一步提高。
发明内容
本发明提供双窗三层SOI高压器件的结构，以提高SOI器件的击穿电压。
本发明提供了双窗三层SOI高压器件的结构，包括了三层埋氧层以及两个窗口，这两个窗口与水平的埋氧层成一定角度。
可选的，所述的角度为90°或其他角度（小于180°大于0°）。
可选的，所述前两层埋氧层是可互换的，即第一埋层下降到第二埋层之下。
可选的，所述前两层埋氧层之间的垂直距离可变。
可选的，第一层与第三层的连接层到器件左边界的距离是可变的。
可选的，填充的多晶硅可换成其他材料。
附图说明
图1是单窗SOI高压器件的结构示意图
图2是双窗SOI高压器件的结构示意图
具体实施方式
图2是本发明第一实施例中双窗三埋层SOI高压器件结构示意图，该结构使用了窗口与埋氧层垂直且的结构前两层埋氧阻挡了横向电场对第三埋氧层与多晶硅界面反型层电荷的抽取，该反型电荷将大大增强第三层埋氧层的电场；同时第一埋氧层的硅窗口可以调制漂移区电场，因而可获得较高的纵向击穿电压。
Claims (6)
1.一种双窗双埋层SOI高压器件结构，包括三层埋氧层以及埋氧层之间的多晶硅层，其特征在于所开的两个窗（第一埋层两端分别与第二埋层两端的连线）不与埋层平行或者第一埋层与第二埋层不在同一平面上，一二层与第三层埋层之间的填充多晶硅。
2.如权利要求1所述的双窗双埋层SOI高压器件结构，其特征在于，所述窗口与埋层所成的角度为大于0°小于180°的角。
3.如权利要求1所述的双窗双埋层SOI高压器件结构，所述前两层埋氧层是可互换的，即第一埋层下降到第二埋层之下。
4.如权利要求1所述的双窗双埋层SOI高压器件结构，所述前两层埋氧层之间的垂直距离可变。
5.如权利要求1所述的双窗双埋层SOI高压器件结构，所述的第一层与第三层的连接层到器件左边界的距离是可变的。
6.如权利要求1所述的双窗双埋层SOI高压器件结构，所述的多晶硅可以换成其他材料。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710185314.7A CN108630709A (zh) | 2017-03-26 | 2017-03-26 | 双垂直窗三埋层soi高压器件结构 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710185314.7A CN108630709A (zh) | 2017-03-26 | 2017-03-26 | 双垂直窗三埋层soi高压器件结构 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108630709A true CN108630709A (zh) | 2018-10-09 |
Family
ID=63706958
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710185314.7A Pending CN108630709A (zh) | 2017-03-26 | 2017-03-26 | 双垂直窗三埋层soi高压器件结构 |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108630709A (zh) |
-
2017
- 2017-03-26 CN CN201710185314.7A patent/CN108630709A/zh active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103928522B (zh) | 一种槽型积累层mosfet器件 | |
| CN104051510B (zh) | 半导体器件 | |
| CN101819996A (zh) | 半导体结构 | |
| WO2014094362A1 (zh) | 使用高介电常数槽结构的低比导通电阻的横向功率器件及其制备方法 | |
| CN104167448B (zh) | 薄膜晶体管及其制备方法、阵列基板和显示装置 | |
| CN103560145B (zh) | 一种具有界面栅的soi功率器件结构 | |
| CN104641470B (zh) | 鳍宽依赖性降低的soi finfet | |
| CN103094353B (zh) | 一种薄膜晶体管结构、液晶显示装置及一种制造方法 | |
| CN104282751B (zh) | 高集成度高迁移率源漏栅辅控型无结晶体管 | |
| CN108630709A (zh) | 双垂直窗三埋层soi高压器件结构 | |
| CN204905261U (zh) | 一种soi横向功率器件耐压结构 | |
| CN103762237A (zh) | 具有场板结构的横向功率器件 | |
| CN104851894A (zh) | 阵列基板及其制备方法、显示装置 | |
| CN104752441A (zh) | 一种阵列基板及其制备方法、显示面板和显示装置 | |
| CN105161527B (zh) | 利用一种表面耐压层结构的绝缘栅双极型器件 | |
| CN103956383B (zh) | 一种基于多顶栅结构的晶体管 | |
| CN204179089U (zh) | 等间距固定电荷区soi耐压结构及soi功率器件 | |
| Jo et al. | Fabrication and single-electron-transfer operation of a triple-dot single-electron transistor | |
| CN105097823A (zh) | 双垂直窗三埋层soi高压器件结构 | |
| CN102130172A (zh) | Soi器件结构 | |
| CN105023938A (zh) | 一种soi横向功率器件耐压结构及其制备方法 | |
| CN106688101A (zh) | 晶体管器件和方法 | |
| CN103187248B (zh) | 一种混合晶向绝缘体上锗晶片及器件的制备方法 | |
| CN104505403A (zh) | 一种具有介质层固定电荷的soi功率器件 | |
| CN204464279U (zh) | 一种阵列基板、显示面板和显示装置 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20181009 |
|
| WD01 | Invention patent application deemed withdrawn after publication |