CN108358629A - 低温共烧自支撑pzt基多层压电厚膜的制备 - Google Patents

低温共烧自支撑pzt基多层压电厚膜的制备 Download PDF

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CN108358629A
CN108358629A CN201810079839.7A CN201810079839A CN108358629A CN 108358629 A CN108358629 A CN 108358629A CN 201810079839 A CN201810079839 A CN 201810079839A CN 108358629 A CN108358629 A CN 108358629A
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thick film
temperature
low temperature
layer piezoelectric
supporting
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马卫兵
高骥风
王明阳
马民杰
郭靖栋
赵怀党
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Tianjin University
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Abstract

本发明公开了一种PZT基低温共烧自支撑多层压电厚膜制备方法，化学式为0.7Pb(Zr0.46Ti0.54)O3‑xPb(Zn1/3Nb2/3)O3‑(0.3‑x)Pb(Ni1/3Nb2/3)O3，的化学计量比，0≤x＜0.3。利用流延法制备得到相应的陶瓷生坯，通过丝网印刷涂上银内电极，制成多层并联结构。然后在850℃的温度下进行烧结得到样品。本发明实现了低温共烧，在保持了良好压电性能的前提下，使用银电极大大降低了成本；多层结构使得压电性能得到叠加，得到了高d33的多层压电厚膜；多层压电厚膜的自支撑，大大减少了总体体积，有利于小型化和微型化的发展方向，制备出了一种降低了成本和高使用价值的压电厚模材料。

Description

低温共烧自支撑PZT基多层压电厚膜的制备
技术领域
本发明属于一种以成分为特征的陶瓷组合物，特别涉及一种低温共烧自支撑PZT基多层压电厚膜的制备方法
背景技术
过去几十年里，压电陶瓷自诞生以来，由于其特殊的性质，一直得到广泛的关注和应用。其中PZT(锆钛酸铅)基压电陶瓷因为其良好的压电性能，一直以来得到了广泛的研究和发展。随着技术的发展，对于电子元件的要求朝着小型化、微型化、集成化方向发展，因此，压电厚膜也就随之诞生。压电厚膜坚固了块体材料高驱动力、宽工作频率以及薄膜材料低工作电压、集成性好的优势，广泛应用于微型电动机、能量采集器等器件中。
单层压电厚膜的性能较差，且需要进行多次热处理，包括排胶、烧结、被电极分开进行，由于电极与陶瓷之间结合不紧密，容易出现脱落和断裂，加上多次的热处理，使得PbO2流失，会恶化压电性能。而通过在单层膜之间涂覆电极，制成并联结构的多层压电厚膜，再通过共烧可以得到整体性良好的多层厚膜。低温共烧压电厚膜陶瓷，通过丝网印刷、流延法、溶胶凝胶法等方法成型，可以实现一次烧结成型。但是通常共烧的温度都较高，会导致PbO2的挥发，恶化压电性能，而且在较高温度下烧结需要使用银钯电极，成本很高。而在较低的烧结温度下进行烧结，可以降低PbO2的流失，同时由于降低了烧结温度，因此可以使用熔点更低、较为便宜的银电极，大大降低了成本。
多层共烧压电厚膜，与传统的单层厚膜相比，具有压电性能好、工作电压低、成本低等优点，但是任然存在可以改进的地方。在多层压电厚膜的成型过程中，受成型工艺和压电厚膜坯体本身的限制，在成型过程中都需要在基板上成型。首先，基板在烧结过程中会一定程度的限制陶瓷的收缩，会影响烧结后陶瓷的致密度，从而影响性能；其次，基板本身有一定的长宽尺寸，大于厚膜，不利于整体的小型化、微型化，基板本身也具有一定的厚度，在整体元件厚度一定的情况下，就会限制压电厚膜的层数，降低整体的压电性能。
因此，在低温共烧多层压电厚膜的基础上，再实现自支撑，可以减小厚膜整体体积，使得多层压电厚膜具有更强的实用性。
发明内容
本发明的目的，是为解决以往的压电厚膜都需要附着在基板上而无法实现自支撑、基板占有体积、有背于小型化微型化发展方向的缺点，提供一种在低温烧结的的条件下，通过多层并联结构，得到性能优异、成本低廉的多层压电厚膜材料。同时，通过有效地预处理和排胶烧结，实现多层厚膜的自支撑，使其符合小型化、微型化、集成化的发展方向。
本发明通过如下技术方案予以实现。
一种低温共烧自支撑多层压电厚膜的制备方法，具体步骤如下：
(1)配料
将原料ZnO、Nb2O5、TiO2、PbO2、Ni2O3、ZrO2按0.7Pb(Zr0.46Ti0.54)O3-xPb(Zn1/3Nb2/3)O3-(0.3-x)Pb(Ni1/3Nb2/3)O3的化学计量比，其中0≤x＜0.3。混合后按照球：料：去离子水的重量比为2：1：0.6放入球磨罐中球磨2h；
(2)合成
将步骤(1)中混合均匀的原料烘干、研磨，放入坩埚中密封，在850℃下合成两小时，冷却至室温，出炉。
(3)二次球磨
将步骤(2)中的合成原料放入球磨罐中球磨，球磨完后出料再在90℃烘干，然后在研钵中研磨过100目筛子；
(4)流延
将步骤(3)过筛后的粉料与有机物按照下述比例混合：
过筛后的粉料∶PVB∶PEG(2000)∶DBP∶丁酮∶乙醇的质量比为63∶4∶3∶3∶12∶18；
将上述混合原料置于球磨罐中湿磨6h，然后流延机上以进行流延，刮刀高度设置为200μm；得到流延生坯，即厚膜生坯；
(5)涂电极与厚膜的并联
将步骤(4)得到的流延生坯裁剪成长宽尺寸为1mm*1mm的小方块状，通过丝网印刷印刷在厚膜上涂覆银内电极，然后再堆叠上一层厚膜，如此反复，得到并联的多层厚膜；
将上述厚膜放在烘箱中将表面烘干后，再次丝网印刷，在烘干的多层厚膜上下分别印刷外电极；
(6)预处理
将步骤(5)得到的厚膜制品先在烘箱中烘干30分钟左右，然后使用压力机加压30MPa，保压5分钟，再在100℃下烘2h，直到制品表面发硬，不再有粘手感；
(7)排胶烧结
将步骤(6)的制品放入马弗炉中，以1.5℃/min的速率升温，分别在150℃保温30min，250℃保温30min，400℃保温40min进行排胶；
排胶完后继续升温直接进行烧结，以2℃/min速度升温至烧结温度，在800℃-900℃进行烧结，保温2h。
(8)极化
将(7)烧结得到的制品放置于硅油中，随硅油加热至120℃极化，然后保压降温，制得低温共烧自支撑PZT基多层压电厚膜。
本发明的有益效果是：
(1)850℃烧结，较低的烧结温度，使得贱金属银电极的使用得以实现，相比于金电极和银钯电极大大降低了成本。
(2)良好的压电性能：单层厚膜的压电系数可以达到202pc/N，九层样品的压电系数就可以达到1800pc/N以上，而总体的厚度不过0.7mm。
(3)自支撑的实现：自支撑的实现使得厚膜不用再附着于基板上，大大减小了总体的体积，有利于小型化微型化的发展方向。
附图说明
图1是本发明的结构示意图。
1——陶瓷相 2——银电极
具体实施方式
本发明的具体实施方法如下：
(1)配料
将原料ZnO、Nb2O5、TiO2、PbO2、Ni2O3、ZrO2按0.7Pb(Zr0.46Ti0.54)O3-0.1Pb(Zn1/ 3Nb2/3)O3-0.2Pb(Ni1/3Nb2/3)O3的化学计量比，混合后按照球：料：去离子水的重量比为2：1：0.6放入球磨罐中球磨2h；
(2)合成
将步骤(1)中混合均匀的料烘干后研细放入坩埚中密封，在850℃下合成两小时，冷却至室温，出炉；
(3)二次球磨
将步骤(2)中的合成料放入球磨罐中球磨8h，球磨完后出料在90℃烘干，然后在研钵中研磨过100目筛子；
(4)流延
将步骤(3)中过筛后的粉料，和有机物按照陶瓷粉、PVB、PEG(2000)、DBP、乙醇、丁酮以量比为63:4:3:3:12:18的比例混合，在球磨罐球磨6h。然后流延机上以进行流延，刮刀高度设置为200μm；
(5)涂电极和厚膜的并联
将步骤(4)得到的流延生坯裁剪成1mm*1mm尺寸小方块，通过丝网印刷印刷在厚膜上涂覆银内电极，然后再堆叠上一层厚膜，如此反复，得到多层比关联的厚膜。放在烘箱中将表面烘干后，再次丝网印刷，在样品上下涂覆上外电极；
(6)预处理
将步骤(5)得到的样品先在烘箱中烘一段时间，然后使用压机加压30MPa保压5分钟，再在较高温度100℃下烘2h，直到样品表面发硬，不再有粘手感；
(7)排胶烧结
将步骤(6)的样品放入马弗炉中，以1.5℃/min的速率升温，分别在150℃保温30min，250℃保温30min，400℃保温40min进行排胶，排胶完后继续升温直接进行烧结，以2℃/min速度升温至850℃，保温2h；
(8)极化
将(7)烧结得到的制品放置于硅油中，随硅油加热至120℃极化，极化电压为2.2KV/mm，极化时间30分钟，然后保压降温，制得低温共烧自支撑PZT基多层压电厚膜。
具体实施例如下：
制品的层数为5层、7层、9层的样品，分别记为实施例1-1、1-2、1-3、；本发明的自支撑多层PZT基压电厚膜的结构参见图1，可以看出，本发明的多层结构是由若干陶瓷相1和银电极2交错叠加组成。
上述具体实施例的微波介电性能测试结果列于表1。
表1
从表中可以看出，在850℃的低温下烧结，厚膜依然表现出良好的压电性能，单层的d33能达到200pc/N以上，而实施例1-3,具有9层叠加的制品压电系数就可以达到1800pc/N以上，与同厚度的块体材料相比大大领先，同时因为850℃的烧结温度，可以使用银电极，成本也降低了很多,。
从数据上可以看出，不同层数的压电厚膜其压电系数和其层数成正比，因此可得出结论，层数组增加并不会引起缺陷增多等问题从而降低单层性质，相反，增加层数可以有效增加总体的压电系数。而介电损耗较大，主要是由于温烧结，导致压电相之密度不够，缺陷较多，导致损耗增大，但是其数值任然在可以接受范围内；大的介电系数证明了该材料良好的介电性能。
本发明制备的低温共烧自支撑多层压电厚膜材料主要应用于微电子领域，在微型机械泵、微致动器、压力传感器、微机械谐振器等行业得到广泛应用。
上述对实施例的描述是便于该技术领域的普通技术人员能理解和应用本发明。熟悉本领域技术的人员显然可以容易地对这些实施例做出各种修改，并把在此说明的一般原理应用到其他实施例中而不必经过创造性的劳动。因此，本发明不限于这里的实施例，本领域技术人员根据本发明的揭示，对于本发明做出的改进和修改都应该在本发明的保护范围之内。

Claims (6)

1.一种低温共烧自支撑多层PZT基压电厚膜的制备方法，具体步骤如下：
(1)配料
将原料ZnO、Nb2O5、TiO2、PbO2、Ni2O3、ZrO2按0.7Pb(Zr0.46Ti0.54)O3-xPb(Zn1/3Nb2/3)O3-(0.3-x)Pb(Ni1/3Nb2/3)O3，的化学计量比，其中0≤x＜0.3。混合后按照球：料：去离子水的重量比为2：1：0.6放入球磨罐中球磨；
(2)合成
将步骤(1)中混合均匀的原料烘干、研磨，放入坩埚中密封，在850℃下合成两小时，冷却至室温，出炉。
(3)二次球磨
将步骤(2)中的合成原料放入球磨罐中球磨，球磨完后出料再在90℃烘干，然后在研钵中研磨过100目筛子；
(4)流延
将步骤(3)过筛后的粉料与有机物按照下述比例混合：
过筛后的粉料∶PVB∶PEG2000∶DBP∶丁酮∶乙醇的质量比为63∶4∶3∶3∶12∶18；
将上述混合原料置于球磨罐中湿磨6h，然后流延机上以进行流延；得到流延生坯，即厚膜生坯；
(5)涂电极与厚膜的并联
将步骤(4)得到的流延生坯裁剪成长宽尺寸为1mm*1mm的小方块状，通过丝网印刷印刷在厚膜上涂覆银内电极，然后再堆叠上一层厚膜，如此反复，得到并联的多层厚膜；
将上述厚膜放在烘箱中将表面烘干后，再次丝网印刷，在烘干的多层厚膜上下分别印刷外电极；
(6)预处理
将步骤(5)得到的厚膜制品先在烘箱中50℃烘干30分钟，然后使用压力机加压30MPa，保压5分钟，再在100℃下烘2h，直到制品表面发硬，不再有粘手感；
(7)排胶烧结
将步骤(6)的制品放入马弗炉中，以1.5℃/min的速率升温，分别在150℃保温30min，250℃保温30min，400℃保温40min进行排胶；
排胶完后继续升温直接进行烧结，以2℃/min速度升温至烧结温度，保温2h，在800-900℃范围内进行烧结。
(8)极化
将(7)烧结得到的制品放置于硅油中，加直流电压进行极化，制得低温共烧自支撑PZT基多层压电厚膜。
2.根据权利要求1所述的低温共烧自支撑多层压电厚膜的制备方法，其特征在于，所述步骤(1)的球磨时间为4h，球磨机转速为750转/分钟。
3.根据权利要求1所述的低温共烧自支撑多层压电厚膜的制备方法，其特征在于，所述步骤(4)中，PVB可以分两次加入，第一次加入50％，先溶解于有机相中再于陶瓷粉混合，球磨2小时后，直接加入剩下50％。
4.根据权利要求1所述的低温共烧自支撑多层压电厚膜的制备方法，其特征在于，所述步骤(4)中流延机刮刀高度为200μm。
5.根据权利要求1所述的低温共烧自支撑多层压电厚膜的制备方法，其特征在于，所述步骤(7)的烧结温度为850℃。
6.根据权利要求1所述的低温共烧自支撑多层压电厚膜的制备方法，其特征在于，所述步骤(8)中极化电压为2200V/mm，极化电压为极化温度120℃，极化时间30min。
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