CN108292659B - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN108292659B
CN108292659B CN201680009075.3A CN201680009075A CN108292659B CN 108292659 B CN108292659 B CN 108292659B CN 201680009075 A CN201680009075 A CN 201680009075A CN 108292659 B CN108292659 B CN 108292659B
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semiconductor layer
type semiconductor
overvoltage protection
semiconductor device
protection diode
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CN108292659A (zh
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小谷凉平
松原寿树
石塚信隆
三川雅人
押野浩
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Shindengen Electric Manufacturing Co Ltd
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Abstract

【课题】提供一种能够扩大活性区域的半导体装置。【解决手段】实施方式涉及的半导体装置1包括：由形成于耐压区域B的绝缘膜4上的N型半导体层5a与P型半导体层5b交替地相邻配置后所构成的过电压保护二极管5，其中，过电压保护二极管5被配置在绝缘膜4的上端面的角部，并且从角部向半导体基板2的中央部延伸。

Description

半导体装置
技术领域
本发明涉及半导体装置，具体为涉及具有MOS(Metal-Oxide-Semiconductor)构造，且设置有过电压保护二极管的半导体装置。
背景技术
以往，具有IGBT(Insulated Gate Bipolar Transistor)或MOSFET(MOS FieldEffect Transistor)等的，所谓MOS构造的半导体装置已被普遍认知。这样的MOS型半导体装置是利用由串联而成的稳压二极管(Zener diode)构成的过电压保护二极管来作为过电压保护的应对措施。具体来说，该过电压保护二极管是由交替地相邻配置的N型半导体层与P型半导体层所构成的。而IGBT则是在集电极端子与栅极端子之间，或栅极端子与发射极端子之间设置有过电压保护二极管。
以往的半导体装置100，在半导体基板120的上端面上，设置有：流通主电流的活性区域A；以及包围该活性区域A的耐压区域B。并且，过电压保护二极管150如图14所示，被设置为从半导体基板120的边部向中央部突出。在半导体基板120的周缘部，为了使耐压区域的表面电位稳定，还设置有由导电性材料构成的导体部(场板(Field plate)160、170、180、190)。这些导体部160、170、180、190为了与过电压保护二极管150的规定部位相连接，如图14所示存在有连接区域Bc。
先行技术文献
专利文献1：国际公开公报WO2014/142331号
由于上述以往的过电压保护二极管150被设置为从半导体基板120的边部向中央部突出，因此就存在有连接区域Bc较大，导致活性区域A相对较窄的课题。
本发明鉴于上述课题，目的是提供一种能够扩大活性区域的半导体装置。
发明内容
本发明涉及的半导体装置，在半导体基板的一方的主面与另一方的主面之间流通主电流，其特征在于：
在所述半导体基板的所述一方的主面上，设置有：流通所述主电流的活性区域、以及将所述活性区域包围并且的，并且包含所述半导体基板的周缘部的耐压区域，
并且包括：由形成于所述耐压区域的绝缘膜上的N型半导体层与P型半导体层交替地相邻配置后所构成的过电压保护二极管，
其中，所述过电压保护二极管被配置在形成于所述半导体基板上的所述绝缘膜的上端面的角部，并且从所述角部向所述半导体基板的中央部延伸。
另外，在所述半导体装置中，也可以是：
所述N型半导体层以及所述P型半导体层的横向宽度是固定的。
另外，在所述半导体装置中，也可以是：
所述N型半导体层以及所述P型半导体层从平面上看被形成为弧形或多段形。
另外，在所述半导体装置中，也可以是：
所述N型半导体层以及所述P型半导体层的横向宽度随着距离所述中央部越近则越宽。
另外，在所述半导体装置中，也可以是：
所述过电压保护二极管从平面上看被形成为梯形或弧形。
另外，在所述半导体装置中，也可以是：
所述N型半导体层以及所述P型半导体层中的至少一方的纵向宽度随着距离所述中央部越近则越窄。
另外，在所述半导体装置中，也可以是：
所述N型半导体层以及所述P型半导体层的厚度随着距离所述中央部越近则越薄。
另外，在所述半导体装置中，也可以是：
所述N型半导体层以及所述P型半导体层的载流子浓度随着距离所述中央部越近则越低。
另外，在所述半导体装置中，也可以是：
所述过电压保护二极管的侧边被形成为阶梯形，所述过电压保护二极管的延伸方向的侧面，与所述N型半导体层以及所述P型半导体层之间的界面几乎垂直相交。
另外，在所述半导体装置中，也可以是：
所述N型半导体层以及所述P型半导体层的横向宽度随着距离所述中央部越近则越窄。
另外，在所述半导体装置中，也可以是：
所述过电压保护二极管从平面上看被形成为弧形或多段形。
另外，在所述半导体装置中，也可以是：
所述N型半导体层以及所述P型半导体层中的至少一方的纵向宽度随着距离所述中央部越近则越宽。
另外，在所述半导体装置中，也可以是：
所述N型半导体层以及所述P型半导体层的厚度随着距离所述中央部越近则越厚。
另外，在所述半导体装置中，也可以是：
所述N型半导体层以及所述P型半导体层的载流子浓度随着距离所述中央部越近则越高。
另外，在所述半导体装置中，也可以是：
所述过电压保护二极管的侧边被形成为阶梯形，所述过电压保护二极管的延伸方向的侧面，与所述N型半导体层以及所述P型半导体层之间的界面几乎垂直相交。
另外，在所述半导体装置中，也可以是：
所述绝缘膜上设置有在与所述过电压保护二极管的延伸方向垂直相交的方向上延伸的沟槽部，所述N型半导体层以及所述P型半导体层中的一方被形成在所述沟槽部的底面上，所述N型半导体层以及所述P型半导体层中的另一方被形成在所述沟槽部的斜面上。
另外，在所述半导体装置中，也可以是：
进一步包括：形成在所述绝缘膜上的，与所述过电压保护二极管电气连接的一条或多条导体部。
另外，在所述半导体装置中，也可以是：
至少具备：被选择性地形成在所述耐压区域的所述一方的主面上的，并且包围所述活性区域的，一个以上的扩散层，
所述N型半导体层与所述P型半导体层的界面从平面上看沿所述扩散层的外侧的界面。
发明效果
在本发明中，过电压保护二极管被配置在形成于半导体基板上的绝缘膜的上端面的角部，并且从该角部向半导体基板的中央部延伸。通过这样，就能够扩大活性区域。
简单附图说明
图1是第一实施方式涉及的半导体装置1的平面图。
图2是沿图1的I-I线的截面图。
图3是沿图1的II-II线的截面图。
图4(A)是第一实施方式的变形例涉及的半导体装置1A的平面图。
图4(B)是第一实施方式的变形例涉及的半导体装置1A’的平面图。
图5是第一实施方式的变形例涉及的半导体装置1B的平面图。
图6是第二实施方式涉及的半导体装置1C的平面图。
图7是用于说明第二实施方式涉及的过电压保护二极管详细构成的平面图。
图8是侧边为阶梯形的过电压保护二极管的平面图。
图9是第二实施方式的变形例涉及的半导体装置1D的平面图。
图10是第三实施方式涉及的半导体装置1E的平面图。
图11是用于说明第三实施方式涉及的过电压保护二极管详细构成的平面图。
图12是第三实施方式的变形例涉及的半导体装置1F的平面图。
图13是具有在绝缘膜4上设置有沟槽部4a的构成的半导体装置的一部分截面图。
图14是以往的半导体装置100的平面图。
图15是用于比较第一实施方式涉及的半导体装置1与以往的半导体装置100之间的连接区域Bc的面积的平面图。
图16是第三实施方式的另一个变形例涉及的过电压保护二极管5的平面图。
图17是第三实施方式的又一个变形例涉及的过电压保护二极管5的平面图。
【发明的具体实施方式】
以下，将参照附图对本发明涉及的各实施方式进行说明。各图中具有同等功能的构成要素使用同一符号进行了标示。另外，在各图中的半导体装置平面图中，导体部6、7、8、9的形状，以及导体部6、7、8、9与过电压保护二极管5的连接关系均为简单的图示，因此有可能与实际的情况略有不同。
(第一实施方式)
以下，将参照图1～图3对本发明的第一实施方式涉及的半导体装置1进行说明。图1是半导体装置1的平面图，但图中并未图示有绝缘膜15、表面保护膜16、发射极21、栅电极22、塞电极(Stopper electrode)24。
第一实施方式涉及的半导体装置1为IGBT，其半导体基板2的上端面2a(一方的主面)与下端面2b(另一方的主面)之间流通有主电流。另外，虽然半导体基板2在本实施方式中为硅基板，但本发明并不仅限于此，也可以是其他类型的半导体基板(例如SiC基板、GaN基板等)。另外，半导体基板2的导电类型虽然在本实施方式中为N型，但不仅限于此。另外，在本实施方式中，半导体基板2虽然从平面上看呈略正方形，但并不仅限于此，半导体基板2也可以是从平面上呈长方形或是具有其他角部的形状。
如图1所示，半导体基板2的上端面2a上，设置有：流通主电流的活性区域A、以及包围该活性区域A的耐压区域B。耐压区域B包含半导体基板2的周缘部。这里的“周缘部”是指包含半导体基板2的侧面的半导体基板2的周缘部分。
如图1～图3所示，半导体装置1包括：P型扩散层3、绝缘膜4、过电压保护二极管5、导体部6、7、8、9、P型集电极区域12、N型扩散区域13、N型塞电极区域14、发射极21、栅电极22、集电极23、以及塞电极24。半导体基板2的上端面2a上还设置有栅极焊盘(Gate pad)(未图示)。
扩散层3被选择性地的形成在耐压区域B的上端面2a上，并且将活性区域A包围。该扩散层3也称为P型基极区域。图1中由界面P1和P2包围的区域就是P型基极区域。界面P1是扩散层3与周边半导体区域10之间的pn结的界面，界面P2是活性区域A与耐压区域B之间的界面。周边半导体区域10是位于扩散层3的外侧的N型半导体区域。
半导体装置1中也可以进一步包括：为了高耐压化而被设置为包围扩散层3的P型扩散层(保护环)。该保护环被选择性地形成在耐压区域B的上端面2a上。另外，保护环的数量不仅限于一个，可以是两个或更多。
扩散层3以及保护环的掺杂物浓度，例如为1×1014cm-3～1×1019cm-3。扩散层3以及保护环的深度，例如为2μm～10μm。周边半导体区域10的掺杂物浓度，例如为1×1013cm-3～1×1015cm-3。
绝缘膜4如图2所示，被形成在扩散层3、以及周边半导体区域10上。该绝缘膜4例如为场氧化膜。在本实施方式中，绝缘膜4为硅氧化膜(SiO2膜)，其厚度例如为200nm～2000nm。
过电压保护二极管5由多个稳压二极管串联而成。具体来说，该过电压保护二极管5是由N型半导体层5a和P型半导体层5b交替地相邻配置而构成的。N型半导体层5a和P型半导体层5b如图2所示，被形成在耐压区域B的绝缘膜4上。N型半导体层5a和P型半导体层5b分别为：被导入N型掺杂物(磷等)多晶硅层以及被导入P型掺杂物(硼等)多晶硅层。另外，虽然在本实施方式中，过电压保护二极管5是位于IGBT的集电极·栅极间的过电压保护二极管，但其也可以是位于IGBT的栅极·发射极间的过电压保护二极管。
过电压保护二极管5如图1所示，从平面上看被形成为略长方形。该长方形的宽度等被设定为能够确保过电压保护二极管5的击穿耐量。
在上述的第一实施方式涉及的过电压保护二极管5中，N型半导体层5a和P型半导体层5b的宽度是固定的。在本申请中，(N型或P型)半导体层的“宽度”是指：与半导体层上的过电压保护二极管5的延伸方向垂直相交的方向上的宽度。
如图1所示，过电压保护二极管5被配置在形成于半导体基板2上的绝缘膜4的上端面的角部，并且从该角部向半导体基板2的中央部延伸。通过这样，就能够削减连接区域Bc的面积，从而扩大活性区域。此处的连接区域Bc如图1所示，为了使导体部6、7、8、9与过电压保护二极管5连接，因而将相互的间隔设置得较宽。
导体部6、7、8、9被形成为在绝缘膜4上沿耐压区域B包围活性区域A，并且图1所示，导体部6、7、8、9分别与过电压保护二极管5的规定部位电气连接。即，导体部6、7、8、9基于各个重要部位的电压，从而与过电压保护二极管5的半导体层(N型半导体层5a和P型半导体层5b)电气连接。连接后的半导体层与导体部为相同的导电类型。另外，导体部也可以是连续跨过两个以上的半导体层后进行连接。
在本实施方式中，导体部6、7、8、9之间相互平行配置，并且例如由多晶硅或铝等导电性材料构成。如图3所述，导体部6、7经由绝缘膜4配置在扩散层3的上方，导体部8、9则经由绝缘膜4配置在周边半导体区域10的上方。导体部的数量不仅限于4个，可以为任意数量(可以是一至三个也可以是五个或更多)。
扩散区域13如图2所示，是形成在扩散层3中的N型半导体区域。该扩散区域13上形成有发射极21。另外，扩散区域13的掺杂物浓度，例如为1×1019cm-3～1×1021cm-3。
N型塞电极区域14被形成在半导体基板2侧端中的上端面2a上。N型塞电极区域14的掺杂物浓度高于周边半导体区域10。N型塞电极区域14上形成有塞电极24。该塞电极24与过电压保护二极管5的另一端(图2中为右端)电气连接。
栅电极22经由绝缘膜4设置在扩散层3的上方。该栅电极22在本实施方式中，被形成在过电压保护二极管5上。具体来说，如图2所示，栅电极22与过电压保护二极管5的活性区域A侧的一端(图2中为左端)电气连接。
P型集电极区域12被形成在半导体基板2的下端面2b上。该集电极区域12的掺杂物浓度例如为1×1017cm-3～1×1019cm-3。如图2所示，集电极区域12上形成有集电极23。另外，与集电极区域12相邻设置有缓冲区域11。该缓冲区域11的掺杂物浓度例如为1×1016cm-3～1×1018cm-3。
另外，如图2所示，半导体装置1还进一步包括：覆盖过电压保护二极管5的绝缘膜15、以及覆盖半导体装置1的整个上端面2a侧的表面保护膜16。绝缘膜15例如为BPSG(BoronPhosphorous Silicate Glass)膜，并且表面保护膜16例如为聚酰亚胺膜或氮化硅膜。
如上述般，在本实施方式涉及的半导体装置1中，过电压保护二极管5被配置在形成于半导体基板2上的绝缘膜4的上端面的角部。而且，过电压保护二极管5还被设置为从该角部向半导体基板2的中央部延伸。像这样，通过将过电压保护二极管5相对于半导体基板2的边斜着配置在角部，就能够扩大活性区域A。如图15所示，根据半导体装置1，连接区域Bc的面积与以往的半导体装置100相比得以被大幅地削减。
再有，在本实施方式涉及的半导体装置1中，过电压保护二极管5被形成为相对于半导体基板2的中心而对称。因此，在周边半导体区域10上设置包围扩散层3的保护环的情况下，就能够轻易地进行半导体装置1的耐压设计。
另外，IGBT的构成不仅限于上述的半导体装置1。例如，变形例涉及的半导体装置也可以具有替代P型集电极区域12的N型漏极区域，并且具有与该漏极区域形成肖特基势垒的集电极23。此情况下，集电极23则由铂、钼等构成的势垒金属所构成。
另外，半导体装置1的各个半导体区域的导电类型也可以与上述相反。即，也可以是：扩散层3为N型，周边半导体区域10为P型。另外，也可以根据重要部位的可靠性来适宜地省略导体部6、7、8、9。
(第一实施方式的变形例)
N型半导体层5a和P型半导体层5b的平面形状不仅限于长方形。图4(A)是第一实施方式的变形例涉及的半导体装置1A的平面图。图4(B)是第一实施方式的变形例涉及的半导体装置1A’的平面图。图5是第一实施方式的变形例涉及的半导体装置1B的平面图。在半导体装置1A中，如图4(A)所示，N型半导体层5a和P型半导体层5b从平面上看被形成为三段形。如图4(B)所示，N型半导体层5a和P型半导体层5b从平面上看可以被形成为两段形(在角部侧凸起的L字形)，也可以被形成为四段以上的形状。像这样，N型半导体层5a和P型半导体层5b可以被形成为多段形。
在半导体装置1B中，N型半导体层5a以及P型半导体层5b从平面上看被形成为在角部侧凸起的弧形。这样的半导体装置1A、1B同样能够获得与半导体装置1同样的作用于效果。进一步地，由于半导体装置1B中的各半导体层5a、5b为弧形，因此能够防止被施加于过电压保护二极管5的电压在局部集中。
(第二实施方式)
接下来，对本发明的第二实施方式涉及的半导体装置1C进行说明。第二实施方式与第一实施方式的不同点之一，在于N型半导体层5a以及P型半导体层5b的横向宽度随着距离中央部越近则越宽。下面，将以与第一实施方式的不同点为中心，对第二实施方式进行说明。
第二实施方式涉及的半导体装置1C如图6所示，过电压保护二极管5从平面上看被形成为梯形。具体来说，过电压保护二极管5从平面上看被形成为：活性区域A侧的边比半导体基板2的角部侧的边更长的梯形。即，N型半导体层5a以及P型半导体层5b的横向宽度随着距离中央部越近则越宽。通过这样，就没有了第一实施方式中存在的连接区域Bc，从而能够进一步扩大活性区域A。
这里，将参照图7，对第二实施方式中过电压保护二极管5的一种更理想的构成进行说明。如图7所示，N型半导体层5a被构成为其纵向宽度随着距离半导体基板2的中央部越近则越窄。在本申请中，(N型或P型)半导体层的“纵向宽度”是指：半导体层中过电压保护二极管5的延伸方向上的宽度。换言之，就是使横向宽度较窄的半导体层5a、5b的纵向宽度变宽。通过这样，由于纵截面积越小的半导体层，其纵向宽度就变得越宽，因此就能够充分确保过电压保护二极管5的击穿耐量。其结果就是，能够在过电压保护二极管5发生屈服时，防止导致永久性击穿。
另外，由于是通过增加半导体层的纵向宽度来增加过电压保护二极管5的电阻，因此如图7所示，虽然对于载流子浓度较高的N型半导体层5a来说，上述构成是比较理想的构成，但是本发明不仅限于此构成。即，P型半导体层5b可以被构成为其纵向宽度随着距离中央部越近则越窄，或也可以是N型半导体层5a以及P型半导体层5b双方均为纵向宽度随着距离中央部越近则越窄。
为了确保过电压保护二极管5的击穿耐量，可以使N型半导体层5a以及P型半导体层5b的厚度(本实施方式中为多晶硅层的厚度)随着距离半导体基板2的中央部越近而变得越薄。换言之，使横向宽度较窄的半导体层5a、5b的厚度变厚。通过这样，由于横向宽度较窄的半导体层5a、5b的纵截面积得以被确保，因此就能够充分确保过电压保护二极管5的击穿耐量。其结果就是，能够在过电压保护二极管5发生屈服时，防止导致永久性击穿。
为了确保过电压保护二极管5的击穿耐量，可以使N型半导体层5a以及P型半导体层5b的载流子浓度(电子浓度、空穴浓度)随着距离半导体基板2的中央部越近而变得越低。换言之，使横向宽度较窄的半导体层5a、5b的载流子浓度变高。通过这样，由于横向宽度较窄(即，纵截面积较小)的半导体层5a、5b的电阻得以被抑制得很低，因此就能够充分确保过电压保护二极管5的击穿耐量。其结果就是，能够在过电压保护二极管5发生屈服时，防止导致永久性击穿。
另外，也可以对上述的半导体层的纵向宽度、厚度以及载流子浓度的控制进行任意的组合，从而来确保过电压保护二极管5的击穿耐量。
再有，如图7所示，在过电压保护二极管5为具有侧边5s的梯形的情况下，当半导体基板1C被施加反向偏置的状态下，由于耗尽层会顺着斜面(Bevel)形状的侧边5s而扩展从而有可能导致发生击穿。此处的“施加方向偏置的状态”是指：集电极23与高电位(例如直流电源的正极)相连接，发射极21与与低电位(例如接地)相连接，栅电极22被施加了不会使IBGT导通(ON)程度的低电压的状态。
因此，如图8所示，可以将过电压保护二极管5的侧边5s形成为阶梯形，并且使过电压保护二极管5的延伸方向上的侧面S1，与N型半导体层5a以及P型半导体层5b之间的界面S2呈几乎垂直相交。通过这样，在施加反向偏置的状态下，耗尽层就会从截面S2上下均等地扩展，从而防止耗尽层的走形扩展。其结果就是，击穿的发生得以被抑制，从而能够抑制过电压保护二极管5的耐压(即，齐纳电压)的变动。
另外，过电压保护二极管5的平面形状不仅限于梯形。例如，也可以如图9所示的半导体装置1D般，从平面上看过电压保护二极管5被形成为弧形。此情况下，就能够防止被施加于过电压保护二极管5的电压在局部集中。过电压保护二极管5还可以被形成为在多处被折弯的多段形。
(第三实施方式)
接下来，对本发明的第三实施方式涉及的半导体装置1E进行说明。第三实施方式与第一实施方式的不同点之一在于：与第二实施方式相反，N型半导体层5a以及P型半导体层5b的横向宽度随着距离中央部越近则越窄。下面，将以与第一实施方式的不同点为中心，对第三实施方式进行说明。
第三实施方式涉及的半导体装置1E如图10所示，过电压保护二极管5从平面上看被形成为弧形。具体来说，过电压保护二极管5从平面上看被形成为：N型半导体层5a以及P型半导体层5b的横向宽度随着距离中央部越近则越窄。通过这样，就没有了第一实施方式中存在的连接区域Bc，从而能够进一步扩大活性区域A。再有，由于各半导体层5a、5b为弧形，因此就能够防止被施加于过电压保护二极管5的电压在局部集中。
这里，将参照图11，对第三实施方式中过电压保护二极管5的一种更理想的构成进行说明。如图11所示，N型半导体层5a被构成为其纵向宽度随着距离半导体基板2的中央部越近则越宽。换言之，就是使横向宽度(弧长)较窄的半导体层5a、5b的纵向宽度变宽。通过这样，由于纵截面积越小的半导体层，其纵向宽度就变得越宽，因此就能够充分确保过电压保护二极管5的击穿耐量。其结果就是，能够在过电压保护二极管5发生屈服时，防止导致永久性击穿。
另外，由于是通过增加半导体层的纵向宽度来增加过电压保护二极管5的电阻，因此如图11所示，虽然对于载流子浓度较高的N型半导体层5a来说，上述构成是比较理想的构成，但是本发明不仅限于此构成。即，P型半导体层5b可以被构成为其纵向宽度随着距离中央部越近则越宽，或也可以是N型半导体层5a以及P型半导体层5b双方均为纵向宽度随着距离中央部越近则越宽。
为了确保过电压保护二极管5的击穿耐量，可以使N型半导体层5a以及P型半导体层5b的厚度(本实施方式中为多晶硅层的厚度)随着距离半导体基板2的中央部越近而变得越厚。换言之，使横向宽度较窄的半导体层5a、5b的厚度变厚。通过这样，由于横向宽度较窄的半导体层5a、5b的纵截面积得以被确保，因此就能够充分确保过电压保护二极管5的击穿耐量。其结果就是，能够在过电压保护二极管5发生屈服时，防止导致永久性击穿。
为了确保过电压保护二极管5的击穿耐量，可以使N型半导体层5a以及P型半导体层5b的载流子浓度(电子浓度、空穴浓度)随着距离半导体基板2的中央部越近而变得越高。换言之，使横向宽度较窄的半导体层5a、5b的载流子浓度变高。通过这样，由于横向宽度较窄(即，纵截面积较小)的半导体层5a、5b的电阻得以被抑制得很低，因此就能够充分确保过电压保护二极管5的击穿耐量。其结果就是，能够在过电压保护二极管5发生屈服时，防止导致永久性击穿。
另外，也可以对上述的半导体层的纵向宽度、厚度以及载流子浓度的控制进行任意的组合，从而来确保过电压保护二极管5的击穿耐量。
第三实施方式涉及的过电压保护二极管5不仅限于弧形。例如，也可以如图12所示的半导体装置1F般，从平面上看过电压保护二极管5被形成为在多处被折弯的多段形。虽然图12中的过电压保护二极管5为在两处被折弯的三段形，但不仅限于此，其也可以是在三处以上被折弯的四段以上的多段形。
另外，过电压保护二极管5也可以从平面上看被形成为呈梯形。具体来说，过电压保护二极管5从平面上看被形成为：活性区域A侧的边比半导体基板2的角部侧的边更短的梯形。
另外，如图16所示，第三实施方式涉及的过电压保护二极管5也可以被形成为扇形。
另外，如图17所示，与第二实施方式中参照图8进行说明一样，可以将过电压保护二极管5的侧边形成为阶梯形。通过这样，在施加反向偏置的状态下就能个防止耗尽层的走形扩展。其结果就是，击穿的发生得以被抑制，从而能够抑制过电压保护二极管5的耐压的变动。
以上，对本发明涉及的三个实施方式进行了说明。如图7以及图11中的说明般，将半导体层的纵向宽度变宽，此情况下，也可以如图13所示，在绝缘膜4上形成沟槽部4a，并且利用该沟槽部4a的斜面。通过这样，就能够减少过电压保护二极管5所占的平面积。
具体来说，如图13所示，在绝缘膜4上，设置有与过电压保护二极管5的延伸方向垂直相交的方向(横方向)上延伸的沟槽部4a。并且，N型半导体层5a被形成在沟槽部4a的底面4a1上，而P型半导体层5b则被形成在沟槽部4a的斜面4a2上。另外。N型半导体层5a还被设置在沟槽部4a间的绝缘膜4上。由于P型半导体层5b的载流子浓度比N型半导体层5a更低，而且相比N型半导体层5a更需要确保纵向宽度，因此其被配置在沟槽部4a的斜面4a2上则较为理想。另外也可以将N型半导体层5a与P型半导体层5b相互替换。即，也可以将N型半导体层5a形成在沟槽部4a的斜面4a2上，将P型半导体层5b形成在沟槽部4a的底面4a1以及沟槽部4a间的绝缘膜4上。另外，在沟槽部4a的斜面上设置N型或P型半导体层的构成，能够被适用于上述任意一种过电压保护二极管5。
再有，虽然如上述般本发明涉及的过电压保护二极管能够采用各种平面形状，但无论是采用哪种平面形状，如上述的平面图(图1、4、5、6、9、10以及12)所示，理想的状态都是N型半导体层5a与P型半导体层5b的界面从平面上看沿着扩散层3的外侧的界面(即界面P1)。通过这样，就能够缓和被施加于过电压保护二极管的电压在局部集中。例如图5所示般，N型半导体层5a与P型半导体层5b的界面(圆弧形的线)与界面P1以及/或界面P2为相同形状则较为理想。另外，N型半导体层5a与P型半导体层5b的界面也可以是沿塞电极24的耐压部的界面。另外，在至少设置有一个以上的包围扩散层3的P型扩散层(保护环)的情况下，N型半导体层5a与P型半导体层5b的界面沿该扩散层的外侧的界面则较为理想。
在上述的实施方式的说明中，虽然是以半导体装置为IGBT为例进行说明，但本发明不仅限于此，本发明同样可以适用于纵型MOSFET等的，具有MOS构造的其他半导体装置。
基于上述记载，虽然本领域业者或许可以联想到本发明的追加效果或各种变形，但本发明的形态并不仅限于上述的各个实施方式。也可是将各种不同的实施方式间的构成要素进行适宜的组合。并且能够在专利请求的范围所规定的内容内，以及不脱离由其对等物指引出的本发明概念性的思想和主旨的范围内进行各种追添加、变更以及部分删除。
符号说明
1、1A、1B、1C、1D、1E、1F 半导体装置
2 半导体基板
2a 上端面
2b 下端面
3 扩散层
4 绝缘膜
4a 沟槽部
4a1 (够槽部的)底面
4a2 (够槽部的)斜面
5 过电压保护二极管
5a N型半导体层
5b P型半导体层
5s 侧边
6、7、8、9 导体部
10 周边半导体区域
11 缓冲区域
12 集电极区域
13 扩散区域
14 塞电极区域
15 绝缘膜
16 表面保护膜
21 发射极
22 栅电极
23 集电极
24 塞电极
100 半导体装置
120 半导体基板
150 过电压保护二极管
160、170、180、190 导体部
A 活性区域
B 耐压区域
Bc 连接区域
P1、P2 (扩散层3的)界面
S1 (过电压保护二极管5的)侧面
S2 (N型半导体层5a与P型半导体层5b的)界面

Claims (17)

1.一种半导体装置，在半导体基板的一方的主面与另一方的主面之间流通主电流，其特征在于：
在所述半导体基板的所述一方的主面上，设置有：流通所述主电流的活性区域、以及将所述活性区域包围并且的，并且包含所述半导体基板的周缘部的耐压区域，
并且包括：由形成于所述耐压区域的绝缘膜上的N型半导体层与P型半导体层交替地相邻配置后所构成的过电压保护二极管；以及
在所述绝缘膜上被形成为沿所述耐压区域将所述活性区域包围，且与所述过电压保护二极管电连接的第一导体部以及第二导体部，
其中，所述过电压保护二极管被配置在形成于所述半导体基板上的所述绝缘膜的上端面的角部，并且从所述角部向所述半导体基板的中央部延伸，
所述第一导体部与构成所述过电压保护二极管的N型半导体层以及P型半导体层中的一个半导体层电连接，所述第二导体部与构成所述过电压保护二极管的N型半导体层以及P型半导体层中的另一个半导体层电连接。
2.根据权利要求1所述的半导体装置，其特征在于：
其中，所述N型半导体层以及所述P型半导体层的横向宽度是固定的。
3.根据权利要求2所述的半导体装置，其特征在于：
其中，所述N型半导体层以及所述P型半导体层从平面上看被形成为弧形或多段形。
4.根据权利要求1所述的半导体装置，其特征在于：
其中，所述N型半导体层以及所述P型半导体层的横向宽度随着距离所述中央部越近则越宽。
5.根据权利要求4所述的半导体装置，其特征在于：
其中，所述过电压保护二极管从平面上看被形成为梯形或弧形。
6.根据权利要求4所述的半导体装置，其特征在于：
其中，所述N型半导体层以及所述P型半导体层中的至少一方的纵向宽度随着距离所述中央部越近则越窄。
7.根据权利要求4所述的半导体装置，其特征在于：
其中，所述N型半导体层以及所述P型半导体层的厚度随着距离所述中央部越近则越薄。
8.根据权利要求4所述的半导体装置，其特征在于：
其中，所述N型半导体层以及所述P型半导体层的载流子浓度随着距离所述中央部越近则越低。
9.根据权利要求4所述的半导体装置，其特征在于：
其中，所述过电压保护二极管的侧边被形成为阶梯形，所述过电压保护二极管的延伸方向的侧面，与所述N型半导体层以及所述P型半导体层之间的界面几乎垂直相交。
10.根据权利要求1所述的半导体装置，其特征在于：
其中，所述N型半导体层以及所述P型半导体层的横向宽度随着距离所述中央部越近则越窄。
11.根据权利要求10所述的半导体装置，其特征在于：
其中，所述过电压保护二极管从平面上看被形成为弧形或多段形。
12.根据权利要求10所述的半导体装置，其特征在于：
其中，所述N型半导体层以及所述P型半导体层中的至少一方的纵向宽度随着距离所述中央部越近则越宽。
13.根据权利要求10所述的半导体装置，其特征在于：
其中，所述N型半导体层以及所述P型半导体层的厚度随着距离所述中央部越近则越厚。
14.根据权利要求10所述的半导体装置，其特征在于：
其中，所述N型半导体层以及所述P型半导体层的载流子浓度随着距离所述中央部越近则越高。
15.根据权利要求10所述的半导体装置，其特征在于：
其中，所述过电压保护二极管的侧边被形成为阶梯形，所述过电压保护二极管的延伸方向的侧面，与所述N型半导体层以及所述P型半导体层之间的界面几乎垂直相交。
16.根据权利要求1所述的半导体装置，其特征在于：
其中，所述绝缘膜上设置有在与所述过电压保护二极管的延伸方向垂直相交的方向上延伸的沟槽部，所述N型半导体层以及所述P型半导体层中的一方被形成在所述沟槽部的底面上，所述N型半导体层以及所述P型半导体层中的另一方被形成在所述沟槽部的斜面上。
17.根据权利要求1所述的半导体装置，其特征在于：
至少具备：被选择性地形成在所述耐压区域的所述一方的主面上的，并且包围所述活性区域的，一个以上的扩散层，
所述N型半导体层与所述P型半导体层的界面从平面上看沿所述扩散层的外侧的界面。
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