CN108231594A - 一种FinFET器件的制作方法 - Google Patents

一种FinFET器件的制作方法 Download PDF

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CN108231594A
CN108231594A CN201711391067.2A CN201711391067A CN108231594A CN 108231594 A CN108231594 A CN 108231594A CN 201711391067 A CN201711391067 A CN 201711391067A CN 108231594 A CN108231594 A CN 108231594A
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silicon
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fin structures
raceway groove
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CN108231594B (zh
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宋雷
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Shanghai IC R&D Center Co Ltd
Chengdu Image Design Technology Co Ltd
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Shanghai Integrated Circuit Research and Development Center Co Ltd
Chengdu Image Design Technology Co Ltd
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Abstract

本发明公开了一种FinFET器件的制作方法，包括如下步骤：S01：提供SOI衬底；S02：采用阻挡层覆盖上述顶层硅的中间部分，并在顶层硅上方进行硅离子注入，使得未被阻挡层覆盖的顶层硅下方的绝缘埋层转化为富硅二氧化硅，S03：去除阻挡层，在顶层硅中定义出Fin结构，Fin结构中的沟道位于上述顶层硅的非注入区，源漏位于上述顶层硅的注入区；去除Fin结构以外的顶层硅；S04：去除Fin结构中沟道下方的绝缘埋层，形成悬空的沟道；S05：在上述悬空的沟道外围依次形成全包围的电介质薄膜和栅极；S06：在上述结构中形成侧墙和源漏掺杂。本发明提供的一种FinFET器件的制作方法，可以使得FinFET器件具有稳定的全包围栅结构，提高器件的栅控能力和驱动电流。

Description

一种FinFET器件的制作方法
技术领域
本发明涉及半导体工艺制造工艺，具体涉及一种FinFET器件的制作方法。
背景技术
随着MOS器件尺寸不断缩减，栅极对沟道的控制能力逐渐减弱，短沟道效应不断增强。这将引起器件关态漏电流增加，亚阈值特性退化等问题。为保证28nm工艺节点下摩尔定律的延续，业界提出了体硅FinFET和全耗尽(full depleted,FD)SOI两种解决方案。其中FinFET器件采用三维结构，通过增加侧面的栅控沟道来改善短沟道效应,提高驱动电流。FDSOI器件仍采用平面结构，通过极薄的顶层硅和绝缘埋层厚度(ultra thin body and BOX，UTBB)来提高栅控能力，改善短沟道效应。
基于SOI材料的quadruple-gate MOS器件(也称为surrounding-gate SOI MOS器件)结合了FinFET和SOI的优点，采用全包围的栅极控制器件沟道。该器件结构可达到理论上最好的栅控能力，大大改善短沟道效应，提高器件的驱动电流。
该结构的制造难点主要为：在刻蚀沟道正下方的绝缘埋层以形成悬空沟道的过程中，沿沟道方向，即靠近Fin源漏下方的绝缘埋层也会被刻蚀。为了形成悬空的沟道结构，通常过刻蚀的厚度为Fin结构中沟道宽度的一半，才能保证沟道正下方的绝缘埋层从两侧被完全刻蚀掉，这也意味着沟道两侧源漏正下方的绝缘埋层也要被过刻蚀掉相应的部分，源漏下方的过刻蚀会改变原来沟道的长度，这种改变对于长沟道器件性能影响较小，对于短沟道器件性能影响较大。因此常规的工艺制造方法不适用于沟道较短的器件，对于器件尺寸的微缩是不利的。
发明内容
本发明所要解决的技术问题为提供一种FinFET器件的制作方法，可以使得FinFET器件具有稳定的全包围栅结构，提高器件的栅控能力和驱动电流。
为了实现上述目的，本发明采用如下技术方案：一种FinFET器件的制作方法，包括如下步骤：
S01：提供SOI衬底，所述SOI衬底自上而下依次为顶层硅、绝缘埋层、衬底，其中绝缘埋层为二氧化硅；
S02：采用阻挡层覆盖上述顶层硅的中间部分，并在顶层硅上方进行硅离子注入，使得未被阻挡层覆盖的顶层硅下方的绝缘埋层转化为富硅二氧化硅，其中，顶层硅中未被阻挡层覆盖的部分称为注入区，被阻挡层覆盖的部分称为非注入区；
S03：去除阻挡层，在顶层硅中定义出Fin结构，所述Fin结构包括沟道和源漏，源漏位于沟道的两侧；且Fin结构中的沟道位于上述顶层硅的非注入区，源漏位于上述顶层硅的注入区；去除Fin结构以外的顶层硅；
S04：去除Fin结构中沟道下方的绝缘埋层，形成悬空的沟道；
S05：在上述悬空的沟道外围依次形成全包围的电介质薄膜和栅极；
S06：在上述结构中形成侧墙和源漏掺杂。
进一步地，所述SOI衬底自上而下依次为p型掺杂的顶层硅、绝缘埋层、p型掺杂的衬底。
进一步地，所述Fin结构中的沟道具有圆形截面或者方形截面。
进一步地，所述步骤S02中在顶层硅上方进行硅离子注入，确保被注入的硅浓度分布的峰值在绝缘埋层中。
进一步地，所述步骤S03中采用干法刻蚀去除Fin结构以外的顶层硅。
进一步地，所述步骤S04中采用湿法刻蚀去除Fin结构中沟道下方的绝缘埋层。
进一步地，所述湿法刻蚀采用HF作为湿法刻蚀剂。
进一步地，所述电介质薄膜由二氧化硅、氮化硅、二氧化铪等高介电常数材料中的一种或几种形成。
进一步地，所述栅极由多晶硅或金属材料形成。
进一步地，所述侧墙由二氧化硅、氮化硅等绝缘材料形成。
本发明的有益效果为：本发明提供一种FinFET器件的制作方法，通过光刻和硅离子注入，使得部分SOI绝缘埋层二氧化硅转化为富硅二氧化硅，减小其刻蚀速率。在后续刻蚀去除沟道下方绝缘埋层二氧化硅时，保证了沟道方向靠近Fin源漏的绝缘埋层刻蚀较弱，适用于短沟道FinFET器件的制造。同时本发明使用硅离子注入，不会改变顶层硅的初始掺杂浓度，有利于保证器件电学参数的稳定性和均匀性。且硅离子注入不引入额外的污染杂质，有利于工艺和器件的可靠性。
附图说明
图1-5为本发明实施例中提出的实施实例的工艺流程图。
图6为本发明实施例中制备的FinFET器件的截面图。
图中：100衬底，101绝缘埋层，102顶层硅，102’Fin结构，103富硅二氧化硅，104电介质薄膜，105栅极，200阻挡层。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面结合附图对本发明的具体实施方式做进一步的详细说明。
本发明提供的一种FinFET器件的制作方法，包括如下步骤：
S01：提供SOI衬底，所述SOI衬底自上而下依次为顶层硅、绝缘埋层、衬底。
其中，如图1所示，为常规p型掺杂的SOI晶圆。其中，本实施例中SOI衬底自上而下依次为p型掺杂的顶层硅、绝缘埋层二氧化硅、p型掺杂的衬底，100为p型掺杂的衬底，通常可以为低阻、高阻或trap rich。101为绝缘埋层，为二氧化硅层，其厚度典型值为15～250nm。102为p型掺杂顶层硅，其厚度典型值为10～200nm。值得说明的是，SOI衬底的掺杂类型不影响本发明的制作方法，此处也可以采用n型掺杂的SOI晶圆，后续步骤采用类似的方法进行操作。
S02：如图2所示，采用阻挡层覆盖上述顶层硅的中间部分，并在顶层硅上方进行硅离子注入，使得未被阻挡层覆盖的顶层硅下方的绝缘埋层转化为富硅二氧化硅，其中，顶层硅中未被阻挡层覆盖的部分称为注入区，被阻挡层覆盖的部分称为非注入区。
其中，通过光刻定义注入区，并进行硅离子注入，如图2所示。其中200为阻挡层，可以采用光阻；其下方的绝缘埋层区域未注入硅离子，故仍为原来的绝缘埋层101。其他未被光阻覆盖的绝缘埋层由于注入了硅离子，形成富硅二氧化硅103。也就是说，在有阻挡层覆盖的部分，其下方的绝缘埋层还是之前的成分不变；没有阻挡层覆盖的部分，经过硅离子注入之后，其下方的绝缘埋层被注入硅离子，变成了富硅二氧化硅103。在后续采用HF溶液进行刻蚀时，富硅二氧化硅103的刻蚀速率低于原来的绝缘埋层101区域的刻蚀速率。因此可有效减小沿沟道方向的刻蚀。
图2中，硅离子注入能量和剂量由顶层硅102及绝缘埋层101厚度决定。所选择的注入能量应保证硅浓度分布的峰值在绝缘埋层101中，其典型值为10～200keV。对于较薄的顶层硅102，注入能量一般较小。对于较厚的顶层硅102，注入能量相对较大。所选择的注入剂量应保证富硅二氧化硅的形成，其典型值为1×1010/cm2～1×1018/cm2。其中，对于较薄的绝缘埋层101，注入剂量一般较小，采用一次注入。对于较厚的绝缘埋层101，注入剂量较大，通常采用多次注入。
本发明使用硅离子注入，不会改变顶层硅的初始掺杂浓度，有利于保证器件电学参数的稳定性和均匀性。同时硅离子注入不引入额外的污染杂质，有利于工艺和器件的可靠性。
S03：如图3所示，去除阻挡层，在顶层硅中定义出Fin结构，Fin结构包括沟道和源漏，源漏位于沟道的两侧；且Fin结构中的沟道位于上述顶层硅的非注入区，源漏位于上述顶层硅的注入区；去除Fin结构以外的顶层硅。本发明中沟道形状可以是图3中截面为方形的的长方体沟道，也可以为截面为圆形的圆柱体或者其他的形状。
其中，去除阻挡层200后，采用光刻定义Fin结构，进行干法刻蚀以去除顶层硅102和绝缘埋层101，所得结构如图3所示。其中102’为Fin结构，非Fin结构区域中的顶层硅102被完全刻蚀，绝缘埋层101被部分刻蚀。Fin下方绝缘埋层未被刻蚀，包括沟道下方绝缘埋层101和源漏下方的富硅二氧化硅103。
干法刻蚀顶层硅102和绝缘埋层二氧化硅101时，绝缘埋层二氧化硅101可以被全部刻蚀，直至露出衬底硅100，或者保留一定厚度的绝缘埋层二氧化硅101，或者仅刻蚀顶层硅而不刻蚀绝缘埋层二氧化硅101。
S04：如图4所示，去除Fin结构中沟道下方的绝缘埋层二氧化硅，形成悬空的沟道。
其中，采用湿法刻蚀去除沟道下方绝缘埋层二氧化硅101，形成悬空的沟道结构，如图4所示。由于源漏下方富硅二氧化硅103的刻蚀速率较沟道下方绝缘埋层101的刻蚀速率低，因此当沟道下方绝缘埋层101被刻蚀完成后，源漏下方的富硅二氧化硅103基本未被刻蚀。由于源漏两端富硅二氧化硅103的支撑，沟道处于稳定的悬空状态。
图4中，湿法刻蚀去除沟道下方绝缘埋层二氧化硅101时，刻蚀的厚度至少为Fin结构宽度的一半。通常采用稀释的HF溶液作为刻蚀液。本发明中沟道下方的绝缘埋层是否被完全刻蚀掉对本发明不产生影响，为了使得后续的电介质薄膜和栅极能够包围在沟道的四周，本实施例中我们使得沟道下方绝缘埋层在垂直于沟道方向上被刻蚀的宽度大于等于Fin结构中沟道宽度的一半，其中，沟道宽度指的是在Fin结构的水平面上，长方体沟道在垂直于沟道方向上的宽度。
S05：如图5所示，在上述悬空的沟道外围依次形成全包围的电介质薄膜和栅极。
图5中，形成电介质薄膜104和栅极105，完成全包围栅结构。其中电介质薄膜由二氧化硅、氮化硅、二氧化铪等高介电常数材料中的一种或几种形成，其采用热生长的方式在悬空的沟道表面上均匀生成。栅极由多晶硅或金属材料形成。
S06：在上述结构中形成侧墙和源漏掺杂。最后采用常规工艺步骤形成侧墙、源漏掺杂。其中侧墙由二氧化硅、氮化硅等绝缘材料形成。源漏采用离子注入进行掺杂。对于NMOS器件，掺杂类型为n型，包括磷，砷等一种或多种掺杂的组合；对于PMOS器件，掺杂类型为p型，包括硼，二氟化硼等一种或多种掺杂的组合。离子注入后采用退火工艺激活源漏掺杂。
本发明制作出来的FinFET器件的截面图如附图6所示，具有全包围栅截面，沟道方向为水平方向。同样地，本发明上述制作方法也适用于圆形的全包围栅截面器件，沟道方向也为水平方向。
以上所述仅为本发明的优选实施例，所述实施例并非用于限制本发明的专利保护范围，因此凡是运用本发明的说明书及附图内容所作的等同结构变化，同理均应包含在本发明所附权利要求的保护范围内。

Claims (10)

1.一种FinFET器件的制作方法，其特征在于，包括如下步骤：
S01：提供SOI衬底，所述SOI衬底自上而下依次为顶层硅、绝缘埋层、衬底，其中绝缘埋层为二氧化硅；
S02：采用阻挡层覆盖上述顶层硅的中间部分，并在顶层硅上方进行硅离子注入，使得未被阻挡层覆盖的顶层硅下方的绝缘埋层转化为富硅二氧化硅，其中，顶层硅中未被阻挡层覆盖的部分称为注入区，被阻挡层覆盖的部分称为非注入区；
S03：去除阻挡层，在顶层硅中定义出Fin结构，所述Fin结构包括沟道和源漏，源漏位于沟道的两侧；且Fin结构中的沟道位于上述顶层硅的非注入区，源漏位于上述顶层硅的注入区；去除Fin结构以外的顶层硅；
S04：去除Fin结构中沟道下方的绝缘埋层，形成悬空的沟道；
S05：在上述悬空的沟道外围依次形成全包围的电介质薄膜和栅极；
S06：在上述结构中形成侧墙和源漏掺杂。
2.根据权利要求1所述的一种FinFET器件的制作方法，其特征在于，所述SOI衬底自上而下依次为p型掺杂的顶层硅、绝缘埋层、p型掺杂的衬底。
3.根据权利要求1所述的一种FinFET器件的制作方法，其特征在于，所述Fin结构中的沟道具有圆形截面或者方形截面。
4.根据权利要求1所述的一种FinFET器件的制作方法，其特征在于，所述步骤S02中在顶层硅上方进行硅离子注入，确保被注入的硅浓度分布的峰值在绝缘埋层中。
5.根据权利要求1所述的一种FinFET器件的制作方法，其特征在于，所述步骤S03中采用干法刻蚀去除Fin结构以外的顶层硅。
6.根据权利要求1所述的一种FinFET器件的制作方法，其特征在于，所述步骤S04中采用湿法刻蚀去除Fin结构中沟道下方的绝缘埋层。
7.根据权利要求6所述的一种FinFET器件的制作方法，其特征在于，所述湿法刻蚀采用HF作为湿法刻蚀剂。
8.根据权利要求1所述的一种FinFET器件的制作方法，其特征在于，所述电介质薄膜由二氧化硅、氮化硅、二氧化铪等高介电常数材料中的一种或几种形成。
9.根据权利要求1所述的一种FinFET器件的制作方法，其特征在于，所述栅极由多晶硅或金属材料形成。
10.根据权利要求1所述的一种FinFET器件的制作方法，其特征在于，所述侧墙由二氧化硅、氮化硅等绝缘材料形成。
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