CN104037159A - 一种半导体结构及其形成方法 - Google Patents

一种半导体结构及其形成方法 Download PDF

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CN104037159A
CN104037159A CN201410275700.1A CN201410275700A CN104037159A CN 104037159 A CN104037159 A CN 104037159A CN 201410275700 A CN201410275700 A CN 201410275700A CN 104037159 A CN104037159 A CN 104037159A
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fin
silicon
lines
layer
corrosion
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CN104037159B (zh
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黎明
杨远程
樊捷闻
宣浩然
张昊
黄如
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Peking University
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Abstract

一种半导体结构，包括：一半导体衬底，多层超细硅线条，所述的多层超细硅线条的界面形状受衬底晶向和线条轴向晶向双重控制。形成方法包括：通过刻蚀工艺形成鱼鳍状硅岛Fin及其两端的源漏区；制备硅的腐蚀掩蔽层；形成多层超细硅线条。本发明的优点：最终形成的多层超细硅线条的位置与截面形状均匀、可控；对硅的各向异性腐蚀是自停止的，工艺窗口大，可在同一硅片上实现不同直径的硅线条；ICPECVD具有较强的窄槽填充能力，淀积牺牲层和腐蚀掩蔽层材料时无空洞；结合氧化技术可以制备尺寸小于10nm的线条，满足小尺寸器件关键工艺的要求；采用自上而下的加工方法，完全和体硅平面晶体管工艺兼容，工艺成本代价小。

Description

一种半导体结构及其形成方法
技术领域
本发明属于超大规模集成电路制造技术领域，涉及一种多层超细硅线条的结构及其制备方法，尤其涉及一种结合鱼鳍状硅岛的侧壁掩膜技术与硅的各向异性腐蚀技术来制备位置与形状可控的多层超细硅线条的方法。
背景技术
随着摩尔定律推进到22nm工艺节点，传统平面器件因其短沟效应和可靠性问题愈加突出，导致器件性能严重退化，不能满足摩尔定律的要求。以鱼鳍型场效应晶体管(FinFET)为代表的三维多栅器件(Multi-gate MOSFET,MuGFET)，以其出众的抑制短沟效应能力，以及集成密度高，与传统CMOS工艺兼容等优点，在22nm节点成功实现量产。
在三维多栅器件中，多层围栅纳米线场效应管(Multi-Bridge-Channel Gate-all-aroundNanowire FET，MBC GAA NWFET)具有非常突出的栅控能力，超高集成密度和驱动电流等优势，成为22nm节点后的有力竞争者。
制造多层围栅纳米线场效应管的关键技术之一是制备位置、截面形状均匀可控的多层超细硅线条。
香港科技大学的Ricky M.Y.Ng小组结合电感耦合等离子(ICP)刻蚀中的Bosch工艺与牺牲氧化，形成上下排列的多层纳米线[M.Y.Ng Ricky,et al.,EDL,2009,30(5):520～522.]。但该方法形成纳米线的位置和截面形状因工艺涨落而不可控，进而造成器件性能涨落严重。
韩国三星电子公司Sung-Young Lee等人以SiGe为牺牲层在体硅衬底上成功制备了多层沟道场效应管[Sung-Young Lee,et al.,TED,2003,2(4):253-257.]。其核心技术为在体硅上外延得到Si-SiGe的超晶格结构，通过湿法腐蚀去掉SiGe牺牲层得到多层悬空沟道。但该超晶格结构中的各层薄膜的质量与厚度受到晶格失配与应力释放等因素限制，且工艺相对复杂。
因此，业界急需一种多层超细硅线条的结构和制备方法，除了具有高的集成密度外，同时又能克服公知技术的缺点。
发明内容
本发明提供一种半导体结构及其形成方法，以改善现有的公知技术。
术语说明：根据叶良修《半导体物理》第一章中定义：(100)、(110)、(111)、(112)为晶面的密勒指数；<100>、<110>、<111>、<112>为晶向指数。
本发明提供一种半导体结构，包括：一半导体衬底，多层超细硅线条，其特征是，所述的多层超细硅线条的界面形状受衬底晶向和线条轴向晶向双重控制：
对于(100)衬底上沿<110>的多层超细硅线条，顶层线条的截面为五边形，该五边形由一个(100)晶面、二个(110)晶面和二个(111)晶面围成；以下各层线条的截面为六边形，该六边形由两个(110)晶面和四个(111)晶面围成；
对于(110)衬底上沿<110>的多层超细硅线条，顶层线条的截面为五边形，该五边形由一个(110)晶面、二个(100)晶面和二个(111)晶面围成；以下各层线条的截面为六边形，该六边形由两个(100)晶面和四个(111)晶面围成；
对于(111)衬底和上沿<110>的多层超细硅线条，所有线条的截面均为矩形，该矩形由二个(111)晶面和二个(112)晶面围成。
本发明同时提供一种半导体结构的形成方法，包括：
A.提供一半导体衬底；
B.形成鱼鳍状硅岛Fin；
为保证在步骤D1中对Fin侧壁的各向异性腐蚀能自停止在(111)晶面，从而形成悬空的截面为多边形的多层超细硅线条，衬底晶向、Fin的长度方向和侧壁晶向需满足：对于(100)衬底，Fin的长度方向及其侧壁晶向均沿<110>；对于(110)衬底，Fin的长度方向沿<110>，其侧壁晶向沿<100>；对于(111)衬底，Fin的长度方向沿<110>，其侧壁晶向沿<112>；
Fin的高宽比的选择需满足最终形成的细线条的层数的要求；
C.形成Fin的侧壁腐蚀掩蔽层(侧壁掩膜技术)；
腐蚀掩蔽层的层数与位置决定细线条的层数与位置；通过牺牲层厚度定义出细线条的层间距，为保证经步骤D1后形成的多层超细硅线条上下完全分离，牺牲层厚度(H)与Fin宽度(WFin)间需满足：对于(100)衬底，H>WFin*tan54.7°；对于(110)衬底，H>WFin*cot54.7°；对于(111)衬底，H>0；其中54.7°为硅的(100)晶面与(111)晶面的夹角；
具体实现步骤如下：
C1.制备牺牲层，包括：
C101.在硅衬底上淀积牺牲层材料，所淀积的牺牲层材料厚度大于Fin高度；
C102.通过化学机械抛光(Chemical Mechanical Polishing，CMP)去除Fin顶部的牺牲层材料，露出Fin顶部；
C103.通过刻蚀定义出牺牲层厚度；
C2.制备腐蚀掩蔽层，包括：
C201.在牺牲层上淀积腐蚀掩蔽层材料，所淀积的腐蚀掩蔽层材料厚度大于Fin高度；
C202.通过CMP去除Fin顶部的腐蚀掩蔽层材料，露出Fin顶部；
C203.通过刻蚀定义出腐蚀掩蔽层厚度；
C3.交替重复步骤C1、C2，在Fin的侧壁形成周期性的“牺牲层-腐蚀掩蔽层”堆叠结构；
C4.在Fin顶部淀积腐蚀掩蔽层；
C5.通过光刻在周期性的“牺牲层-腐蚀掩蔽层”堆叠结构上定义出硅的湿法腐蚀窗口；
C6.通过各向异性刻蚀工艺，将光刻定义的图形转移到牺牲层-腐蚀掩蔽层的堆叠结构上，露出硅衬底；
C7.去除牺牲层；
D.形成多层超细硅线条，目的是从Fin的侧壁对其进行各向异性腐蚀，在侧壁腐蚀掩蔽层的保护下，腐蚀最终自停止于(111)晶面，形成多层截面为多边形的超细硅线条，具体实现步骤如下：
D1.通过各向异性腐蚀形成截面为多边形的多层超细硅线条；
D2.将多层超细硅线条去除腐蚀掩蔽层。
进一步地，步骤D2中，在去除腐蚀掩蔽层之后，通过牺牲氧化可将多层超细硅线条的截面改为圆形，并进一步缩小其半径；该牺牲氧化为干法氧化，温度为850～950℃，优选925℃；
进一步地，与经步骤B形成的Fin两端相连的微米尺度的源漏区或STI区可保证经步骤D1形成的多层超细硅线条两端有足够的硅作为支撑；
进一步地，步骤C1、C2、C4中所述淀积可选ALD(Atomic Layer Deposition，原子层淀积)、LPCVD(Low Pressure Chemical Vapor Deposition，低压化学气相淀积)、PECVD(PlasmaEnhanced Chemical Vapor Deposition，等离子体增强化学气相淀积)、ICPECVD(InductivelyCoupled Plasma Enhance Chemical Vapor Deposition，电感耦合等离子体增强化学气相淀积)或溅射等，优选ICPECVD。
进一步地，牺牲层材料可选SiO2，采用BHF(缓冲氢氟酸)溶液进行SiO2牺牲层的释放，BHF溶液浓度为HF:NH4F＝1:30～1:100，优选为1:40，腐蚀温度为常温；腐蚀掩蔽层材料可选Si3N4；采用浓磷酸进行Si3N4腐蚀掩蔽层的去除；腐蚀温度为170℃。
进一步地，牺牲层与腐蚀掩蔽层的材料组合不限于SiO2与Si3N4，但二者需满足：牺牲层与光刻胶的刻蚀速率比大于5:1；腐蚀掩蔽层与光刻胶的刻蚀速率比大于5:1；牺牲层与硅的刻蚀速率比大于5:1；腐蚀掩蔽层与硅的刻蚀速率比大于5:1。
进一步地，采用TMAH(Tetramethyl Ammonium Hydroxide，四甲基氢氧化铵)溶液进行所述硅的各向异性腐蚀；TMAH溶液浓度为10～25wt％，优选25wt％；腐蚀温度为35～60℃，优选40℃。
本发明还提供一种多层围栅纳米线场效应管，使用上述半导体结构的形成方法制备出多层超细硅线条，然后经过标准CMOS工艺即可形成多层围栅纳米线场效应管。
本发明的优点和积极效果如下：
1)最终形成的多层超细硅线条的位置与截面形状均匀、可控；
2)对硅的各向异性腐蚀是自停止的，工艺窗口大，可在同一硅片上实现不同直径的硅线条；
3)ICPECVD具有较强的窄槽填充能力，淀积牺牲层和腐蚀掩蔽层材料时无空洞；
4)结合氧化技术可以制备尺寸小于10nm的线条，满足小尺寸器件关键工艺的要求；
5)采用TMAH溶液湿法腐蚀多晶硅，操作简便，安全；并且不会引入金属离子，适用于集成电路制造工艺中；
6)采用自上而下的加工方法，完全和体硅平面晶体管工艺兼容，工艺成本代价小。
附图说明
图1-14是本发明提出的基于各向异性腐蚀制备多层超细硅线条结构的工艺流程示意图。各图中，(a)为俯视图，(b)(c)分别为(a)中沿A-A’和B-B’的剖面图。
其中：
图1各向异性刻蚀形成鱼鳍状硅岛结构及与之相连的源漏区；
图2淀积牺牲层，CMP露出Fin顶部；
图3刻蚀定义牺牲层厚度；
图4淀积硅的腐蚀掩蔽层，CMP露出Fin顶部；
图5刻蚀定义腐蚀掩蔽层厚度；
图6淀积并定义第二层牺牲层厚度；
图7淀积并CMP顶部腐蚀掩蔽层；
图8定义并刻蚀出硅的各向异性腐蚀窗口；
图9释放牺牲层；
图10～图12各向异性腐蚀形成截面为多边形的多层超细硅线条；
图13超细线条的牺牲氧化，并通过湿法腐蚀去除包裹硅线条的氧化层，最终得到截面为圆形的多层超细硅线条。
图14为图例。
具体实施方式
下面结合附图和具体实例对本发明进行详细说明。
实施例1：
根据下列步骤可以实现2层直径约10nm的圆形纳米线结构：
1)在(111)体硅衬底上热生长SiO2作为硬掩膜与硅衬底间的应力缓冲层；
2)LPCVDSi3N4作为刻蚀硬掩膜；
3)通过光刻在硬掩膜上定义出Fin及与Fin两端相连的源漏区，其中Fin结构的宽度为20nm，长度为300nm，长度方向与侧壁晶向均沿<110>；
4)通过各向异性刻蚀将图形转移到硬掩膜上，露出硅衬底；
5)通过各向异性刻蚀将硬掩膜上的图形转移到硅衬底上，形成Fin及与Fin两端相连的源漏区，其中Fin结构的高度为宽度为20nm，长度为300nm，长度方向与侧壁晶向均沿<110>；
6)去除光刻胶；
7)用热(170℃)的浓磷酸去除Si3N4刻蚀硬掩膜；
8)用BHF溶液(HF:NH4F＝1:40)去除SiO2应力缓冲层，如图1所示；
9)ICPECVDSiO2；
10)CMP露出Fin顶部，如图2所示；
11)各向异性刻蚀去除SiO2，剩余SiO2作为第一层牺牲层，如图3所示；
12)ICPECVDSi3N4；
13)CMP露出Fin顶部，如图4所示；
14)各向异性刻蚀去除Si3N4，剩余Si3N4作为第一层硅的腐蚀掩蔽层，如图5所示；
15)ICPECVDSiO2；
16)CMP露出Fin顶部；
17)各向异性刻蚀去除SiO2，剩余SiO2作为第二层牺牲层，如图6所示；
18)ICPECVDSi3N4；
19)CMP留下Si3N4作为顶部硅的腐蚀掩蔽层，如图7所示；
20)电子束光刻定义硅的腐蚀窗口；
21)各向异性干法刻蚀去除窗口内的SiO2-Si3N4叠层材料，露出底部的硅；
22)去除光刻胶，如图8所示；
23)用BHF溶液(HF:NH4F＝1:40)去除SiO2牺牲层，如图9所示；
24)用溶液浓度为25wt％的TMAH在40℃下各向异性腐蚀硅，使上下的细线条完全分离，如图10所示；
25)用热(170℃)的浓磷酸去除Si3N4腐蚀掩蔽层；
26)在925℃下进行干氧氧化，得到截面为圆形、直径为5nm的硅纳米线；
27)用BHF溶液(HF:NH4F＝1:40)去除包裹在硅纳米线周围的氧化层，如图13所示；最终得到直径约5nm的2层纳米线结构。
实施例2：
根据下列步骤可以实现2层直径约5nm的方形纳米线结构：
1)在(100)体硅衬底上热生长SiO2作为硬掩膜与硅衬底间的应力缓冲层；
2)LPCVDSi3N4作为刻蚀硬掩膜；
3)通过光刻在硬掩膜上定义出Fin及与Fin两端相连的源漏区，其中Fin结构的宽度为10nm，长度为300nm，长度方向沿<110>，侧壁晶向均沿<112>；
4)通过各向异性刻蚀将图形转移到硬掩膜上，露出硅衬底；
5)通过各向异性刻蚀将硬掩膜上的图形转移到硅衬底上，形成Fin及与Fin两端相连的源漏区，其中Fin结构的高度为宽度为10nm，长度为300nm，长度方向沿<110>，侧壁晶向均沿<112>；
6)去除光刻胶；
7)用热(170℃)的浓磷酸去除Si3N4刻蚀硬掩膜；
8)用BHF溶液(HF:NH4F＝1:40)去除SiO2应力缓冲层；
9)ICPECVDSiO2；
10)CMP露出Fin顶部；
11)各向异性刻蚀去除SiO2，剩余SiO2作为第一层牺牲层；
12)ICPECVDSi3N4；
13)CMP露出Fin顶部；
14)各向异性刻蚀去除Si3N4，剩余Si3N4作为第一层硅的腐蚀掩蔽层；
15)ICPECVDSiO2；
16)CMP露出Fin顶部；
17)各向异性刻蚀去除SiO2，剩余SiO2作为第二层牺牲层；
18)ICPECVDSi3N4；
19)CMP留下Si3N4作为顶部硅的腐蚀掩蔽层，；
20)电子束光刻定义硅的腐蚀窗口；
21)各向异性干法刻蚀去除窗口内的SiO2-Si3N4叠层材料，露出底部的硅；
22)去除光刻胶；
23)用BHF溶液(HF:NH4F＝1:40)去除SiO2牺牲层；
24)用溶液浓度为25wt％的TMAH在40℃下各向异性腐蚀硅，使上下的细线条完全分离，如图11所示；
25)用热(170℃)的浓磷酸去除Si3N4腐蚀掩蔽层；
最终得到直径约10nm的2层截面为方形的纳米线结构。
实施例3：
制备3层直径约10nm的纳米线结构。
1)在(110)体硅衬底上热生长SiO2作为刻蚀硬掩膜与硅衬底间的应力缓冲层；
2)LPCVDSi3N4作为硅的刻蚀硬掩膜；
3)通过光刻定义Fin及与Fin两端相连的源漏区，其中Fin结构的宽度为30纳米，长度为300纳米，长度方向沿<110>晶向，侧壁沿<100>晶向；
4)通过各向异性刻蚀将图形转移到硬掩膜上，露出硅衬底；
5)通过各向异性刻蚀将硬掩膜上的图形转移到硅衬底上，形成Fin及与Fin两端相连的源漏区，其中Fin结构的高度为宽度为30纳米，长度为300纳米，长度方向沿<110>晶向，侧壁沿<100>晶向；
6)去除光刻胶；
7)用热(170℃)的浓磷酸去除Si3N4刻蚀硬掩膜；
8)用BHF溶液(HF:NH4F＝1:40)去除SiO2应力缓冲层；
9)ICPECVD多晶锗；
10)CMP露出Fin顶部；
11)各向异性刻蚀去除多晶锗，剩余多晶锗作为第一层牺牲层；
12)ICPECVDSiO2；
13)CMP露出Fin顶部；
14)各向异性刻蚀去除SiO2，剩余SiO2作为第一层硅的腐蚀掩蔽层；
15)ICPECVD多晶锗；
16)CMP露出Fin顶部；
17)各向异性刻蚀去除多晶锗，剩余多晶锗作为第二层牺牲层；
18)ICPECVDSiO2；
19)CMP露出Fin顶部；
20)各向异性刻蚀去除SiO2，剩余SiO2作为第二层硅的腐蚀掩蔽层；
21)ICPECVD多晶锗；
22)CMP露出Fin顶部；
23)各向异性刻蚀去除多晶锗，剩余多晶锗作为第三层牺牲层；
24)ICPECVDSiO2；
25)CMP留下SiO2作为顶部硅的腐蚀掩蔽层；
26)采用193nm浸没式光刻定义硅的腐蚀窗口；
27)各向异性干法刻蚀去除窗口内的多晶锗-SiO2叠层材料，露出底部的硅；
28)去除光刻胶；
29)采用氨水与双氧水的混合液(NH4OH:H2O2:H2O＝2:2:5)在室温下去除多晶锗牺牲层；
30)用溶液浓度为25wt％的TMAH在40℃下各向异性腐蚀硅，使上下的细线条完全分离，如图12所示；
31)采用BHF溶液(HF:NH4F＝1:40)去除SiO2腐蚀掩蔽层；
32)在925℃下进行干氧氧化，得到截面为圆形、直径为5nm的硅纳米线；
33)用BHF溶液(HF:NH4F＝1:40)去除包裹在硅纳米线周围的氧化层；
最终得到直径约10nm的3层纳米线结构。
本发明实施例并非用以限定本发明。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。

Claims (12)

1.一种半导体结构，包括：一半导体衬底，多层超细硅线条，其特征是，所述的多层超细硅线条的界面形状受衬底晶向和线条轴向晶向双重控制：
对于(100)衬底上沿<110>的多层超细硅线条，顶层线条的截面为五边形，该五边形由一个(100)晶面、二个(110)晶面和二个(111)晶面围成；以下各层线条的截面为六边形，该六边形由两个(110)晶面和四个(111)晶面围成；
对于(110)衬底上沿<110>的多层超细硅线条，顶层线条的截面为五边形，该五边形由一个(110)晶面、二个(100)晶面和二个(111)晶面围成；以下各层线条的截面为六边形，该六边形由两个(100)晶面和四个(111)晶面围成；
对于(111)衬底和上沿<110>的多层超细硅线条，所有线条的截面均为矩形，该矩形由二个(111)晶面和二个(112)晶面围成。
2.一种半导体结构的形成方法，其特征是，包括如下步骤：
A.提供一半导体衬底；
B.形成鱼鳍状硅岛Fin；需满足条件：对于(100)衬底，Fin的长度方向及其侧壁晶向均沿<110>；对于(110)衬底，Fin的长度方向沿<110>，其侧壁晶向沿<100>；对于(111)衬底，Fin的长度方向沿<110>，其侧壁晶向沿<112>；Fin的高宽比的选择需满足最终形成的细线条的层数的要求；
C.形成Fin的侧壁腐蚀掩蔽层；具体实现步骤如下：
C1.制备牺牲层，包括：
C101.在硅衬底上淀积牺牲层材料，所淀积的牺牲层材料厚度大于Fin高度；
C102.通过化学机械抛光去除Fin顶部的牺牲层材料，露出Fin顶部；
C103.通过刻蚀定义出牺牲层厚度；
C2.制备腐蚀掩蔽层，包括：
C201.在牺牲层上淀积腐蚀掩蔽层材料，所淀积的腐蚀掩蔽层材料厚度大于Fin高度；
C202.通过CMP去除Fin顶部的腐蚀掩蔽层材料，露出Fin顶部；
C203.通过刻蚀定义出腐蚀掩蔽层厚度；
C3.交替重复步骤C1、C2，在Fin的侧壁形成周期性的“牺牲层-腐蚀掩蔽层”堆叠结构；
C4.在Fin顶部淀积腐蚀掩蔽层；
C5.通过光刻在周期性的“牺牲层-腐蚀掩蔽层”堆叠结构上定义出硅的湿法腐蚀窗口；
C6.通过各向异性刻蚀工艺，将光刻定义的图形转移到牺牲层-腐蚀掩蔽层的堆叠结构上，露出硅衬底；
C7.去除牺牲层；
D.形成多层超细硅线条，目的是从Fin的侧壁对其进行各向异性腐蚀，在侧壁腐蚀掩蔽层的保护下，腐蚀最终自停止于(111)晶面，形成多层截面为多边形的超细硅线条，具体实现步骤如下：
D1.通过各向异性腐蚀形成截面为多边形的多层超细硅线条；
D2.将多层超细硅线条去除腐蚀掩蔽层。
3.如权利要求2所述的半导体结构的形成方法，其特征是，步骤D2中，在去除腐蚀掩蔽层之后，通过牺牲氧化将多层超细硅线条的截面改为圆形，并进一步缩小其半径。
4.如权利要求2所述的半导体结构的形成方法，其特征是，与经步骤B形成的Fin两端相连的源漏区或STI区为微米尺度。
5.如权利要求2所述的半导体结构的形成方法，其特征是，步骤C1、C2、C4中所述淀积可选ALD、LPCVD、PECVD、ICPECVD或溅射。
6.如权利要求2所述的半导体结构的形成方法，其特征是，所述牺牲层材料为SiO2，采用BHF溶液进行SiO2牺牲层的释放，BHF溶液浓度为HF:NH4F＝1:30～1:100，腐蚀温度为常温；所述腐蚀掩蔽层材料选Si3N4；采用浓磷酸进行Si3N4腐蚀掩蔽层的去除；腐蚀温度为170℃。
7.如权利要求2所述的半导体结构的形成方法，其特征是，所述牺牲层与腐蚀掩蔽层的材料组合需满足：牺牲层与光刻胶的刻蚀速率比大于5:1；腐蚀掩蔽层与光刻胶的刻蚀速率比大于5:1；牺牲层与硅的刻蚀速率比大于5:1；腐蚀掩蔽层与硅的刻蚀速率比大于5:1。
8.如权利要求2所述的半导体结构的形成方法，其特征是，采用TMAH溶液进行所述硅的各向异性腐蚀；TMAH溶液浓度为10～25wt％；腐蚀温度为35～60℃。
9.如权利要求2所述的半导体结构的形成方法，其特征是，步骤C中，腐蚀掩蔽层的层数与位置决定细线条的层数与位置；通过牺牲层厚度定义出细线条的层间距，为保证经步骤D1后形成的多层超细硅线条上下完全分离，牺牲层厚度H与Fin宽度WFin间需满足：对于(100)衬底，H>WFin*tan54.7°；对于(110)衬底，H>WFin*cot54.7°；对于(111)衬底，H>0；其中54.7°为硅的(100)晶面与(111)晶面的夹角。
10.如权利要求3所述的半导体结构的形成方法，其特征是，所述牺牲氧化为干法氧化，温度为850～950℃。
11.如权利要求6所述的半导体结构的形成方法，其特征是，所述的BHF溶液浓度为HF:NH4F＝1:40。
12.一种多层围栅纳米线场效应管，其特征是，用权利要求1至11中任一种半导体结构的形成方法制备出多层超细硅线条，然后经过标准CMOS工艺即可形成多层围栅纳米线场效应管。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015192691A1 (zh) * 2014-06-19 2015-12-23 北京大学 一种半导体结构及其形成方法
CN108231594A (zh) * 2017-12-21 2018-06-29 上海集成电路研发中心有限公司 一种FinFET器件的制作方法
CN109742025A (zh) * 2019-01-21 2019-05-10 中国科学院微电子研究所 一种环栅纳米线器件的制造方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9543440B2 (en) * 2014-06-20 2017-01-10 International Business Machines Corporation High density vertical nanowire stack for field effect transistor
WO2019017326A1 (ja) * 2017-07-19 2019-01-24 グローバルウェーハズ・ジャパン株式会社 三次元構造体の製造方法、縦型トランジスタの製造方法、縦型トランジスタ用ウェ－ハおよび縦型トランジスタ用基板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080135949A1 (en) * 2006-12-08 2008-06-12 Agency For Science, Technology And Research Stacked silicon-germanium nanowire structure and method of forming the same
US20100295021A1 (en) * 2009-05-21 2010-11-25 International Business Machines Corporation Single Gate Inverter Nanowire Mesh
CN102509697A (zh) * 2011-11-01 2012-06-20 北京大学 一种制备超细线条的方法
CN102509698A (zh) * 2011-11-23 2012-06-20 北京大学 一种制备超细线条的方法
CN103700582A (zh) * 2013-12-27 2014-04-02 中国科学院微电子研究所 一种锗纳米线叠层结构的制作方法
CN103824759A (zh) * 2014-03-17 2014-05-28 北京大学 一种制备多层超细硅线条的方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5661524B2 (ja) * 2011-03-22 2015-01-28 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
US8796695B2 (en) * 2012-06-22 2014-08-05 United Microelectronics Corp. Multi-gate field-effect transistor and process thereof
CN104037159B (zh) * 2014-06-19 2017-01-25 北京大学 一种半导体结构及其形成方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080135949A1 (en) * 2006-12-08 2008-06-12 Agency For Science, Technology And Research Stacked silicon-germanium nanowire structure and method of forming the same
US20100295021A1 (en) * 2009-05-21 2010-11-25 International Business Machines Corporation Single Gate Inverter Nanowire Mesh
CN102509697A (zh) * 2011-11-01 2012-06-20 北京大学 一种制备超细线条的方法
CN102509698A (zh) * 2011-11-23 2012-06-20 北京大学 一种制备超细线条的方法
CN103700582A (zh) * 2013-12-27 2014-04-02 中国科学院微电子研究所 一种锗纳米线叠层结构的制作方法
CN103824759A (zh) * 2014-03-17 2014-05-28 北京大学 一种制备多层超细硅线条的方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015192691A1 (zh) * 2014-06-19 2015-12-23 北京大学 一种半导体结构及其形成方法
CN108231594A (zh) * 2017-12-21 2018-06-29 上海集成电路研发中心有限公司 一种FinFET器件的制作方法
CN108231594B (zh) * 2017-12-21 2020-10-02 上海集成电路研发中心有限公司 一种FinFET器件的制作方法
CN109742025A (zh) * 2019-01-21 2019-05-10 中国科学院微电子研究所 一种环栅纳米线器件的制造方法

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