CN108231590A - 水平纳米线半导体器件 - Google Patents

水平纳米线半导体器件 Download PDF

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Publication number
CN108231590A
CN108231590A CN201711191237.2A CN201711191237A CN108231590A CN 108231590 A CN108231590 A CN 108231590A CN 201711191237 A CN201711191237 A CN 201711191237A CN 108231590 A CN108231590 A CN 108231590A
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nano
nano wire
sacrificial layer
interval
semiconductor devices
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CN201711191237.2A
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CN108231590B (zh
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K·沃斯汀
H·梅尔腾斯
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Interuniversitair Microelektronica Centrum vzw IMEC
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Interuniversitair Microelektronica Centrum vzw IMEC
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Abstract

一种形成包含水平纳米线的半导体器件的方法。该方法包括在基片上沉积(410)多层堆叠，该多层堆叠包括交替的第一牺牲层(150)和纳米线材料(140)的层；在多层堆叠中形成(420)至少一个鳍片；围绕鳍片施加(430)额外的牺牲层(510)，使得所得的牺牲层(520)围绕整个纳米线材料形成；由所得的牺牲层(520)在纳米线材料的末端围绕纳米线材料形成(440)纳米线间隔(810)。

Description

水平纳米线半导体器件
技术领域
本发明涉及半导体器件领域。本发明更具体涉及形成包含水平纳米线的半导体器件的方法，以及用于制备包含纳米线的半导体器件的鳍片。
背景技术
形成堆叠纳米线是降低半导体器件特征尺寸的重要步骤。
必须解决的一个重要问题是减小由于晶体管栅极和源漏区之间的重叠引起的寄生电容。
为了最大程度地减小寄生电容，形成内部间隔必须是纳米线集成方案中的一个集成部分。
形成内部间隔对形成包含水平纳米线的半导体器件的方法提出了额外的要求。因此，形成这种半导体器件的方法还有改善的空间。
发明内容
本发明实施方式的一个目的是提供良好的形成包含水平纳米线的半导体器件的方法，以及提供良好的包含纳米线的半导体器件。
上述目的是通过本发明所述的一种方法和器件实现的。
在第一方面，本发明的实施方式涉及形成包含水平纳米线的半导体器件的方法。该方法包括：
-在基片上沉积多层堆叠，该多层堆叠包含交替的第一牺牲层和纳米线材料层，
-在多层堆叠中形成至少一个鳍片，
-在鳍片周围施加额外的牺牲层，使得所得的牺牲层在整个纳米线材料周围形成，
-由所得的牺牲层在纳米线材料的末端围绕纳米线材料形成纳米线间隔。
在本发明的实施方式中，所得牺牲层包含第一牺牲层和额外的牺牲层。本发明实施方式的优点在于所得牺牲层在整个纳米线周围形成。这样可以在纳米线材料的末端围绕纳米线材料形成纳米线间隔。因为在纳米线材料周围形成纳米线间隔，纳米线间隔的所有部分(例如，顶部，底部和侧部，围绕各不同纳米线的部分)都是自动对齐的。原因在于所有这些部分都是使用相同的工艺步骤形成的。因此，对齐是依据本发明实施方式的集成方案所固有的。因此，围绕不同纳米线的间隔之间的自对齐得以实现。这与现有技术的方法不同，现有技术中需要对栅极间隔(紧挨着栅极施加)与内间隔之间进行对齐。在现有技术的方法中，需要谨慎调节内间隔模块，例如通过匹配选择性氧化或去除到栅极间隔的厚度。因为在纳米线材料的末端围绕整个纳米线材料形成纳米线间隔，本发明实施方式的优点在于对于所有在方法中形成的纳米线，栅极长度相同。本发明的实施方式的优点在于它们适用于不同纳米线器件结构。例子有Si，SiGe，Ge或III/V纳米线集成方案。
在本发明实施方式中，在施加额外牺牲层后，施加伪栅极堆叠。
在本发明的实施方式中，伪栅极堆叠包含伪栅极电介质和伪栅极。伪栅极电介质由此在栅极蚀刻过程中保护鳍片。在本发明的实施方式中，在伪栅极形成过程中施加额外的牺牲层。
在本发明的实施方式中，形成鳍片包括蚀刻或STI凹陷。
在本发明的实施方式中，在形成至少一个鳍片和STI后，但在形成伪栅极电介质和伪栅极之前，形成额外的牺牲层。因此，本发明实施方式的一个优点在于额外的牺牲层正确地设置在随后的模块中，这样纳米线间隔的自对齐得以实现。
在本发明的实施方式中，在形成纳米线间隔的过程中，部分所得的牺牲层被选择性地除去。
在本发明的实施方式中，部分所得的牺牲层被除去，并且被电介质代替(在形成纳米线间隔的区域中的部分)。在将形成S/D的区域中和将形成栅极的区域中，所得牺牲层仅仅在流动的不同阶段被除去。
在本发明的实施方式中，部分所得的牺牲层被各向同性地除去。
数种方法可用于选择性去除，这取决于纳米线和牺牲层的组成：
(1)Si线×SiGe选择性蚀刻：选择性蚀刻的方法是例如HCl(气体)，干蚀刻，HF:H2O2:CH3COOH混合物；
(2)SiGe线×Si选择性蚀刻：可通过例如TMAH、NH4OH、KOH...(碱性溶液)或干蚀刻进行；
(3)Ge线×SiGe选择性蚀刻，使用配制的混合物；
(4)InGaAs线×InP选择性蚀刻，在HCl(水溶液)中。
在本发明的实施方式中，使用保形沉积施加额外的牺牲层。
在本发明的实施方式中，源极或漏极区域紧邻纳米线间隔施加，这样纳米线间隔位于伪栅极和源极或漏极区域之间。
在本发明的实施方式中，对所得牺牲层进行蚀刻，以获得纳米线。
在本发明的实施方式中，在纳米线周围施加栅极堆叠。
本发明实施方式的一个优点在于栅极堆叠与纳米线间隔对齐。因为纳米线间隔针对不同的纳米线对齐，这意味着可以实现具有固定栅极长度的纳米线。
在第二方面，本发明的实施方式涉及一种半导体器件，该半导体器件包括至少一个由纳米线材料制成的纳米线，在纳米线第一末端的第一电极，以及在纳米线周围的控制电极，以及在控制电极和第一电极之间的在纳米线第一末端围绕纳米线的第一间隔。
在本发明的实施方式中，半导体器件包括在纳米线与第一末端相对的第二末端处的第二电极，以及在控制电极和第二电极之间的在纳米线第二末端围绕整个纳米线的第二间隔。
在依据本发明的实施方式中，第一电极是源电极，第二电极是漏电极，控制电极是栅电极。本发明实施方式的一个优点在于对于半导体器件的不同纳米线，栅极长度是相同的，而且在纳米线周围栅极长度是均一的。原因在于在整个纳米线周围存在间隔。
在本发明的实施方式中，纳米线材料包含至少一种选自Si和Ge的元素，或选自III-V化合物材料。
在本发明的实施方式中，纳米线材料可以例如包含Si，或Ge，或SiGe，III-V化合物材料。这种III-V化合物材料可以是二元的，例如GaAs或GaP，或者可以是三元的，例如InGaAs。
在本发明的实施方式中，纳米线材料是掺杂的。
本发明特定和优选的方面在所附独立和从属权利要求中阐述。可以将从属权利要求中的特征与独立权利要求中的特征以及其它从属权利要求中的特征进行适当组合，而并不仅限于权利要求书中明确所述的情况。
本发明的这些和其它方面将参考下文所述的实施方式披露并阐明。
附图的简要说明
图1示意性地显示了由多层堆叠制备的鳍片在去除内部牺牲层之前和之后的纵向截面。
图2示意性地显示了由多层堆叠制备的鳍片的纵向截面，其中引入间隔以减小源极/漏极到栅极的电容。
图3示意性地显示栅极间隔与内间隔之间的错位。
图4是显示依据本发明示例性实施方式的方法的方法步骤顺序的流程图。
图5示意性地显示依据本发明实施方式的包含额外牺牲层的鳍片的截面。
图6示意性地显示依据本发明实施方式的包含额外牺牲层的鳍片的纵向截面。
图7显示由多层堆叠开始形成内间隔，所述多层堆叠在整个纳米线材料周围不包含所得牺牲层。
图8显示依据本发明实施方式由多层堆叠开始形成纳米线间隔，所述多层堆叠在整个纳米线材料周围包含牺牲层。
权利要求书中的任何引用符号不应理解为限制本发明的范围。在不同的图中，相同的附图标记表示相同或类似的元件。
示例性实施方式的详细描述
将就具体实施方式并参照某些附图对本发明进行描述，但本发明并不受此限制，仅由权利要求书限定。描述的附图仅是说明性的且是非限制性的。在附图中，一些元素的尺寸可能被夸大且未按比例尺绘画以用于说明目的。所述尺寸和相对尺寸不与本发明实践的实际减小相对应。
在说明书和权利要求书中的术语第一、第二等用来区别类似的元件，而不一定是用来描述时间、空间、等级顺序或任何其它方式的顺序。应理解，如此使用的术语在合适情况下可互换使用，本发明所述的实施方式能够按照本文所述或说明的顺序以外的其它顺序进行操作。
此外，在说明书和权利要求书中，术语顶、之下等用于描述目的，而不一定用于描述相对位置。应理解，如此使用的术语在合适情况下可互换使用，本发明所述的实施方式能够按照本文所述或说明的取向以外的其它取向进行操作。
应注意，权利要求中使用的术语“包含”不应解释为被限制为其后列出的部分，其不排除其它元件或步骤。因此，其应被理解为指出所述特征、集成、步骤或组分的存在，但这并不排除一种或多种其它特征、集成、步骤或组分或其组合的存在或添加。因此，表述“包括部件A和B的装置”的范围不应被限制为所述装置仅由组件A和B构成。其表示对于本发明，所述装置的相关组件仅为A和B。
说明书中提及的“一个实施方式”或“一种实施方式”是指连同实施方式描述的具体特征、结构或特性包括在本发明的至少一个实施方式中。因此，在说明书中各处出现的短语“在一个实施方式中”或“在一种实施方式中”不一定全部指同一个实施方式，但可能全部都指同一个实施方式。此外，具体特征、结构或特性可以任何合适方式在一个或多个实施方式中组合，这对于本领域普通技术人员而言是显而易见的。
类似地，应理解，在本发明的示例性实施方式的描述中，本发明的不同特征有时组合成一个单一实施方式、特征或其描述，这是为了简化公开内容并帮助理解本发明的一个或多个不同方面。然而，本公开内容中的方法不应被理解为反映一项发明，请求保护的本发明需要比各权利要求中明确引用的具有更多的特征。并且，如同所附权利要求所反映的那样，发明方面包括的特征可能会少于前述公开的一个单一实施方式的全部特征。因此，具体说明之后的权利要求将被明确地纳入该具体说明，并且各权利要求本身基于本发明独立的实施方式。
此外，当本文所述的一些实施方式包括一些但不包括其它实施方式中所包括的其它特征时，不同实施方式的特征的组合应意在包括在本发明范围内，并且形成不同的实施方式，这应被本领域技术人员所理解。例如，在之后的权利要求中，所请求保护的任何实施方式可以任何组合形式使用。
本文的描述中阐述了众多的具体细节。然而应理解，本发明的实施方式可不用这些具体细节进行实施。在其它情况中，为了不混淆对该说明书的理解，没有详细描述众所周知的方法、步骤和技术。
在本发明的实施方式中，提及纳米线间隔，就是提及在纳米线材料末端围绕整个纳米线材料的间隔。该纳米线材料末端可以是例如紧邻于伪栅极的纳米线材料。
在本发明的实施方式中，提及栅极间隔，就是提及紧邻于伪栅极和伪栅极电介质的间隔。该间隔也称为初始间隔。
在本发明的实施方式中，提及纳米线材料，就是提及制成纳米线的材料。
图1示意性地显示了由多层堆叠100制备的鳍片100的纵向截面。显示了在置换金属栅极(RMG)方法过程中选择性蚀刻之前(左图)和之后(右图)的鳍片。左图显示源极或漏极区域(S/D)160，纳米线材料140，第一牺牲层150，以及在其上方的伪栅极电介质(例如氧化物)130和伪栅极120，紧邻伪栅极120和伪栅极电介质130的栅极间隔110，以及紧邻S/D区域160的延伸180。这些延伸180是(掺杂)区域，形成低掺杂或内在纳米线通道与重度掺杂的S/D区域之间的连接。这些延伸180可在伪栅极形成后通过离子注入制备，或者在S/D形成后通过扩散制备。右图显示蚀刻后的纳米线140。该图显示选择性蚀刻导致形成间隔底切部170。该间隔底切部导致由于栅极到源极以及栅极到漏极的重叠而产生的寄生电容。
在现有技术的方法中，可通过提供内间隔来解决该问题。这种间隔位于纳米线之间。这种内间隔的优点在于可以降低源极/漏极到栅极的电容。图2示意性地显示了这一点，在图2中显示了内间隔210，降低了栅极到源极以及栅极到漏极的重叠的影响。除了内间隔210外，该图与图1相同。该堆叠通过施加以下步骤形成。在第一步骤中，在空白晶片上沉积多层堆叠。在下一步骤中，该多层堆叠图案化为鳍片100。然后，伪栅极120沉积在鳍片周围。该伪栅极120可以例如包含无定形硅。在沉积伪栅极120之前，伪栅极电介质130可以已经沉积在鳍片周围。伪栅极电介质可以例如是氧化硅。在其它步骤中，形成栅极间隔110，源极或漏极区域160。
内间隔210的形成可以数种方式进行，例如：
(1)对于凹陷的源极-漏极，进行第一FIN凹陷蚀刻，然后，
a.牺牲层的选择性凹陷，然后沉积，然后源极/漏极沉积，
b.牺牲层上的选择性沉积或牺牲层的选择性氧化，
c.牺牲层的选择性凹陷，然后牺牲层上的选择性沉积或牺牲层的选择性氧化，然后源极/漏极沉积，
(2)对于环绕源极-漏极和触点，可以类似于上述方法进行，但是无凹陷FIN。源极/漏极模块中的线释放可与上述(1)中所述的步骤组合。
选择性蚀刻可以数种方式进行。可使用的选择性蚀刻例如是：
-SiGe-Si选择性蚀刻：气相HCl，干蚀刻，HF/H2O2/CH3COOH混合物和配制的混合物；
-Si-SiGe:NH4OH，TMAH，KOH，...(通常为碱性溶液)；
-SiGe-Ge:配制的化学混合物；
-InP-InGaAs:HCl水溶液。
选择性氧化可例如通过蒸气氧化或干氧化来进行。
例如，还可以通过选择性氧化、或者选择性蚀刻与选择性氧化的组合来形成内间隔。
在图2中，使用TMAH蚀刻(氢氧化四甲铵)来进行选择性蚀刻。在图2中，内间隔210和栅极间隔120很好地对齐。
当形成这种内间隔时，优选该间隔与紧邻伪栅极的栅极间隔对齐，以对所有堆叠纳米线获得相同且均一的通道长度。
但是，使内间隔210对齐栅极间隔110是困难的，并非显而易见，而是需要谨慎的工艺控制。因此，内间隔210与栅极间隔110的对齐很麻烦，可能导致彼此之间的错位。其中的一个例子如图3中的尺寸线‘x’所示。
因此，在本发明实施方式中，在设置伪栅极之前，施加额外的牺牲层。在本发明的实施方式中，所得的牺牲层围绕在纳米线周围。在第一方面，本发明的实施方式涉及形成包含水平纳米线的半导体器件的方法400。该方法包括在基片上沉积多层堆叠的步骤410。多层堆叠包括交替排列的纳米线材料层和第一牺牲层。该方法包括在多层堆叠中形成至少一个鳍片的步骤420。因此，该鳍片包括交替排列的第一牺牲层和纳米线材料。该方法包括在形成鳍片后在鳍片周围施加额外的牺牲层的步骤430，这样所得的牺牲层在整个纳米线周围形成。额外的牺牲层可例如在鳍片蚀刻后、在STI凹陷后或伪栅极形成之前形成。该方法包括在整个纳米线周围形成纳米线间隔的步骤440。由所得的牺牲层开始形成纳米线间隔。因此，本发明实施方式的优点在于纳米线间隔在纳米线材料末端处的纳米线材料周围。因此，围绕纳米线材料的对齐将由该所得牺牲层的选择性去除来决定。因此，产生自对齐的集成方案，意味着对齐是该集成方案所固有的。这与现有技术的方法相比，在现有技术方法中无额外的牺牲层形成，因此在整个纳米线材料周围无间隔。在这些现有技术方法中，基于第一牺牲层形成的间隔是纳米线材料之间的内间隔。因此，在这些现有技术方法中，需要内间隔与栅极间隔对齐。
本发明实施方式的一个重要方面是在鳍片周围施加额外的牺牲层，这样所得的牺牲层在整个纳米线材料周围形成。如果额外的牺牲层仅在顶部，则对齐将仅存在于鳍片顶上。在仅在顶部有间隔的情况中，顶部纳米线的界面将自对齐于其它纳米线的底部和顶部界面，但是所有纳米线的侧壁界面将不会自对齐于该参考平面。
图4是显示依据本发明示例性实施方式的方法的方法步骤顺序的流程图。该方法包括在晶片上沉积(410)多层堆叠，形成(420)鳍片，施加(430)额外的牺牲层，形成(440)纳米线间隔。
图5的左图示意性地示出了鳍片的截面。在鳍片蚀刻之后或者在STI凹陷之后得到该截面图。该截面显示纳米线材料140和第一牺牲层150交替排列的堆叠。右图显示在施加覆盖鳍片的额外的牺牲层510之后的纳米线堆叠的截面。这样产生所得的牺牲层520，该牺牲层520在整个纳米线材料140周围形成。所得牺牲层520包括额外的牺牲层510和第一牺牲层150。在本发明的该示例性实施方式中，额外的牺牲层510由与第一牺牲层150相同的材料制成。在额外的牺牲层510周围施加伪栅极电介质530，在伪栅极电介质530周围施加伪栅极540。
接着进行标准纳米线加工步骤，例如栅极蚀刻和间隔蚀刻。
图6的左图示意性地示出了如图5所示的相同鳍片或纳米线堆叠的纵向截面。右图显示在施加额外的牺牲层510、伪栅极电介质530和伪栅极540之后纳米线堆叠的纵向截面。
图7显示由在整个纳米线材料周围不包含所得牺牲层的多层堆叠开始形成内间隔210。左图显示这种堆叠的纵向截面。该堆叠包括交替堆叠的纳米线材料140和第一牺牲层150。伪栅极电介质130位于最上面纳米线材料层140的顶部上。伪栅极120位于伪栅极电介质130的顶部上。伪栅极电介质在伪栅极蚀刻过程中保护鳍片结构。图7显示紧邻伪栅极120和伪栅极电介质130的栅极间隔110。在鳍片的源极/漏极区域中形成凹陷后，并且在形成内间隔210(通过例如选择性氧化或选择性蚀刻，保形电介质沉积和回蚀来进行)之后，以及在通过选择性外延生长形成源极/漏极160之后，
得到如图7的中间图所示的堆叠。在这种现有技术方法中，栅极间隔110与内间隔210之间的对齐由内间隔形成工艺决定。例如，可通过定时选择性去除和/或选择性氧化来进行控制。但是，这种控制是有难度的，因此可能导致栅极间隔110与内间隔210之间的错位，如图7的尺寸线‘x’所示。在RMG模块中选择性蚀刻后，产生图7的右图所示的堆叠。如图中所示，导致在纳米线一侧上的栅极间隔与纳米线另一侧上的内间隔之间的错位。
图8显示依据本发明实施方式由在整个纳米线材料140周围包含所得牺牲层520的多层堆叠开始形成纳米线间隔810。左图显示这种堆叠的纵向截面。该堆叠包括交替堆叠的纳米线材料140和第一牺牲层150。另外，该堆叠包含全部在堆叠周围的额外的牺牲层510。伪栅极电介质530位于额外的牺牲层510的顶部上。伪栅极540位于伪栅极电介质530的顶部上。图8显示紧邻伪栅极540和伪栅极电介质530的栅极间隔110。在形成纳米线间隔810(该纳米线间隔由所得牺牲层520开始形成，可通过例如选择性氧化或选择性蚀刻，保形电介质沉积和回蚀，或选择性蚀刻和沉积/氧化的组合来形成)和源极/漏极160(例如通过选择性外延生长来进行)之后，得到如图8的中间图所示的堆叠。由紧邻伪栅极540的所得牺牲层520开始形成纳米线间隔810。纳米线间隔810位于源极或漏极160(S/D)和伪栅极540之间。因此，本发明实施方式的优点在于纳米线间隔810在整个纳米线周围。当由其中牺牲层520都在纳米线周围的堆叠开始时，可以实现该优点。因为纳米线间隔810围绕整个纳米线，所以自动获得纳米线上方、下方和侧面上的间隔对齐。原因在于，围绕整个纳米线的纳米线间隔810的每一部分都是使用相同的工艺步骤由围绕整个纳米线的牺牲层520开始制得的。因此，本发明实施方式的优点在于无需控制栅极间隔110和纳米线间隔810之间的对齐。原因在于，所述纳米线间隔围绕整个纳米线材料形成。
在本发明实施方式中，纳米线材料可以是未掺杂的(掺杂浓度～5E15cm-3)，轻度掺杂的(掺杂浓度～5E17cm-3)，和重度掺杂的(掺杂浓度～1E19cm-3)。
牺牲层150,510的蚀刻可以是各向同性或各向异性的。各向同性的选择性蚀刻是优选的，因为能提供对齐的纳米线间隔。在各向异性蚀刻的情况中，例如，必须调节额外的牺牲层的厚度，才能产生相同的凹陷。这也适用于选择性氧化，该情况下氧化处理取决于牺牲层厚度。
间隔形成方法可包括选择性氧化步骤。该氧化步骤可以是各向同性的或各向异性的。在使用各向异性选择性蚀刻方案形成间隔的情况中，可通过匹配第一牺牲层150和额外的牺牲层510的尺寸来实现对齐，这是因为对于各向异性(即依赖晶体取向)蚀刻方法而言，由于沿着最慢的蚀刻晶面形成小平面，横向蚀刻深度取决于牺牲层尺寸。
在第二方面，本发明的实施方式涉及半导体器件，该半导体器件包括至少一个纳米线140，在纳米线140一侧的第一电极160，和围绕纳米线的控制电极。在控制电极和第一电极之间，存在在纳米线末端完全围绕纳米线的第一间隔。
该半导体器件可包括在纳米线相对于第一电极侧的一侧上的第二电极，以及在控制电极和第二电极之间的间隔。
在中间处理步骤中，依据本发明的实施方式，形成鳍片500，用于制备包含纳米线的半导体器件。该鳍片包括纳米线材料140和第一牺牲层150交替排列的堆叠。而且，在交替堆叠周围存在额外的牺牲层，这样在各纳米线的整个周围存在所得牺牲层。这种鳍片的一个例子示意性地如图5的右图所示。
根据本发明的实施方式，所述方法可以施加于不同纳米线器件结构。例子有Si，SiGe，Ge或III/V纳米线集成方案。
在纳米线材料140是Si的情况中，第一牺牲层150和额外的牺牲层510的材料可以是SiGe。牺牲层150，510的锗含量可以是例如10％-50％，或者甚至20％-50％，例如30％。
在本发明的其它实施方式中，纳米线材料140可以是SiGe。这些纳米线材料的锗含量可以是20％-50％，或者甚至25％-30％。在SiGe纳米线材料140的情况中，在纳米线材料140是Si的情况中，第一牺牲层150和额外的牺牲层510的材料可以是硅。在本发明的其它实施方式中，纳米线材料140可以是锗。例如，锗可以是应变或松弛的锗。在纳米线材料140是锗的情况中，第一牺牲层150和额外的牺牲层510的材料可以是SiGe。牺牲层150，510的锗含量可以是例如50％-80％，或者甚至50％-70％。在本发明的其它实施方式中，纳米线材料140可以是InGaAs。在纳米线材料140是InGaAs的情况中，第一牺牲层150和额外的牺牲层510的材料可以是InP。
本发明实施方式的一个优点在于纳米线可以相互堆叠。在本发明的实施方式中，顶部和底部纳米线可以来自不同类型(例如nMOS和pMOS)。例如，这可以用于形成CFET(补充FET)。在本发明的实施方式中，超过2个纳米线可以相互堆叠。
依据本发明实施方式的使用额外牺牲层用于形成水平纳米线的方法可用于制备pMOS，nMOS或组合pMOS/nMOS结构。

Claims (13)

1.一种形成包含水平纳米线的半导体器件的方法(400)，该方法包括：
-在基片上沉积(410)多层堆叠，所述多层堆叠包含交替的第一牺牲层(150)和纳米线材料(140)的层，
-在多层堆叠中形成(420)至少一个鳍片，
-围绕鳍片施加(430)额外的牺牲层(510)，使得所得的牺牲层(520)围绕整个纳米线材料形成，
-由所得的牺牲层(520)在纳米线材料的末端围绕纳米线材料形成(440)纳米线间隔(810)。
2.如权利要求1所述的方法，其特征在于，在施加额外的牺牲层(510)后，施加伪栅极堆叠(530,540)。
3.如上述权利要求中任一项所述的方法(400)，其特征在于，形成鳍片的步骤包括蚀刻或STI凹陷。
4.如上述权利要求中任一项所述的方法(400)，其特征在于，在形成纳米线间隔(810)的过程中，部分所得的牺牲层被选择性地除去。
5.如上述权利要求中任一项所述的方法(400)，其特征在于，部分所得的牺牲层被各向同性地除去。
6.如上述权利要求中任一项所述的方法(400)，其特征在于，使用保形沉积施加额外的牺牲层。
7.如权利要求2-6中任一项所述的方法，其特征在于，源极或漏极区域(160)紧邻纳米线间隔(810)施加，这样纳米线间隔(810)位于伪栅极(540)和源极或漏极区域(160)之间。
8.如上述权利要求中任一项所述的方法(400)，其特征在于，所述方法包括对所得的牺牲层(520)进行蚀刻，以得到纳米线(820)。
9.如权利要求8所述的方法(400)，其特征在于，所述方法包括围绕纳米线施加栅极堆叠。
10.一种半导体器件，所述半导体器件包括至少一个由纳米线材料制成的纳米线(820)，在纳米线(820)第一末端的第一电极(160)，以及围绕整个纳米线的控制电极，以及在控制电极和第一电极(160)之间的在纳米线第一末端围绕整个纳米线的第一间隔(810)。
11.如权利要求10所述的半导体器件，其特征在于，所述半导体器件包括在纳米线与第一末端相对的第二末端处的第二电极，以及在控制电极和第二电极之间的在纳米线第二末端围绕整个纳米线的第二间隔。
12.如权利要求10或11所述的半导体器件，其特征在于，所述纳米线材料包含至少一种选自Si和Ge的元素，或选自III-V化合物材料。
13.如权利要求10-12中任一项所述的半导体器件，其特征在于，所述纳米线材料是掺杂的。
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